CN217445252U

CN217445252U - Voltage reduction circuit equivalent to DC-DC converter and LDO combined circuit

Info

Publication number: CN217445252U
Application number: CN202221005443.6U
Authority: CN
Inventors: 杨元仁
Original assignee: Individual
Current assignee: Individual
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2022-09-16
Anticipated expiration: 2032-04-28

Abstract

The utility model discloses a voltage reduction circuit equivalent to a DC-DC converter and LDO combined circuit, which comprises a first output circuit, a second output circuit and a third output circuit, wherein the input voltage in the first output circuit is divided by a voltage reduction module to output the output voltage meeting the requirement, the second output end in the second output circuit is coupled with the first input end, the input voltage and the output voltage of the second output end are equal, after an input electric instrument of the second input end in the third output circuit passes through a pull-up resistor, an uncertain signal is clamped at a high level through a resistor, after the input electric instrument inputs a grid electrode of a first depletion type NMOS tube, the source electrode and the drain electrode are communicated, simultaneously, under the action of the grid electrode and the source electrode voltage, the conduction resistor between the source electrode and the drain electrode is changed, so that the pressure difference is generated between the source electrode and the drain electrode, and further the voltage meeting the requirement is output by the third output end, the DC-DC and LDO combined circuit can be replaced by a small number of electronic elements to achieve the same output effect.

Description

Voltage reduction circuit equivalent to DC-DC converter and LDO combined circuit

Technical Field

The utility model relates to a DC-DC converter and LDO equivalent circuit field especially relate to a step-down circuit equivalent with DC-DC converter and LDO combination formula circuit.

Background

A DC-DC converter (Direct current-Direct current converter) is a device that converts electric energy of one voltage value into electric energy of another voltage value in a Direct current circuit, and is constructed by assembling a small surface-mount integrated circuit and a microelectronic device into a whole by using a microelectronic technology.

Ldo (low dropout regulator), a low dropout linear regulator, uses a transistor or Field Effect Transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage.

In a combined circuit of a DC-DC converter circuit which needs to use two paths of 3.3V input voltages to respectively output 1.9V and 2.0V voltages and an LDO low dropout linear regulator circuit which needs to use one path of 3.3V input voltages to output 1.8V voltages, a DC-DC converter and an LDO low dropout linear regulator are often integrated into one circuit for use, so that the DC-DC converter and the LDO low dropout linear regulator are not only needed to be debugged in the use process of the combined circuit, but also the volume of a circuit board is increased by using a large number of electronic components, the production cost is greatly increased, and therefore, an equivalent circuit which can replace the DC-DC converter and the LDO combined circuit to achieve the same output effect by using a small number of electronic components is needed urgently.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a step-down circuit equivalent with DC-DC converter and LDO combined circuit to how only need to use a small amount of electronic components just can replace the combined circuit that needs two way defeated DC-DC converter circuits and LDO circuit all the way simultaneously among the solution above-mentioned background art, and reach the equivalent circuit's of the same output effect problem.

In order to solve the technical problems, the following technical scheme is proposed:

a buck circuit equivalent to a combined DC-DC converter and LDO circuit, comprising:

the first input end is coupled with one end of the voltage reduction module, the other end of the voltage reduction module is coupled with the first output end to form a first output loop, the second output end is coupled with a second output loop which is formed on the connection point of the first input end and the voltage reduction module, and the input voltage and the output voltage of the second output end are equal;

the control end is coupled to a grid electrode of the first depletion type NMOS tube and used for controlling the on-off of the first depletion type NMOS tube, the first input end is coupled with a drain electrode of the first depletion type NMOS tube, and a source electrode of the first depletion type NMOS tube is coupled with the third output end to form a third output loop.

Preferably, the power supply further comprises a first capacitor and a filter circuit module, wherein one end of the first capacitor is coupled to a connection point between the control terminal and the gate, the other end of the first capacitor is connected to one end of the filter circuit module, and the other end of the filter circuit module is coupled to the third output terminal.

Preferably, the filter circuit module includes a second capacitor and a third capacitor, one end of the second capacitor is coupled to the first capacitor, the other end of the second capacitor is coupled to the third output terminal, the third capacitor is connected in parallel to the second capacitor, and one end of the second capacitor, which is connected to the first capacitor, is grounded, where a capacity of the third capacitor is smaller than a capacity of the second capacitor.

Preferably, the control terminal includes a second input terminal and a pull-up resistor, the second input terminal is coupled to one end of the pull-up resistor, and the other end of the pull-up resistor is coupled to the gate.

Preferably, the depletion type NMOS transistor further comprises a second depletion type NMOS transistor, a drain of the second depletion type NMOS transistor is coupled with a drain of the first depletion type NMOS transistor, a source of the second depletion type NMOS transistor is coupled with a source of the first depletion type NMOS transistor, and a gate of the second depletion type NMOS transistor is coupled with a gate of the first depletion type NMOS transistor.

Preferably, the voltage-reducing module includes a voltage-reducing resistor, one end of the voltage-reducing resistor is coupled to the first input terminal, and the other end of the voltage-reducing resistor is coupled to the first output terminal.

Preferably, the depletion mode NMOS transistor further includes a fourth capacitor, a connection point between the drain of the first depletion mode NMOS transistor and the second input terminal is coupled to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.

Preferably, the circuit further comprises a fifth capacitor, one end of the fifth capacitor is coupled to the first output terminal, and the other end of the fifth capacitor is grounded.

Preferably, the circuit further comprises a sixth capacitor, one end of the sixth capacitor is coupled to the second output terminal, and the other end of the sixth capacitor is grounded.

Has the advantages that: the utility model discloses a voltage reduction circuit equivalent to a DC-DC converter and LDO combined circuit, in the application, 2V and 3.3V voltage are respectively input to a first input end and a second input end, and the first input end and the second input end are in the same network, so 2V voltage is equivalently output between the second input ends, 1.8V voltage is output at a second output end after the voltage input by the first input end passes through a voltage reduction resistor, a first depletion type NMOS tube is also arranged in the equivalent circuit, the voltage input by the second input end provides 3.3V high level for a grid electrode of the first depletion type NMOS tube through a pull-up resistor, a source electrode and a drain electrode of the first depletion type NMOS tube are conducted, meanwhile, under the combined action of the 3.3V voltage of the grid electrode and the 2V voltage of the source electrode, the conduction resistor between the source electrode and the drain electrode of the first depletion type NMOS tube is changed, and 0.1V differential pressure appears between the source electrode and the drain electrode of the first depletion type NMOS tube, and the third output end outputs 1.9V voltage, and the equivalent circuit replaces one path of LDO circuit which inputs 3.3V and outputs 1.8V and two paths of DC-DC circuits which input 3.3V and output 1.9V and 2V respectively, so that the requirement of power-on time sequence is met, the circuit size is greatly reduced, and the production cost is reduced.

Drawings

FIG. 1 is a circuit diagram of a conventional LDO circuit outputting 1.8V voltage after inputting 3.3V voltage;

FIG. 2 is a circuit diagram of a conventional DC-DC converter with an input voltage of 3.3V and an output voltage of 1.9V;

FIG. 3 is a circuit diagram of a conventional DC-DC converter with an input 3.3V voltage and an output 2V voltage;

fig. 4 is a circuit diagram of the present invention.

The main element symbols are as follows:

IN1, a first input; IN2, a second input terminal;

out1, a first output; out2, a second output terminal; out3, a third output terminal;

r1 and a voltage reduction resistor; r2, pull-up resistor;

c1, a first capacitor; c2, a second capacitor; c3, a third capacitance; c4, a fourth capacitance; c5, a fifth capacitance; c6, a sixth capacitor;

q1, a first depletion type NMOS tube; q2, second depletion type NMOS tube.

Detailed Description

To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the attached drawings in the embodiments of the present invention are combined to clearly and completely describe the technical solution in the embodiments of the present invention, and obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

The following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

In the prior art, as shown in fig. 1, in a conventional LDO circuit that outputs a voltage of 1.8V by inputting a voltage of 3.3V, after the voltage of 3.3V is input into the LDO circuit, the voltage of 1.8V is output through the LDO circuit, in fig. 2-3, the voltage of 3.3V is input into a DC-DC converter circuit, and voltages of 1.9V and 2V are output through the DC-DC converter circuit, respectively, when 3 sets of circuits shown in fig. 1-3 are integrated into the same circuit for use, not only the power-on timing between the circuits needs to be adjusted, but also one LDO low dropout linear regulator, two DC-DC converters, and a plurality of inductors, resistors, and capacitors need to be used in the circuit, which not only increases the volume of a PCB board for carrying the circuits, but also greatly increases the cost of the production circuit.

To solve the above problems, the present invention discloses a voltage reduction circuit equivalent to a combined circuit of a DC-DC converter and an LDO, referring to fig. 4, comprising a first input terminal IN1, a first output terminal out1, a second output terminal out2, a third output terminal out3, a voltage reduction module, a control terminal and a first depletion type NMOS transistor Q1,

the first input end IN1 inputs 2V voltage, the input end of the voltage-reducing module is connected with the first input end IN1, the output end of the voltage-reducing module is connected with the first output end out1 to form a first output loop, the first output end out1 outputs 1.8V voltage after passing through the voltage-reducing module, the voltage-reducing module generates 0.2V voltage reduction, the connection point of the input end of the voltage-reducing module and the first input end IN1 is also connected with the second output end out2, because the first input end IN1 and the second output end 2 are IN the same network, the first input end IN1 and the second output end out2 are equivalent input and output, the second output end out2 outputs 2V voltage, the first input end IN1 is also coupled with the drain of the first depletion type NMOS transistor Q1, the source of the first depletion type NMOS transistor Q1 is coupled with the third output end out3, and the gate of the first depletion type NMOS transistor Q1 is coupled with the control end;

the control end is used for controlling the conduction of a first depletion type NMOS tube Q1, the control end inputs a high level of 3.3V to the grid electrode of the first depletion type NMOS tube, so that the source electrode and the drain electrode of the first depletion type NMOS tube are communicated, and under the combined action of 3.3V voltage input to the grid electrode and 2V voltage of the source electrode, the magnitude of differential pressure between the source electrode and the drain electrode is changed, so that differential pressure of 0.1V is generated between the source electrode and the drain electrode, and further, the third output end outputs 1.9V voltage; by using a small number of electronic components, the same output effect of a combined circuit of the existing DC-DC converter circuit with two paths of input 3.3V voltages respectively outputting 1.9V and 2.0V voltages and the LDO circuit with one path of input 3.3V voltage outputting 1.8V voltage is achieved, a voltage reduction module, a first depletion type NMOS tube, a control end and other small numbers of electronic components are used, the size of a circuit board is greatly reduced, the production cost is reduced, and the power-on time sequence does not need to be debugged in the use process.

In this embodiment, the circuit further includes a first capacitor C1 and a filter circuit module, wherein one end of the first capacitor C1 is coupled to a connection point of the control terminal and the gate, the other end of the first capacitor C1 is connected to one end of the filter circuit module, and the other end of the filter circuit module is coupled to the third output terminal.

In this embodiment, the filter circuit includes a second capacitor C2 and a third capacitor C3, one end of the second capacitor C2 is coupled to a connection point of the gate and the pull-up resistor R2, the other end is coupled to the third output end out3, the third capacitor C3 is connected in parallel to the second capacitor C2, and the capacity of the third capacitor C3 is smaller than that of the second capacitor C2, wherein the second capacitor with large capacity can allow low-frequency signals to easily pass through, and the third capacitor with small capacity allows high-frequency signals to easily pass through, so that the second capacitor is used for filtering high-frequency signals during use, and the third capacitor is used for filtering low-frequency signals.

IN this embodiment, the control terminal includes a second input terminal IN2 and a pull-up resistor R2, the second input terminal is coupled to one end of the pull-up resistor R2, and the other end of the pull-up resistor R2 is coupled to the gate, where the pull-up resistor is used to clamp an indeterminate signal at a high level through a resistor after a voltage of 3.3V input by the second input terminal passes through the pull-up resistor, so that the gate of the first depletion type NMOS transistor is input at the high level, and the pull-up resistor also plays a role IN current limiting.

In this embodiment, the depletion type NMOS transistor Q2 is further included, a drain of the second depletion type NMOS transistor Q2 is coupled to a drain of the first depletion type NMOS transistor Q1, a source of the second depletion type NMOS transistor Q2 is coupled to a source of the first depletion type NMOS transistor Q1, a gate of the second depletion type NMOS transistor Q2 is coupled to a gate of the first depletion type NMOS transistor Q1, two groups of parallel depletion type NMOS transistors are arranged in the circuit to shunt current in the circuit, when current sharing is performed among the depletion type NMOS transistors, when current in one of the depletion type NMOS transistors is greater than current in the other depletion type NMOS transistor, the depletion type NMOS transistor with large current generates more heat, thereby causing an increase in on-resistance, thereby reducing current flowing through the depletion type NMOS transistor, and current balancing between the two depletion type NMOS transistors is achieved by repeatedly adjusting between the two groups of parallel depletion type NMOS transistors according to different current magnitudes, thereby increasing the output load current.

IN this embodiment, the voltage-reducing module includes a voltage-reducing resistor R1, one end of the voltage-reducing resistor R1 is coupled to the first input terminal IN1, and the other end of the voltage-reducing resistor R1 is coupled to the first output terminal out1, the voltage of the input 2V of the first input terminal IN1 generates a voltage division of 0.2V after passing through the voltage-reducing resistor R1, so that the first output terminal outputs a voltage of 1.8V, and the purpose of reducing the input voltage of the first input terminal IN1 to a desired voltage by using only a small number of electronic components is achieved.

IN this embodiment, the voltage regulator further includes a fourth capacitor C4, the fourth capacitor C4 is a filter capacitor, a connection point between the drain of the first depletion NMOS transistor Q1 and the second input terminal IN2 is coupled to one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is grounded, so that the voltage of the drain of the first input terminal is a stable dc voltage after being filtered by the fourth capacitor.

In this embodiment, the load further includes a fifth capacitor C5, the fifth capacitor C5 is used as a filtering decoupling capacitor, the capacity of the fifth capacitor C5 is 10UF, the capacitor withstand voltage is 10V, and the capacity error is 20%, one end of the fifth capacitor C5 is coupled to the first output end out1, and the other end of the fifth capacitor C5 is grounded, so that the voltage output by the filtered first output end out1 is a stable dc voltage, and further, the load operation is more stable.

In this embodiment, the load further includes a sixth capacitor C6, the sixth capacitor C6 is used as a filtering decoupling capacitor, one end of the sixth capacitor C6 is coupled to the second output terminal out2, and the other end of the sixth capacitor C6 is grounded, so that the voltage output by the second output terminal out2 after filtering is a stable dc voltage, and thus the load operation is more stable.

The utility model discloses a theory of operation does:

the first output loop is characterized in that 2V voltage input by the first input end passes through the voltage reduction resistor and is divided by the voltage reduction resistor, so that 0.2V voltage reduction is generated, the first output end outputs 1.8V voltage, meanwhile, the first output end is coupled with a fifth capacitor with one grounded end, and current output by the first output end is filtered through the fifth capacitor, so that the first output end outputs 1.8V voltage which is stable direct current voltage;

a second output loop, wherein the second output end is coupled with the connection point of the first input end and the voltage-reducing resistor, so that the voltage output by the second output end is equal to the input voltage of the first input end, namely the output voltage of the second output end is 2V, meanwhile, the second output end is coupled with a sixth capacitor with one end grounded, and the voltage output by the second output end is filtered by the sixth capacitor, so that the 2V voltage output by the second output end is a stable direct-current voltage;

a third output loop, wherein the second input end inputs 3.3V voltage, when the voltage input at the second input end passes through a pull-up resistor, the pull-up resistor clamps uncertain signals at high level through a resistor, so that the high level is input to the grids of the first depletion type NMOS tube and the second depletion type NMOS tube, the source electrodes and the drain electrodes of the first depletion type NMOS tube and the second depletion type NMOS tube are controlled to be communicated, the on-resistance between the source electrode and the drain electrode is changed under the combined action of the 3.3V voltage input to the grid electrode and the 2V voltage of the source electrode, so that a differential pressure difference of 0.1V is generated between the source electrode and the drain electrode, and further the third output end outputs 1.9V voltage, meanwhile, a pull-up resistor R2 and a first capacitor C1 form an RC delay network for adjusting power-on time sequence, and secondly, the first depletion type NMOS tube and the second depletion type NMOS tube are two depletion type NMOS tubes connected in parallel, so as to shunt current in the circuit, when the depletion type NMOS tubes carry out current sharing, when one of the current is larger than the current in the other MOS tube, the heat generated by the MOS tube with large current is large, so that the on-resistance is increased, the current flowing through the MOS tube is reduced, the current is repeatedly adjusted according to the difference of the current between the two parallel depletion type NMOS tubes, the current balance between the two depletion type NMOS tubes is realized, and the output load current is increased.

The above disclosure is only for the specific embodiments of the present invention, but the present invention is not limited thereto, and any changes that can be made by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A buck circuit equivalent to a combined DC-DC converter and LDO circuit, comprising:

the first input end is coupled with one end of the voltage reduction module, the other end of the voltage reduction module is coupled with the first output end to form a first output loop, the second output end is coupled with a connecting point of the first input end and the voltage reduction module to form a second output loop, and the input voltage and the output voltage of the second output end are equal;

2. The buck circuit equivalent to a combined DC-DC converter and LDO circuit of claim 1, further comprising a first capacitor and a filter circuit module, wherein one end of the first capacitor is coupled to a connection point of the control terminal and the gate of the first depletion type NMOS transistor, the other end of the first capacitor is connected to one end of the filter circuit module, and the other end of the filter circuit module is coupled to the third output terminal.

3. The buck circuit equivalent to a combined DC-DC converter and LDO circuit of claim 2, wherein the filter circuit module comprises a second capacitor and a third capacitor, one end of the second capacitor is coupled to the first capacitor, the other end of the second capacitor is coupled to the third output terminal, the third capacitor is connected in parallel with the second capacitor, and one end of the second capacitor is connected to ground, wherein the third capacitor has a smaller capacitance than the second capacitor.

4. The buck circuit equivalent to a combined DC-DC converter and LDO circuit of claim 2, wherein the control terminal comprises a second input terminal and a pull-up resistor, the second input terminal is coupled to one end of the pull-up resistor, and the other end of the pull-up resistor is coupled to the gate of the first depletion type NMOS transistor.

5. The buck circuit equivalent to a combined DC-DC converter and LDO circuit of claim 1, further comprising a second depletion type NMOS transistor, wherein a drain of the second depletion type NMOS transistor is coupled to a drain of the first depletion type NMOS transistor, a source of the second depletion type NMOS transistor is coupled to a source of the first depletion type NMOS transistor, and a gate of the second depletion type NMOS transistor is coupled to a gate of the first depletion type NMOS transistor.

6. The buck circuit equivalent to a combined DC-DC converter and LDO circuit of claim 1, wherein the buck module comprises a buck resistor, one end of the buck resistor being coupled to the first input terminal and the other end of the buck resistor being coupled to the first output terminal.

7. The buck circuit equivalent to a combined DC-DC converter and LDO circuit of claim 4, further comprising a fourth capacitor, wherein a connection point of the drain of the first depletion type NMOS transistor and the second input terminal is coupled to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.

8. The buck circuit equivalent to the combined DC-DC converter and LDO circuit of claim 7, further comprising a fifth capacitor, wherein one end of the fifth capacitor is coupled to the first output terminal, and the other end of the fifth capacitor is grounded.

9. The buck circuit equivalent to a combined DC-DC converter and LDO circuit of claim 8, further comprising a sixth capacitor, wherein one end of the sixth capacitor is coupled to the second output terminal, and the other end of the sixth capacitor is grounded.