CN217406403U

CN217406403U - Drive circuit, power management device, and electronic apparatus

Info

Publication number: CN217406403U
Application number: CN202220650828.1U
Authority: CN
Inventors: 张凯; 聂健波; 赵密
Original assignee: Shenzhen Zhenghao Zhizao Technology Co ltd
Current assignee: Shenzhen Zhenghao Zhizao Technology Co ltd
Priority date: 2022-03-23
Filing date: 2022-03-23
Publication date: 2022-09-09
Anticipated expiration: 2032-03-23

Abstract

The application relates to a drive circuit, a power management device and an electronic apparatus. The drive circuit of MOS pipe includes: the circuit comprises a first anti-reverse circuit, a second anti-reverse circuit, a first voltage division circuit, a second voltage division circuit, a switch circuit and a first bleeder circuit; the first end of the first voltage division circuit is used for receiving a driving signal of the MOS tube; the voltage division of the second anti-reverse circuit is the same as that of the first anti-reverse circuit, so that the voltage division of the second voltage division circuit is equal to the voltage difference between the source electrode and the grid electrode of the MOS tube; the switch circuit is used for being in a cut-off state when the driving signal is a turn-on signal and being in a turn-on state when the driving signal is a turn-off signal. According to the MOS transistor protection circuit, the switch-off of the MOS transistor can be accelerated through the switch circuit and the first discharge circuit, the MOS transistor is protected, and the voltage of the grid electrode of the MOS transistor can be quickly and accurately adjusted through voltage adjustment of the second voltage division circuit through the first anti-reverse circuit and the second anti-reverse circuit.

Description

Drive circuit, power management device, and electronic apparatus

Technical Field

The application belongs to the technical field of power switches, and particularly relates to a driving circuit, a power management device and electronic equipment.

Background

A BATTERY is a very common energy storage device, and a conventional BATTERY pack or BATTERY module includes a BATTERY assembly and a BMS (BATTERY management system) for managing the BATTERY assembly, and generally, the BMS includes a control chip and a switching MOS transistor disposed on a charging or discharging loop (charging and discharging may be the same circuit) of the BATTERY assembly. When the MOS transistor is turned off, the gate voltage of the MOS transistor needs to be discharged through the discharge resistor, and a certain time is required in the process, so that the switching MOS transistor may not be turned off quickly. Especially when the charging current/discharging current is relatively large, if the turn-off time of the switch MOS tube is too long, the switch MOS tube possibly exceeds the safe working window of the switch MOS tube, so that the switch MOS tube is damaged by thermal breakdown, and the switch MOS tube directly loses the protection function. Meanwhile, due to the fact that a plurality of discharge resistors need to be arranged, the grid voltage of the MOS tube can be divided, and the grid voltage of the MOS tube cannot be accurately controlled.

Therefore, the conventional technical scheme has the problems that the turn-off time of the switching MOS tube is too long and the grid voltage of the MOS tube is difficult to control.

SUMMERY OF THE UTILITY MODEL

The present application aims to provide a driving circuit, a power management device and an electronic apparatus, and aims to solve the problems of a conventional switching MOS transistor that the turn-off time is too long and the gate voltage of the MOS transistor is difficult to control.

A first aspect of an embodiment of the present application provides a driving circuit of a MOS transistor, including: the first anti-reverse circuit, the second anti-reverse circuit, the first voltage division circuit, the second voltage division circuit, the switch circuit and the first bleeder circuit; the first end of the first voltage division circuit is used for receiving a driving signal of the MOS tube; the positive electrode of the first anti-reverse circuit is connected with the second end of the first voltage division circuit, the negative electrode of the first anti-reverse circuit is connected with the first end of the switch circuit, and the negative electrode of the first anti-reverse circuit is also used for being connected with the grid electrode of the MOS tube; the positive electrode of the second anti-reverse circuit is connected with the positive electrode of the first anti-reverse circuit, and the negative electrode of the second anti-reverse circuit is connected with the source electrode of the MOS tube after being connected with the second voltage division circuit in series; the negative electrode of the second anti-reverse circuit is also connected with the control end of the switch circuit; the second end of the switch circuit is connected to the source electrode of the MOS tube after being connected in series with the first bleeder circuit; the voltage division of the second anti-reverse circuit is the same as that of the first anti-reverse circuit, so that the voltage division of the second voltage division circuit is equal to the voltage difference between the source and the gate of the MOS tube; the switch circuit is used for being in a cut-off state when the driving signal is a turn-on signal and being in a turn-on state when the driving signal is a turn-off signal.

In one embodiment, the circuit further comprises a second bleeder circuit; the second bleeder circuit is arranged between the source electrode and the grid electrode of the MOS tube.

In one embodiment, the impedance of the first bleeder circuit is smaller than the impedance of the second bleeder circuit.

In one embodiment, the first bleeding circuit includes a first bleeding resistor, and the second bleeding circuit includes a second bleeding resistor; the first bleed resistor is connected between a first end of the first bleed circuit and a second end of the first bleed circuit; the second bleed off resistor is connected between the first end of the second bleed off circuit and the second end of the second bleed off circuit; the resistance value of the first bleeder resistor is smaller than that of the second bleeder resistor.

In one embodiment, the MOS transistor is an NMOS transistor; the switching circuit comprises a PNP switching tube, an emitting electrode of the PNP switching tube is connected with a first end of the switching circuit, a base electrode of the PNP switching tube is connected with a control end of the switching circuit, and a collector electrode of the PNP switching tube is connected with a second end of the switching circuit.

In one embodiment, the first anti-reverse circuit comprises a first anti-reverse diode, and the second anti-reverse circuit comprises a second anti-reverse diode; the positive electrode of the first anti-reverse diode is connected with the positive electrode of the first anti-reverse circuit, and the negative electrode of the first anti-reverse diode is connected with the negative electrode of the first anti-reverse circuit; the positive pole of the second anti-reverse diode is connected with the positive pole of the second anti-reverse circuit, and the negative pole of the second anti-reverse diode is connected with the negative pole of the second anti-reverse circuit.

In one embodiment, the device further comprises a voltage stabilizing circuit; the voltage stabilizing circuit is arranged between the grid electrode of the MOS tube and the source electrode of the MOS tube and used for stabilizing the voltage of the grid electrode of the MOS tube.

In one embodiment, the power supply further comprises a current limiting circuit, and the gate of the MOS transistor is connected to the first anti-reverse circuit, the second bleeder circuit and the switch circuit through the current limiting circuit respectively.

A second aspect of the embodiments of the present application provides a power management device, including a main control circuit, an MOS transistor, and a driving circuit of the MOS transistor as described above, where the MOS transistor is used as a charging switching transistor or a discharging switching transistor and is connected in series in a target power supply loop; the main control circuit is connected with the first voltage division circuit and used for outputting the driving signal so as to control the conduction and the cut-off of the MOS tube.

A third aspect of the embodiments of the present application provides an electronic device, including a power supply and the power supply management apparatus as described above.

Compared with the prior art, the embodiment of the application has the advantages that:

1. when the drive circuit receives a turn-off signal to turn off the MOS tube, the switch circuit can be synchronously switched on, and the voltage discharge of the grid electrode of the MOS tube is accelerated through the switch circuit and the first discharge circuit, so that the MOS tube is quickly turned off, the MOS tube is prevented from being punctured, and the MOS tube is protected.

2. Because the conduction voltage drops of the first anti-reverse circuit and the second anti-reverse circuit are the same, and the anode of the first anti-reverse circuit is connected with the anode of the second anti-reverse circuit, the voltage of the cathode of the second anti-reverse circuit can be adjusted by configuring the resistance value of the second voltage division circuit, namely the voltage of the cathode of the first anti-reverse circuit is adjusted, so that the voltage of the grid of the MOS tube can be quickly and accurately adjusted.

Drawings

Fig. 1 is a schematic diagram of a driving circuit according to a first embodiment of the present application;

fig. 2 is a detailed schematic diagram of a driving circuit according to a first embodiment of the present application;

fig. 3 is a circuit configuration diagram of a driving circuit according to a first embodiment of the present application;

fig. 4 is a schematic diagram of a power management device according to a second embodiment of the present application;

fig. 5 is a schematic diagram of an electronic device according to a third embodiment of the present application.

The drawings described above illustrate: 100. a drive circuit; 110. an MOS tube; 121. a first anti-reverse circuit; 122. a second anti-reverse circuit; 131. a first voltage dividing circuit; 132. a second voltage dividing circuit; 140. a switching circuit; 151. a first bleed circuit; 152. a second bleed circuit; 160. a voltage stabilizing circuit; 170. a current limiting circuit; 200. a master control circuit; 300. a power source; 400. a voltage conversion circuit; 50. and (4) an external device.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings to facilitate the description of the application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be constructed in operation as a limitation of the application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 1 shows a schematic diagram of a driving circuit provided in a first embodiment of the present application, and for convenience of illustration, only the parts related to this embodiment are shown, and detailed descriptions are as follows:

a driving circuit of a MOS transistor 110 comprises: the first anti-reverse circuit 121, the second anti-reverse circuit 122, the first voltage divider circuit 131, the second voltage divider circuit 132, the switch circuit 140, and the first bleeding circuit 151. The first terminal of the first voltage dividing circuit 131 is used for receiving the driving signal of the MOS transistor 110. The positive electrode of the first anti-reflection circuit 121 is connected to the second end of the first voltage division circuit 131, the negative electrode of the first anti-reflection circuit 121 is connected to the first end of the switch circuit 140, and the negative electrode of the first anti-reflection circuit 121 is further used for being connected to the gate of the MOS transistor 110. The positive electrode of the second anti-reverse circuit 122 is connected to the positive electrode of the first anti-reverse circuit 121, and the negative electrode of the second anti-reverse circuit 122 is connected to the source of the MOS transistor 110 after being connected in series with the second voltage dividing circuit 132. The cathode of the second anti-reverse circuit 122 is also connected to the control terminal of the switch circuit 140. The second terminal of the switching circuit 140 is connected in series with the first bleeder circuit 151 and then connected to the source of the MOS transistor 110.

In this embodiment, the MOS transistor 110 may be disposed between the power supply and the electrical device as a power switch, so that when the MOS transistor 110 is turned on, the power supply may supply power to the electrical device through the MOS transistor 110, and when the MOS transistor 110 is turned off, the power supply stops supplying power to the electrical device.

The voltage division of the second anti-reverse circuit 122 is the same as that of the first anti-reverse circuit 121, so that the voltage division of the second voltage division circuit 132 is equal to the voltage difference between the source and the gate of the MOS transistor 110. The switch circuit 140 is configured to be in an off state when the driving signal is an on signal, and to be in an on state when the driving signal is an off signal. Specifically, the MOS transistor 110 may be an NMOS transistor Q1, where the on signal is a high level signal and the off signal is a low level signal. Therefore, when the MOS transistor 110 changes from the on state to the off state, the voltage of the gate of the MOS transistor 110 needs to change from the high level to the low level, and the switch circuit 140 can be turned on at this time to accelerate the voltage change of the gate of the MOS transistor 110.

The voltage leakage of the gate of the MOS transistor 110 can be accelerated by the switch circuit 140 and the first leakage circuit 151, so that the MOS transistor 110 is turned off quickly, the MOS transistor 110 is prevented from being broken down, and the MOS transistor 110 is protected.

As shown in fig. 2 and fig. 3, in the embodiment, the switch circuit 140 includes a PNP switch Q2, an emitter of the PNP switch Q2 is connected to the first end of the switch circuit 140, a base of the PNP switch Q2 is connected to the control end of the switch circuit 140, and a collector of the PNP switch Q2 is connected to the second end of the switch circuit 140.

It should be noted that the response speed of the transistor is faster than that of the MOS transistor 110, so that the switch circuit 140 can be turned on quickly when the base voltage changes from high level (turn-on signal) to low level (turn-off signal).

The first anti-reverse circuit 121 and the second anti-reverse circuit 122 can prevent the current from flowing backwards, and meanwhile, since the conduction voltage drops of the first anti-reverse circuit 121 and the second anti-reverse circuit 122 are the same, and the positive electrode of the first anti-reverse circuit 121 is connected with the positive electrode of the second anti-reverse circuit 122, the voltage of the second voltage division circuit 132 can be adjusted by configuring the resistance ratio of the first voltage division circuit 131 to the second voltage division circuit 132, so that the effect of adjusting the voltage of the negative electrode of the second anti-reverse circuit 122 is achieved, that is, the voltage of the negative electrode of the first anti-reverse circuit 121 is adjusted, so that the voltage of the gate of the MOS transistor 110 can be rapidly and accurately configured when the driving signal is the conduction signal.

As shown in fig. 2 and fig. 3, in the present embodiment, the driving circuit of the MOS transistor 110 further includes a second bleeder circuit 152. The second bleeder circuit 152 is disposed between the source and the gate of the MOS transistor 110. The second bleeder circuit 152 may also accelerate the voltage bleeder of the gate of the MOS transistor 110 when the MOS transistor 110 changes from the on state to the off state, so that the MOS transistor 110 can be turned off quickly.

In this embodiment, the impedance of the first bleeding circuit 151 is smaller than the impedance of the second bleeding circuit 152. The first bleeding circuit 151 is only used for bleeding the voltage of the gate of the MOS transistor 110, so the impedance of the first bleeding circuit 151 may be small to speed up the bleeding of the voltage.

As shown in fig. 2 and 3, in particular, the first bleeder circuit 151 includes a first bleeder resistor R3, and the second bleeder circuit 152 includes a second bleeder resistor R4. First bleeder resistor R3 is connected between a first end of first bleeder circuit 151 and a second end of first bleeder circuit 151. The second bleed resistor R4 is connected between the first end of the second bleed circuit 152 and the second end of the second bleed circuit 152. The resistance value of the first bleeder resistor R3 is smaller than the resistance value of the second bleeder resistor R4.

Specifically, the first anti-reverse circuit 121 includes a first anti-reverse diode D1, and the second anti-reverse circuit 122 includes a second anti-reverse diode D2. The anode of the first anti-reverse diode D1 is connected to the anode of the first anti-reverse circuit 121, and the cathode of the first anti-reverse diode D1 is connected to the cathode of the first anti-reverse circuit 121. The anode of the second anti-reverse diode D2 is connected to the anode of the second anti-reverse circuit 122, and the cathode of the second anti-reverse diode D2 is connected to the cathode of the second anti-reverse circuit 122.

Specifically, the first voltage-dividing circuit 131 includes a first voltage-dividing resistor R1, and the second voltage-dividing circuit 132 includes a second voltage-dividing resistor R2. The first voltage dividing resistor R1 is connected between the first end of the first voltage dividing circuit 131 and the second end of the first voltage dividing circuit 131. The second voltage dividing resistor R2 is connected between the first terminal of the second voltage dividing circuit 132 and the second terminal of the second voltage dividing circuit 132. The effect of configuring the gate voltage of the MOS transistor 110 can be achieved by configuring the resistances of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2.

As shown in fig. 2 and fig. 3, in this embodiment, the driving circuit of the MOS transistor 110 further includes a voltage stabilizing circuit 160. The voltage stabilizing circuit 160 is disposed between the gate of the MOS transistor 110 and the source of the MOS transistor 110, for stabilizing the voltage of the gate of the MOS transistor 110.

Specifically, the voltage stabilizing circuit 160 includes a zener diode D3, the anode of the zener diode D3 is connected to the source of the MOS transistor 110, and the cathode of the zener diode D3 is connected to the gate of the MOS transistor 110. When the voltage of the gate of the MOS transistor 110 is too large, the zener diode D3 may be broken down, so that the gate of the MOS transistor 110 is communicated with the source of the MOS transistor 110, so as to reduce the voltage of the gate of the MOS transistor 110, and implement protection on the MOS transistor 110.

As shown in fig. 2 and fig. 3, in this embodiment, the driving circuit of the MOS transistor 110 further includes a current limiting circuit 170, and the gate of the MOS transistor 110 is connected to the first anti-inversion circuit 121, the second bleeder circuit 152, and the switch circuit 140 through the current limiting circuit respectively.

The current limiting circuit 170 includes a current limiting resistor R5, a first end of the current limiting resistor R5 is connected to the gate of the MOS transistor 110, and a second end of the current limiting resistor R5 is connected to the negative electrode of the first anti-reverse circuit 121, the first end of the second bleeder circuit 152, and the first end of the switch circuit 140.

Fig. 4 shows a schematic diagram of a power management device provided in a second embodiment of the present application, and for convenience of description, only the parts related to this embodiment are shown, and detailed descriptions are as follows:

a power management device comprises a main control circuit 200, a MOS tube 110 and a drive circuit 100 as in the above embodiment, wherein the MOS tube 110 is connected in series in a target power supply loop as a charging switch tube or a discharging switch tube. The main control circuit 200 is connected to the first voltage dividing circuit 131, and is configured to output a driving signal to control the MOS transistor 110 to be turned on and off.

Fig. 5 shows a schematic diagram of an electronic device provided in the third embodiment, and for convenience of description, only the parts related to this embodiment are shown, which are detailed as follows:

an electronic device comprises a power supply 300 and a power supply circuit, the electronic device can be an energy storage device, and the power supply 300 can be an energy storage battery. Specifically, the electronic device further includes a voltage conversion circuit 400 disposed on the power supply loop and the power management apparatus according to the above-described embodiment for controlling on/off of the power supply loop. Specifically, a first terminal of the voltage conversion circuit 400 is connected to a first terminal of the power supply 300, a second terminal of the voltage conversion circuit 400 is configured to be connected to a first power terminal of the external device 50, a drain of the MOS transistor 110 is connected to a second terminal of the power supply 300, and a source of the MOS transistor 110 is configured to be connected to a second power terminal of the external device 50. The MOS transistor 110 is used as a power switch, and when the MOS transistor 110 is turned on, the power supply 300 can be controlled to supply power to the external device 50, and when the MOS transistor 110 is turned off, the power supply 300 can be controlled to stop supplying power to the external device 50.

In another embodiment, the power supply 300 may also be a power adapter for connecting to a power grid, the MOS transistor 110 is used for controlling power input of the power grid, and the electronic device may also be a power-consuming device. The present embodiment does not limit the type of the electronic device and the power supply 300.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. In addition, specific names of the functional units and modules are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the present application. For the specific working processes of the units and modules in the system, reference may be made to the corresponding processes in the foregoing method embodiments, which are not described herein again.

In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A driving circuit of a MOS transistor is characterized by comprising: the first anti-reverse circuit, the second anti-reverse circuit, the first voltage division circuit, the second voltage division circuit, the switch circuit and the first bleeder circuit;

the first end of the first voltage division circuit is used for receiving a driving signal of the MOS tube;

the positive electrode of the first anti-reverse circuit is connected with the second end of the first voltage division circuit, the negative electrode of the first anti-reverse circuit is connected with the first end of the switch circuit, and the negative electrode of the first anti-reverse circuit is also used for being connected with the grid electrode of the MOS tube;

the positive electrode of the second anti-reverse circuit is connected with the positive electrode of the first anti-reverse circuit, and the negative electrode of the second anti-reverse circuit is connected with the source electrode of the MOS tube after being connected with the second voltage division circuit in series; the negative electrode of the second anti-reverse circuit is also connected with the control end of the switch circuit;

the second end of the switch circuit is connected to the source electrode of the MOS tube after being connected in series with the first bleeder circuit;

the voltage division of the second anti-reverse circuit is the same as that of the first anti-reverse circuit, so that the voltage division of the second voltage division circuit is equal to the voltage difference between the source and the gate of the MOS tube; the switch circuit is used for being in a cut-off state when the driving signal is a turn-on signal and being in a turn-on state when the driving signal is a turn-off signal.

2. The driving circuit of the MOS transistor according to claim 1, further comprising a second bleeder circuit; the second bleeder circuit is arranged between the source electrode and the grid electrode of the MOS tube.

3. The driving circuit of a MOS transistor as claimed in claim 2, wherein the impedance of the first bleeder circuit is smaller than the impedance of the second bleeder circuit.

4. The driving circuit of the MOS transistor according to claim 2 or 3, wherein the first bleeder circuit comprises a first bleeder resistor, and the second bleeder circuit comprises a second bleeder resistor; the first bleed resistor is connected between the first end of the first bleed circuit and the second end of the first bleed circuit; the second bleed resistor is connected between the first end of the second bleed circuit and the second end of the second bleed circuit; the resistance value of the first bleeder resistor is smaller than that of the second bleeder resistor.

5. The driving circuit of the MOS transistor according to any of claims 1 to 3, wherein the MOS transistor is an NMOS transistor; the switching circuit comprises a PNP switching tube, an emitting electrode of the PNP switching tube is connected with a first end of the switching circuit, a base electrode of the PNP switching tube is connected with a control end of the switching circuit, and a collector electrode of the PNP switching tube is connected with a second end of the switching circuit.

6. The driving circuit of a MOS transistor according to any one of claims 1 to 3, wherein the first anti-reverse circuit comprises a first anti-reverse diode, and the second anti-reverse circuit comprises a second anti-reverse diode;

the positive electrode of the first anti-reverse diode is connected with the positive electrode of the first anti-reverse circuit, and the negative electrode of the first anti-reverse diode is connected with the negative electrode of the first anti-reverse circuit; the positive pole of the second anti-reverse diode is connected with the positive pole of the second anti-reverse circuit, and the negative pole of the second anti-reverse diode is connected with the negative pole of the second anti-reverse circuit.

7. The driving circuit of MOS transistor according to any of claims 1 to 3, further comprising a voltage stabilizing circuit; the voltage stabilizing circuit is arranged between the grid electrode of the MOS tube and the source electrode of the MOS tube and used for stabilizing the voltage of the grid electrode of the MOS tube.

8. The driving circuit of the MOS transistor according to claim 2 or 3, further comprising a current limiting circuit, wherein a gate of the MOS transistor is connected to the first anti-reverse circuit, the second bleeder circuit, and the switch circuit through the current limiting circuit, respectively.

9. A power management device, comprising a master control circuit, a MOS transistor and a driving circuit of the MOS transistor according to any one of claims 1 to 8, wherein the MOS transistor is connected in series in a target power supply loop as a charging switch transistor or a discharging switch transistor; the main control circuit is connected with the first voltage division circuit and used for outputting the driving signal so as to control the conduction and the cut-off of the MOS tube.

10. An electronic device comprising a power supply and the power management apparatus of claim 9.