CN217386347U - Watchdog system - Google Patents
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- CN217386347U CN217386347U CN202221328393.5U CN202221328393U CN217386347U CN 217386347 U CN217386347 U CN 217386347U CN 202221328393 U CN202221328393 U CN 202221328393U CN 217386347 U CN217386347 U CN 217386347U
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Abstract
The application provides a watchdog system, includes: the system comprises a processing module, a watchdog module and a first pull-down module; the processing module is used for connecting a first pin externally connected with the simulator with the first pull-down module, the first pin is also connected with an enabling pin of the watchdog module, when the first pin is not externally connected with the simulator, the first pull-down module pulls down the level of the first pin to be the enabling level of the watchdog, the enabling pin receives the enabling level, and the watchdog module works normally; when the first pin is externally connected with the simulator, the first pull-down module pulls down the level of the first pin to be the closing level of the watchdog, the enabling pin receives the closing level, and the watchdog module stops working. According to the scheme, when the processing module writes the program in a programming mode, the watchdog receives the closing level, and the watchdog cannot send the reset instruction to the processing module even if the watchdog does not receive the dog feeding signal, so that the normal programming of the program of the processing module is realized.
Description
Technical Field
The application belongs to the field of electronic circuits, and particularly relates to a watchdog system.
Background
The electronic product is widely applied to various industries, and a watchdog system is arranged in the electronic product and comprises a processing module and a watchdog module, wherein the processing module is provided with a control program to control the action of the electronic product. The processing module often cannot work normally due to reasons such as the running of the control program, and for this reason, the watchdog module is required to restart the processing module so as to enable the processing module to work normally.
In the related technology, when the processing module works normally, a dog feeding signal is sent to the dog feeding module at regular time, and when the dog feeding module does not receive the dog feeding signal within the dog feeding time, the processing module is restarted if the processing module does not work normally.
However, in the related art, when the emulator program is inserted into the processing module, the processing module does not send out the dog feeding signal, so that the dog feeding module may mistakenly consider that the processing module does not normally operate, and send out the restart instruction to the processing module, thereby failing to realize normal program writing of the processing module program.
SUMMERY OF THE UTILITY MODEL
The application provides a watchdog system, aiming at solving the problem that the processing module cannot be normally programmed.
The application provides a watchdog system, includes: the system comprises a processing module, a watchdog module and a first pull-down module; the processing module comprises a first pin, and the first pin is externally connected with a simulator for programming the processing module; the first pull-down module is connected with the first pin and used for pulling down the level of the first pin to be the enabling level of the watchdog module when the first pin is not externally connected with a simulator; when the first pin is externally connected with the simulator, the level at the first pin is pulled down to be the closing level of the watchdog module; the first pin is connected with an enabling pin of the watchdog module, wherein the enabling pin is used for controlling the watchdog module to work when receiving the enabling level; and controlling the watchdog module to stop working when receiving the closing level.
Optionally, the processing module further includes: a second pin; the second pin is used for outputting the enabling level when the processing module works and is not in a remote upgrading state; when the processing module works and is in a remote upgrading state, outputting the closing level; the system further comprises: an OR gate; the first pin is connected with a first input end of the OR gate, the second pin is connected with a second input end of the OR gate, and an output end of the OR gate is connected with an enabling pin of the watchdog module.
Optionally, the system further includes: a second pull-down module; the second pull-down module is connected with the second pin and used for pulling down the level of the second pin to the enabling level when the second pin does not output signals.
Optionally, the first pull-down module includes: a first pull-down resistor; one end of the first pull-down resistor is connected with the first pin, and the other end of the first pull-down resistor is grounded.
Optionally, the second pull-down module includes: a second pull-down resistor; one end of the second pull-down resistor is connected with the second pin, and the other end of the second pull-down resistor is grounded.
Optionally, the enable level is a low level, and the shutdown level is a high level.
Optionally, the processing module further includes: a third pin; the three pins are connected with a watchdog input pin of the watchdog module, and the third pin is used for outputting a dog feeding signal through the third pin regularly when the processing module works normally.
Optionally, the processing module includes: a fourth pin; the fourth pin is connected with a watchdog output pin of the watchdog module; the fourth pin is used for receiving the output reset signal of the watchdog output pin when the watchdog module works so as to reset the processing module.
Optionally, the system further includes: a control switch; one end of the control switch is connected with a fourth pin of the processing module, and the other end of the control switch is connected with a watchdog output pin of the watchdog; the control end of the control switch is connected with the processing module; and the processing module is used for controlling the control switch to be switched off or switched on according to a user instruction.
Optionally, the processing module includes a digital signal processing chip.
In the watchdog system provided by the application, the processing module is used for connecting a first pin externally connected with the simulator with the first pull-down module, the first pin is also connected with an enabling pin of the watchdog module, when the first pin is not externally connected with the simulator, the first pull-down module pulls down the level of the first pin to be the enabling level of the watchdog, the enabling pin receives the enabling level, and the watchdog module works normally; when the first pin is externally connected with the simulator, the first pull-down module pulls down the level of the first pin to be the closing level of the watchdog, the enabling pin receives the closing level, and the watchdog module stops working. According to the scheme, when the processing module writes the program, the watchdog receives the closing level, and even if the watchdog does not receive the dog feeding signal, the watchdog cannot send the restart instruction, so that the program of the processing module is programmed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the embodiments of the application and, together with the description, serve to explain the principles of the embodiments of the application.
Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. The drawings and written description are not intended to limit the scope of the embodiments of the application in any way, but rather to illustrate the concepts of the embodiments of the application by reference to particular embodiments.
FIG. 1 is a waveform diagram illustrating the operation of a watchdog module;
fig. 2 is a schematic structural diagram of a watchdog system according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a watchdog system according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of a watchdog system according to a third embodiment of the present application;
fig. 5 is a waveform diagram of an operation of a watchdog system according to a third embodiment of the present application.
Reference numerals
21-a processing module;
211-a first pin;
212-second pin;
213-third pin;
214-a fourth pin;
22-watchdog module;
221-enable pin;
222-watchdog output pin;
23-a first pull-down module;
231-first pull-down resistor;
24-a second pulldown module;
241-a second pull-down resistor;
25-or gate.
Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The electronic product is widely applied to various industries, and a watchdog system is arranged in the electronic product and comprises a processing module and a watchdog module, wherein the processing module is provided with a control program to control the action of the electronic product. The processing module often can not work normally due to reasons such as the running of the control program, and for this reason, the watchdog module needs to send a reset instruction to the processing module so as to enable the processing module to work normally.
In the related technology, when the processing module works normally, a dog feeding signal is sent to the watchdog module at regular time, and when the watchdog module does not receive the dog feeding signal within the dog feeding time, and the processing module is regarded as not working normally, a reset instruction is sent to the processing module so as to restart the processing module. Fig. 1 is a waveform diagram of an operation of a watchdog module, as shown in fig. 1, in a normal operation, a processing module periodically sends a pulse signal (i.e., a dog feeding signal) similar to an input signal of the watchdog in the diagram to the watchdog module, and a duration of a high level and a low level of the pulse signal is not longer than a dog feeding time TWD. If the watchdog module regularly receives the pulse signal sent by the processing module, the watchdog module does not trigger the control processing module to reset. Taking the reset signal as the low level active as an example, as shown in the figure, the duration of the high level and the low level of the first three pulse signals does not exceed TWD, the output signal of the watchdog is always at the high level, and the processing module continues to work normally. Once the processing module fails to send a dog feeding signal to the watchdog module in time due to a dead halt or a fault, for example, after three pulses in fig. 1, the duration of the low level exceeds TWD, the watchdog circuit outputs a low level reset signal to control the processing module to reset and restart.
The programming procedure of the processing module refers to a procedure of transmitting a programmed procedure to the processing module through an interface specified by a manufacturer according to a programming protocol specified by the manufacturer, and storing the procedure in a memory of the processing module. At present, a program in a computer is generally programmed into a processing module by means of a simulator, and the programming of the program of the processing module is completed through a test interface of the processing module. However, in the related art, when the emulator program is inserted into the processing module, the processing module does not send out the dog feeding signal, so that the dog feeding module may mistakenly consider that the processing module does not normally operate, and send out the restart instruction to the processing module, thereby failing to realize normal program writing of the processing module program.
The technical means of the present application and the technical means of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. In the description of the present application, unless otherwise explicitly specified and defined, each term should be understood broadly in the art. Embodiments of the present application will be described below with reference to the accompanying drawings.
Example one
Fig. 2 is a schematic structural diagram of a watchdog system according to an embodiment of the present application, and as shown in fig. 2, the embodiment provides a watchdog system, including: a processing module 21, a watchdog module 22 and a first pull-down module 23.
The processing module 21 includes a first pin 211, and the first pin 211 is used for externally connecting a simulator for programming to the processing module 21.
The first pull-down module 23 is connected to the first pin 211, and the first pull-down module 23 is configured to pull down a level at the first pin 211 to an enable level of the watchdog module 22 when the first pin 211 is not externally connected to the emulator. And when the first pin 211 is externally connected with the emulator, the level at the first pin 211 is pulled down to the off level of the watchdog module 22.
The first pin 211 is connected to an enable pin 221 of the watchdog module 22, wherein the enable pin 221 is used for controlling the watchdog module 22 to operate when receiving an enable level; and controls the watchdog module 22 to stop operating upon receiving the shutdown level.
In this embodiment, the processing module 21 is a core for implementing the operation of the device, and for example, the processing module 21 may be a chip or a single chip. The processing module 21 includes a first pin 211, and the first pin 211 is used for externally connecting a simulator for programming the processing module 21.
In an example, the Processing module 21 is a Digital Signal Processing (DSP) chip, the DSP chip is provided with a Joint Test Action Group (JTAG) interface, the first pin 211 is a Test Reset Input (TRST) pin of the JTAG interface, and the TRST pin is a selectively used pin of the JTAG interface. The emulator is plugged into the JTAG interface, and the emulator is connected to the first pin 211 through the JTAG interface.
The emulator is a link connecting the processing module 21 and the computer loaded with the program to be programmed, and the emulator is electrified, so that the first pin 211 outputs different levels before and after the emulator is connected to the first pin 211. Continuing to take the processing module 21 as an example of a DSP chip, when the emulator is plugged into the JTAG interface, the TRST pin outputs a high level. However, when the emulator is not plugged into the JTAG interface, the first pin 211 is in a floating state, outputting an indeterminate signal.
In order to prevent the first pin 211 from outputting an indeterminate signal when the emulator is not connected to the first pin 211, in this embodiment, the first pull-down module 23 is connected to the first pin 211, and the first pull-down module 23 is configured to pull down the level of the first pin 211 to the enable level of the watchdog module 22 when the emulator is not externally connected to the first pin 211. And when the first pin 211 is externally connected with the emulator, the level at the first pin 211 is pulled down to the off level of the watchdog module 22.
The enabling level refers to a level capable of controlling the watchdog system to normally work, and the closing level is a level for controlling the watchdog to close. It will be appreciated that the enable level and the disable level are unequal levels, and that the enable level and the disable level are used to indicate the operational status of the watchdog. Illustratively, the enable level is low and the shut down level is high. It is of course also possible to set the enable level to a high level and the shut down level to a low level.
In this embodiment, the first pull-down module 23 outputs different and determinable levels when the first pin 211 is connected to the external emulator and is not connected to the emulator, and determines whether the processing module 21 is in the program programming state according to the level of the level.
For the first pull-down module 23, in one example that can be implemented, with continued reference to fig. 2, the first pull-down module 23 includes a first pull-down resistor 231, one end of the first pull-down resistor 231 is connected to the first pin 211, and the other end of the first pull-down resistor 231 is grounded. It should be noted that the first pull-down resistor 231 is a weak pull-down resistor, and it can be understood that when the voltage at the first pin 211 is high, such as when an emulator is plugged in, a signal is still input to the enable pin 221 at a high level due to the weak pull-down strength of the first pull-down resistor. Therefore, when the emulator is not in operation, the first pull-down resistor 231 pulls down the voltage at the first pin 211 to a low level. When the emulator is switched in, the voltage at the first pin 211 will go high.
In this example, before and after the emulator is connected, the enable pin 221 receives a close level or an enable level through the first pull-down resistor 231, so that when the processing module is connected to the emulator to perform program burning, the watchdog module 22 is automatically controlled to close, and when the processing module is not connected to the emulator, that is, when the program burning is not performed, the watchdog module is automatically enabled to normally operate.
The working process of the embodiment: when the emulator is not inserted into the processing module 21, the first pull-down module 23 pulls down the level at the first pin 211 to the enable level, the enable pin 221 receives the enable level, the watchdog module 22 operates normally, and continues to monitor the processing module 21 in real time. When the emulator is plugged into the processing module 21 to program, the voltage at the first pin 211 changes to the shutdown level, the watchdog module 22 receives the shutdown level, and the watchdog module 22 stops working and no longer monitors the processing module 21. After the processing module 21 completes program programming, the emulator is turned off, the watchdog module 22 continues to receive the enable level, and the watchdog module 22 continues to monitor the processing module 21.
In this embodiment, the processing module 21 is configured to connect a first pin 211 of an external emulator to the first pull-down module 23, where the first pin 211 is further connected to an enable pin 221 of the watchdog module 22, and when the first pin 211 is not connected to the external emulator, the first pull-down module 23 pulls down a level of the first pin 211 to an enable level of the watchdog, and the enable pin 221 receives the enable level, so that the watchdog module 22 operates normally; when the first pin 211 is externally connected to the emulator, the first pull-down module 23 pulls down the level of the first pin 211 to the off level of the watchdog, and the enable pin 221 receives the off level, and the watchdog module 22 stops working. According to the scheme, when the processing module 21 writes the program in a programming mode, the watchdog receives the closing level, and even if the watchdog does not receive the dog feeding signal, the watchdog cannot send out the restarting instruction, so that the program of the processing module 21 is written in the programming mode.
Example two
Fig. 3 is a schematic structural diagram of a watchdog system provided in the second embodiment of the present application, and as shown in fig. 3, on the basis of the foregoing embodiment, the watchdog system provided in the present embodiment further includes: a second pin 212; the second pin 212 is used for outputting an enable level when the processing module 21 is working and is not in a remote upgrade state; and outputting the shutdown level when the processing module 21 is in operation and in the remote upgrade state.
For example, the second pin 212 may be a General Purpose Input/output (GPIO) pin of a chip, and the GPIO pin may output a low level according to a control program of the chip when the chip is not in a remote upgrade state, and output a high level when the chip is in the remote upgrade state, where the high level is a shutdown level and the low level is an enable level. Of course, the high level may be output when the chip is not in the remote upgrade state, and the low level may be output when the chip is in the remote upgrade state.
With continued reference to fig. 3, the watchdog system provided in this embodiment further includes: an OR gate 25; the first pin 211 is connected to a first input of the or gate 25, the second pin 212 is connected to a second input of the or gate 25, and an output of the or gate 25 is connected to an enable pin 221 of the watchdog module 22.
It is understood that when at least one of the first pin 211 or the second pin 212 outputs the off level, the watchdog module 22 receives the off level, and the watchdog module 22 is turned off. When both the first pin 211 and the second pin 212 output the enable level, the watchdog module 22 operates normally. That is, when the processing module 21 remotely upgrades or inserts the emulator program, the watchdog module 22 receives the shutdown level, and the watchdog module 22 does not send the reset instruction even if it does not receive the watchdog feeding signal.
When the watchdog system works, the processing module 21 is not upgraded remotely, the second pin 212 outputs a low level, if the first pin 211 is not connected with the emulator programming program, and the first pin 211 outputs a low level, the enable pin 221 of the watchdog module 22 inputs a low level, and the watchdog works normally; if the first pin 211 is connected to the emulator programming program and the first pin 211 outputs a high level, the enable pin 221 of the watchdog module 22 inputs a high level, and the watchdog stops working. When the processing module 21 performs remote upgrade, the second pin 212 outputs a high level, the enable pin 221 inputs a high level, and the watchdog module 22 stops working.
After the processing module 21 is powered on, in some cases, the processing module 21 is not normally started, and the control program of the processing module 21 cannot run, so that the output of the second pin 212 is not an enable signal or a close signal, but is an uncertain signal, and thus the watchdog cannot normally work, and cannot send a restart instruction to the processing module 21, so that the processing module 21 is still in a deadlock state.
In response to the above problem, in one example, still referring to fig. 3, the watchdog system further includes: a second pull-down module 24; the second pull-down module 24 is connected to the second pin 212, and the second pull-down module 24 is configured to pull down a level at the second pin 212 to an enable level when the second pin 212 does not output a signal, that is, does not output an enable signal or a turn-off signal. That is, even if the processing module 21 does not normally operate, the watchdog system can still receive the enable signal, and the watchdog system normally operates, at this time, because the processing module 21 is not normally started, the watchdog system does not receive the dog feeding signal, and the watchdog module 22 sends a restart instruction to the processing module 21 to start the processing module 21.
In this example, the second pin 212 is connected to the second pull-down module 24, so that the enable level can be output even when the processing module 21 is not started after being powered on, the watchdog module 22 can normally operate, and the processing module 21 is restarted.
In one example that may be implemented, with continued reference to fig. 3, the second pull-down module 24 may include a second pull-down resistor 241; one end of the second pull-down resistor 241 is connected to the second pin 212, and the other end of the second pull-down resistor 241 is grounded. It should be noted that the second pull-down resistor 241 is a weak pull-down resistor, and it can be understood that when the second pin 212 outputs a high level, the high level is still inputted to the second input terminal of the or gate 25 by the pull-down action of the second pull-down resistor 241.
In use, when the second pin 212 outputs no signal or outputs a low level, the second input terminal of the or gate 25 inputs a low level because the second pull-down resistor 241 is grounded, and when the second pin 212 outputs a high level, the second input terminal of the or gate 25 receives a high level.
In this example, the second pull-down resistor 241 ensures that the second input terminal of the or gate 25 can still receive the enable level when the processing module 21 is powered on and is not started, thereby ensuring that the watchdog module 22 works normally.
In this example, it is also ensured that when the processing module 21 is powered on and not started, the second input terminal of the or gate 25 can still receive the enable level, thereby ensuring that the watchdog module 22 works normally.
In this embodiment, the first pin 211 is connected to a first input terminal of the or gate 25, the second pin 212 is connected to a second input terminal of the or gate 25, and an output terminal of the or gate 25 is connected to the enable pin 221 of the watchdog module 22. By the scheme, the effect that when the processing module 21 is remotely upgraded or programmed, the enabling pin 221 receives the closing level, the watchdog is in the temporary shielding state, and the processing module 21 cannot be restarted is achieved.
EXAMPLE III
Fig. 4 is a schematic structural diagram of a watchdog system provided in a third embodiment of the present application, and as shown in fig. 4, on the basis of any one of the above embodiments, the watchdog system provided in this embodiment further includes: a third pin 213; the third pin 213 is connected to a watchdog Input pin 222 (WDI for short) of the watchdog module 22, and the third pin 213 is used for outputting a Dog feeding signal through the third pin 213 at regular time when the processing module 21 normally operates.
For example, the third pin 213 may be a GPIO48 of a chip, the output of the third pin 213 is connected to the watchdog input pin 222, the third pin 213 outputs a pulse signal to the watchdog input pin 222, and if the duration of the high level or the low level of the pulse signal is within the specified dog feeding time TWD, the watchdog module 22 outputs a persistent high level, that is, the processing module 21 is not restarted. Once the duration of the high or low level exceeds the dog feeding time TWD, the watchdog will output a low level to instruct the processing circuit to restart.
In this embodiment, the third pin 213 of the processing module 21 is connected to the watchdog input pin 222, so that the watchdog module 22 can receive a reliable dog feeding signal.
For the flow after the watchdog receives the dog feeding signal, in an example, as shown in fig. 4, the processing module 21 is further provided with a fourth pin 214; the fourth pin 214 is connected to the watchdog output pin 223 of the watchdog module 22; the fourth pin 214 is used for receiving the output reset signal of the watchdog output pin 223 to reset the processing module when the watchdog module 22 is in operation.
In this example, the fourth pin 214 may be a Reset pin (Reset, abbreviated as RST) of the chip, and after the watchdog module 22 receives the dog feeding signal within the dog feeding time TWD, the watchdog output pin 223 may output a continuous high level, and certainly may also output a continuous low level. When the dog feeding signal is not received within the dog feeding time TWD, a low level opposite to the original persistent high level is output as a reset signal, and the reset pin RST of the processing module 21 resets the processing module 21 after receiving the reset signal.
In some examples, a control switch may also be provided in the watchdog system, wherein one end of the control switch is connected to the fourth pin 214 of the processing module 21, and the other end of the control switch is connected to the watchdog output pin 223 of the watchdog module 22; the control end of the control switch is connected with the processing module 21; and the processing module 21 is used for controlling the control switch to be switched off or switched on according to a user instruction.
It will be appreciated that when the control switch is open, the processing module 21 no longer receives the reset indication output by the watchdog module 22. Therefore, the control switch can be used as an emergency processing button, when the system has a fault, such as an open circuit at the or gate 25 or the enable pin 221, and the off level cannot be normally input into the watchdog module 22, the user can manually control the control switch to be turned off, so that the reset indication output by the watchdog module 22 cannot be transmitted to the processing module 21, and therefore, the false reset when the reset of the processing module is not desired to be performed is avoided, and the reliability of the watchdog system is further improved.
Next, the working process of this embodiment will be exemplarily described with reference to specific scenarios, and fig. 5 is a working waveform diagram of a watchdog system provided in the third embodiment of the present application, as shown in fig. 4 and fig. 5, after power-on, t 0 -t 1 In the processing module 21, the processing module operates normally, the first input terminal of the or gate 25 receives the low level pulled down by the first pull-down resistor 231, the second input terminal of the or gate 25 receives the low level pulled down by the second pull-down resistor, the output terminal of the or gate 25 outputs the low level to the enable pin 221, and the watchdog module 22 operates normally. The third pin 213 of the processing module 21 outputs a pulse signal to the watchdog input pin 222, the duration of the high level and the low level of the pulse signal is not longer than the dog feeding time TWD, the watchdog output pin 223 of the watchdog module 22 outputs a persistent high level, and the processing module 21 is not reset. t is t 1 At this time, the first pin 211 is externally connected to the emulator, the program starts to be programmed into the processing module 21, the voltage at the first pin 211 is at a high level, the output end of the or gate 25 outputs the high level to the enable pin 221, the watchdog module 22 is turned off, stops working, and is in a shielding state. At this time, the processing module 21 normally executes the program programming, the watchdog input pin is not output with the watchdog feeding signal in the process, and the watchdog is in the shielding state, so that the processing module 21 is not mistakenly reset, and the normal program programming of the processing module 21 is ensured. Up to t 2 At this time, the processing module 21 completes the programming procedure, the emulator is pulled out from the first pin 211, the first pin 211 is disconnected from the emulator, the potential at the first pin 211 is pulled down to the low level by the first pull-down resistor again, the enable pin 221 of the watchdog module 22 receives the low level again, the watchdog module 22 is activated again, the working state of the processing module 21 continues to be monitored, and the monitoring reset function is realized.
In the watchdog system provided by the embodiment, the processing module is used for connecting a first pin externally connected with the simulator with the first pull-down module, the first pin is also connected with an enabling pin of the watchdog module, when the first pin is not externally connected with the simulator, the first pull-down module pulls down the level of the first pin to be the enabling level of the watchdog, the enabling pin receives the enabling level, and the watchdog module works normally; when the first pin is externally connected with the simulator, the first pull-down module pulls down the level of the first pin to be the closing level of the watchdog, the enabling pin receives the closing level, and the watchdog module stops working. According to the scheme, when the processing module writes the program, the watchdog receives the closing level, and even if the watchdog does not receive the dog feeding signal, the watchdog cannot send out the restart instruction, so that the program of the processing module is written.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A watchdog system, comprising: the system comprises a processing module, a watchdog module and a first pull-down module;
the processing module comprises a first pin, and the first pin is externally connected with a simulator for programming the processing module;
the first pull-down module is connected with the first pin and used for pulling down the level of the first pin to be the enabling level of the watchdog module when the first pin is not externally connected with a simulator; when the first pin is externally connected with the simulator, the level at the first pin is pulled down to be the closing level of the watchdog module;
the first pin is connected with an enabling pin of the watchdog module, wherein the enabling pin is used for controlling the watchdog module to work when receiving the enabling level; and controlling the watchdog module to stop working when receiving the closing level.
2. The watchdog system of claim 1, wherein the processing module further comprises: a second pin; the second pin is used for outputting the enabling level when the processing module works and is not in a remote upgrading state; when the processing module works and is in a remote upgrading state, outputting the closing level;
the system further comprises: an OR gate; the first pin is connected with a first input end of the OR gate, the second pin is connected with a second input end of the OR gate, and an output end of the OR gate is connected with an enabling pin of the watchdog module.
3. The watchdog system of claim 2, the system further comprising: a second pull-down module;
the second pull-down module is connected with the second pin and used for pulling down the level of the second pin to the enabling level when the second pin does not output signals.
4. The watchdog system of claim 1, wherein the first pull-down module comprises: a first pull-down resistor;
one end of the first pull-down resistor is connected with the first pin, and the other end of the first pull-down resistor is grounded.
5. The watchdog system of claim 3, wherein the second pull-down module comprises: a second pull-down resistor;
one end of the second pull-down resistor is connected with the second pin, and the other end of the second pull-down resistor is grounded.
6. The watchdog system of claim 1, wherein the enable level is a low level and the shut down level is a high level.
7. A watchdog system according to any one of claims 1-6, wherein the processing module further comprises: a third pin;
the three pins are connected with a watchdog input pin of the watchdog module, and the third pin is used for outputting a dog feeding signal through the third pin regularly when the processing module works normally.
8. A watchdog system according to any one of claims 1-6, wherein the processing module comprises: a fourth pin;
the fourth pin is connected with a watchdog output pin of the watchdog module; the fourth pin is used for receiving the output reset signal of the watchdog output pin when the watchdog module works so as to reset the processing module.
9. The watchdog system of claim 7, the system further comprising: a control switch;
one end of the control switch is connected with a fourth pin of the processing module, and the other end of the control switch is connected with a watchdog output pin of the watchdog; the control end of the control switch is connected with the processing module;
and the processing module is used for controlling the control switch to be switched off or switched on according to a user instruction.
10. A watchdog system according to any one of claims 1 to 6, wherein the processing module includes a digital signal processing chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221328393.5U CN217386347U (en) | 2022-05-30 | 2022-05-30 | Watchdog system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221328393.5U CN217386347U (en) | 2022-05-30 | 2022-05-30 | Watchdog system |
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| CN217386347U true CN217386347U (en) | 2022-09-06 |
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| CN202221328393.5U Active CN217386347U (en) | 2022-05-30 | 2022-05-30 | Watchdog system |
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