CN217386191U

CN217386191U - Interface circuit compatible with two interface modes and corresponding numerical control equipment

Info

Publication number: CN217386191U
Application number: CN202221425609.XU
Authority: CN
Inventors: 吴飞龙; 方乐
Original assignee: Higerman Cnc Technology Shenzhen Co ltd
Current assignee: Higerman Cnc Technology Shenzhen Co ltd
Priority date: 2022-06-08
Filing date: 2022-06-08
Publication date: 2022-09-06
Anticipated expiration: 2032-06-08

Abstract

The utility model provides an interface circuit that can compatible two kinds of interface modes, it includes input module, first interface module, second interface module. The input module inputs digital signals of the host, and both the first interface module and the second interface module can receive the digital signals. The first interface module comprises a first filtering unit and a first electrostatic protection unit which are connected in series, and the second interface module comprises a second filtering unit and a second electrostatic protection unit which are connected in series. The first filtering unit and the second filtering unit can filter out direct current components in the digital signals, and the first static protection unit and the second static protection unit can perform static elimination operation on the digital signals. When the first interface module is connected with the display device, the first interface module transmits the digital signal to the display device. When the second interface module is connected with the display device, the second interface module transmits the digital signal to the display device. The interface circuit is applied to a numerical control device.

Description

Interface circuit compatible with two interface modes and corresponding numerical control equipment

Technical Field

The utility model relates to a circuit field, in particular to interface circuit.

Background

In modern society, DVI is a digital video interface. DVI is used to transmit digital signals and digital image information is transmitted directly to a display device without any conversion. HDMI is a high definition multimedia interface, which can transmit audio and video signals simultaneously. And the HDMI technology can provide a clearer picture quality for the display device. However, the existing interface circuit can only satisfy one interface mode, so that the existing interface circuit is difficult to satisfy the requirements of users for using various display devices.

Therefore, it is necessary to provide an interface circuit compatible with two interface modes and a corresponding numerical control device to solve the above technical problems.

SUMMERY OF THE UTILITY MODEL

The utility model provides an interface circuit that can compatible two kinds of interface modes and the numerical control equipment that corresponds has effectively solved current interface circuit and has been difficult to satisfy the technical problem that the user used multiple display device demand.

The utility model provides an interface circuit that can compatible two kinds of interface modes, it includes:

the input module is used for inputting a digital signal of the host;

the first interface module is used for receiving the digital signal and comprises a first filtering unit and a first electrostatic protection unit which are connected in series, wherein the first filtering unit is used for filtering out a direct-current component in the digital signal, and the first electrostatic protection unit is used for carrying out electrostatic elimination operation on the digital signal;

the second interface module is used for receiving the digital signal and comprises a second filtering unit and a second electrostatic protection unit which are connected in series, wherein the second filtering unit is used for filtering out a direct-current component in the digital signal, and the second electrostatic protection unit is used for carrying out electrostatic elimination operation on the digital signal;

when the first interface module is connected with a display device, the first interface module transmits the digital signal to the display device; when the second interface module is connected with the display device, the second interface module transmits the digital signal to the display device.

Furthermore, the digital signals comprise Clock differential signals and three groups of data differential signals, the first interface module comprises the first interface chip unit, the first interface chip unit comprises a TMDS Clock + pin and a TMDS Clock-pin, and the TMDS Clock + pin and the TMDS Clock-pin are respectively connected with the first electrostatic protection unit and used for transmitting the Clock differential signals; the first interface chip unit comprises a TMDS Data0+ pin and a TMDS Data 0-pin, wherein the TMDS Data0+ pin and the TMDS Data 0-pin are respectively connected with the first electrostatic protection unit and used for transmitting a first group of Data differential signals;

the first interface chip unit comprises a TMDS Data1+ pin and a TMDS Data 1-pin, wherein the TMDS Data1+ pin and the TMDS Data 1-pin are respectively connected with the first electrostatic protection unit and are used for transmitting a second group of Data differential signals; the first interface chip unit comprises a TMDS Data2+ pin and a TMDS Data 2-pin, wherein the TMDS Data2+ pin and the TMDS Data 2-pin are respectively connected with the first electrostatic protection unit and are used for transmitting a third group of Data differential signals.

Further, the second interface module comprises a second interface chip unit, the second interface chip unit comprises a TMDS CLK + pin and a TMDS CLK-pin, and the TMDS CLK + pin and the TMDS CLK-pin are respectively connected to the second electrostatic protection unit and are used for transmitting the clock differential signal; the second interface chip unit comprises a TMDS D0+ pin and a TMDS D0-pin, wherein the TMDS D0+ pin and the TMDS D0-pin are respectively connected with the second electrostatic protection unit and are used for transmitting a first group of data differential signals;

the second interface chip unit comprises a TMDS D1+ pin and a TMDS D1-pin, wherein the TMDS D1+ pin and the TMDS D1-pin are respectively connected with the second electrostatic protection unit and are used for transmitting a second group of data differential signals; the second interface chip unit comprises a TMDS D2+ pin and a TMDS D2-pin, wherein the TMDS D2+ pin and the TMDS D2-pin are respectively connected with the second electrostatic protection unit and are used for transmitting a third group of data differential signals.

Furthermore, the first interface module further comprises the first data transmission unit, one end of the first data transmission unit is connected with the host, and the other end of the first data transmission unit is connected with the first interface chip unit; the second interface module further comprises a second data transmission unit, one end of the second data transmission unit is connected with the host, the other end of the second data transmission unit is connected with the second interface chip unit, and the first data transmission unit or the second data transmission unit is used for transmitting information of the display device to the host.

Further, the first interface chip unit includes a HOST pin, the first interface module includes a first TVS diode, one end of the first TVS diode is connected to the HOST pin, and the other end of the first TVS diode is grounded; the second interface chip unit comprises a Hot plus Delete pin, the first interface module comprises a second TVS diode, one end of the second TVS diode is connected with the Hot plus Delete pin, and the other end of the second TVS diode is grounded.

Further, the first interface module includes a first Power supply unit, the first interface chip unit includes a +5V Power pin, the first Power supply unit is connected to the +5V Power pin, and the first Power supply unit is configured to provide a working voltage to the first interface chip unit;

the second interface module comprises a second power supply unit, the second interface chip unit comprises a +5V pin, the second power supply unit is connected with the +5V pin, and the second power supply unit is used for supplying working voltage to the second interface chip unit.

Further, the first Power supply unit comprises a first diode, the anode of the first diode is connected with the Power supply, and the cathode of the first diode is connected with the +5V Power pin;

the second power supply unit comprises a second diode, the anode of the second diode is connected with the power supply, and the cathode of the second diode is connected with the +5V pin.

Furthermore, the first power supply unit further comprises a first filter capacitor, one end of the first filter capacitor is connected with the anode of the first diode, and the other end of the first filter capacitor is grounded; the second power supply unit further comprises a second filter capacitor, one end of the second filter capacitor is connected with the negative electrode of the second diode, and the other end of the second filter capacitor is grounded.

Furthermore, the capacitive reactance of the first filter capacitor is 0.05-0.15 muF, and the capacitive reactance of the second filter capacitor is 0.05-0.15 muF.

A numerical control device comprises any one of the interface circuits compatible with the two interface modes.

The utility model discloses compare in prior art, its beneficial effect is: the utility model provides an interface circuit of two kinds of compatible interface modes, this digital signal of the interface circuit accessible input module input host computer of two kinds of compatible interface modes, this first interface module and second interface module all are connected with input module. When the first interface module is connected with the display device, the first interface module transmits the digital signal to the display device. When the second interface module is connected with the display device, the second interface module transmits the digital signal to the display device. The circuit can provide an HDMI interface and a DVI interface, so that a client can select a proper interface according to the condition of the display device, and the circuit can establish communication between the host and the display device. Because the HDMI interface and the DVI interface are respectively connected with the display equipment with different definition, the circuit can meet the requirement of using various display equipment by a user. The technical problem that the existing interface circuit is difficult to meet the requirements of users on using various display devices is effectively solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments are briefly introduced below, and the drawings in the following description are only corresponding drawings of some embodiments of the present invention.

Fig. 1 is a block diagram of an embodiment of an interface circuit compatible with two interface modes according to the present invention.

Fig. 2 is one of circuit diagrams of an embodiment of an interface circuit compatible with two interface modes according to the present invention.

Fig. 3 is a second circuit diagram of an embodiment of an interface circuit compatible with two interface modes according to the present invention.

Fig. 4 is a third circuit diagram of an embodiment of an interface circuit compatible with two interface modes according to the present invention.

In the figure, 10, an interface circuit compatible with two interface modes; 11. an input module; 12. a first interface module; 121. a first filtering unit; 122. a first electrostatic protection unit; 123. a first interface chip unit; 124. a first data transmission unit; 125. a first power supply unit; 13. a second interface module; 131. a second filtering unit; 132. a second electrostatic protection unit; 133. a second interface chip unit; 134. a second data transmission unit; 135. a second power supply unit.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.

In the present invention, the directional terms, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", "top" and "bottom", refer to the orientation of the drawings, and the directional terms are used for illustration and understanding, but not for limiting the present invention.

The terms "first," "second," and the like in the terms of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or any order limitation.

In the drawings, elements having similar structures are denoted by the same reference numerals.

Referring to fig. 1, 2 and 3, the present invention provides an interface circuit 10 compatible with two interface modes. The interface circuit 10 compatible with the two interface modes comprises an input module 11, a first interface module 12 and a second interface module 13, and the interface circuit 10 compatible with the two interface modes can be applied to a numerical control device. The input module 11 is configured to input a digital signal of a host, and the input module 11 includes a first input terminal CONN _ HDMI _ CLKP, a second input terminal CONN _ HDMI _ CLKN, a third input terminal CONN _ HDMI _ TXN0, a fourth input terminal CONN _ HDMI _ TXP0, a fifth input terminal CONN _ HDMI _ TXP1, a sixth input terminal CONN _ HDMI _ TXN1, a seventh input terminal CONN _ HDMI _ TXP2, and an eighth input terminal CONN _ HDMI _ TXN 2. The digital signals include a clock differential signal and three sets of data differential signals, a first input terminal CONN _ HDMI _ CLKP and a second input terminal CONN _ HDMI _ CLKN are for inputting the clock differential signal, and a third input terminal CONN _ HDMI _ TXN0 and a fourth input terminal CONN _ HDMI _ TXP0 are for inputting the first set of data differential signals. The fifth and sixth input terminals CONN _ HDMI _ TXP1 and CONN _ HDMI _ TXN1 are for inputting the second group of data differential signals, and the seventh and eighth input terminals CONN _ HDMI _ TXP2 and CONN _ HDMI _ TXN2 are for inputting the third group of data differential signals.

Referring to fig. 1, fig. 2 and fig. 3, the first interface module 12 is used for receiving a digital signal, and the first interface module 12 includes a first filtering unit 121 and a first electrostatic protection unit 122 connected in series. The first filtering unit 121 is configured to filter a dc component in the digital signal, and the first electrostatic protection unit 122 is configured to perform an electrostatic elimination operation on the digital signal. The first filtering unit 121 includes a first capacitor C211 and a second capacitor C212, and the first capacitor C211 is connected in parallel with the second capacitor C212. The capacitive reactance of the first capacitor C211 and the second capacitor C212 is 0.1 muf, and the withstand voltage of the first capacitor C211 and the second capacitor C212 is 50V. The first ESD protection unit 122 includes a first ESD tube U27, and the EDS tube is an ESD protection tube, which can be used to prevent static electricity. The first ESD tube U27 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the first capacitor C211 is connected to the first input terminal CONN _ HDMI _ CLKP, and the other end of the first capacitor C211 is connected to the I1 pin of the first ESD tube U27. One end of the second capacitor C212 is connected to the second input terminal CONN _ HDMI _ CLKN, and the other end of the second capacitor C212 is connected to the I2 pin of the first ESD tube U27.

Referring to fig. 1, 2 and 3, the first filtering unit 121 includes a third capacitor C217 and a fourth capacitor C218, and the third capacitor C217 is connected in parallel with the fourth capacitor C218. The capacitive reactance of the third capacitor C217 and the fourth capacitor C218 is 0.1 muf, and the withstand voltage of the third capacitor C217 and the fourth capacitor C218 is 50V. The first ESD protection unit 122 includes a second ESD tube U28, and the second ESD tube U28 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the third capacitor C217 is connected to the third input terminal CONN _ HDMI _ TXN0, and the other end of the third capacitor C217 is connected to the I1 pin of the second ESD tube U28. One end of the fourth capacitor C218 is connected to the fourth input terminal CONN _ HDMI _ TXP0, and the other end of the fourth capacitor C218 is connected to the I2 pin of the second ESD tube U28.

Referring to fig. 1, 2 and 3, the first filtering unit 121 includes a fifth capacitor C215 and a sixth capacitor C216, and the fifth capacitor C215 is connected in parallel with the sixth capacitor C216. The capacitance reactance of the fifth capacitor C215 and the sixth capacitor C216 is 0.1 muf, and the withstand voltage value of the fifth capacitor C215 and the sixth capacitor C216 is 50V. The first ESD protection unit 122 includes a third ESD tube U30, and the third ESD tube U30 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the fifth capacitor C215 is connected to a fifth input terminal CONN _ HDMI _ TXP1, and the other end of the fifth capacitor C215 is connected to the I1 pin of the third ESD tube U30. One end of the sixth capacitor C216 is connected to a sixth input terminal CONN _ HDMI _ TXN1, and the other end of the sixth capacitor C216 is connected to the I2 pin of the third ESD tube U30.

Referring to fig. 1, 2 and 3, the first filter unit 121 includes a seventh capacitor C213 and an eighth capacitor C214, and the seventh capacitor C213 is connected in parallel with the eighth capacitor C214. The capacitance reactance of the seventh capacitor C213 and the eighth capacitor C214 is 0.1 muf, and the withstand voltage of the seventh capacitor C213 and the eighth capacitor C214 is 50V. The first ESD protection unit 122 includes a fourth ESD tube U29, and the fourth ESD tube U29 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the seventh capacitor C213 is connected to the seventh input terminal CONN _ HDMI _ TXP2, and the other end of the seventh capacitor C213 is connected to the I1 pin of the fourth ESD tube U29. One end of the eighth capacitor C214 is connected to the eighth input terminal CONN _ HDMI _ TXN2, and the other end of the eighth capacitor C214 is connected to the I2 pin of the fourth ESD tube U29.

Referring to fig. 1, fig. 2 and fig. 3, the second interface module 13 is used for receiving a digital signal. The second interface module 13 includes a second filtering unit 131 and a second electrostatic protection unit 132 connected in series, where the second filtering unit 131 is configured to filter a dc component in the digital signal, and the second electrostatic protection unit 132 is configured to perform an electrostatic elimination operation on the digital signal. The second filtering unit 131 includes a ninth capacitor C219 and a tenth capacitor C220, and the ninth capacitor C219 and the tenth capacitor C220 are connected in parallel. The capacitance reactance of the ninth capacitor C219 and the tenth capacitor C220 is 0.1 μ F, and the withstand voltage of the ninth capacitor C219 and the tenth capacitor C220 is 50V. The second ESD protection unit 132 includes a fifth ESD tube U32, and the fifth ESD tube U32 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the ninth capacitor C219 is connected to the first input terminal CONN _ HDMI _ CLKP, and the other end of the ninth capacitor C219 is connected to the I1 pin of the fifth ESD tube U32. One end of the tenth capacitor C220 is connected to the second input terminal CONN _ HDMI _ CLKN, and the other end of the tenth capacitor C220 is connected to the I2 pin of the fifth ESD tube U32.

Referring to fig. 1, 2 and 3, the second filtering unit 131 includes an eleventh capacitor C225 and a twelfth capacitor C226, and the eleventh capacitor C225 is connected in parallel with the twelfth capacitor C226. The capacitance reactance of the eleventh capacitor C225 and the twelfth capacitor C226 is 0.1 μ F, and the withstand voltage value of the eleventh capacitor C225 and the withstand voltage value of the twelfth capacitor C226 are 50V. The second ESD protection unit 132 includes a sixth ESD tube U33, and the sixth ESD tube U33 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the eleventh capacitor C225 is connected to the first input terminal CONN _ HDMI _ CLKP, and the other end of the eleventh capacitor C225 is connected to the I1 pin of the sixth ESD tube U33. One end of the twelfth capacitor C216 is connected to the second input terminal CONN _ HDMI _ CLKN, and the other end of the twelfth capacitor C226 is connected to the I2 pin of the sixth ESD tube U33.

Referring to fig. 1, 2 and 3, the second filter unit 131 includes a thirteenth capacitor C223 and a fourteenth capacitor C224, and the thirteenth capacitor C223 is connected in parallel with the fourteenth capacitor C224. The capacitance reactance of the thirteenth capacitor C223 and the fourteenth capacitor C224 is 0.1 μ F, and the withstand voltage of the thirteenth capacitor C223 and the fourteenth capacitor C224 is 50V. The second ESD protection unit 132 includes a seventh ESD tube U35, and the seventh ESD tube U35 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the thirteenth capacitor C223 is connected to the first input terminal CONN _ HDMI _ CLKP, and the other end of the thirteenth capacitor C223 is connected to the I1 pin of the seventh ESD tube U35. One end of the fourteenth capacitor C224 is connected to the second input terminal CONN _ HDMI _ CLKN, and the other end of the fourteenth capacitor C224 is connected to the I2 pin of the seventh ESD tube U35.

Referring to fig. 1, 2 and 3, the second filter unit 131 includes a fifteenth capacitor C221 and a sixteenth capacitor C222, and the fifteenth capacitor C221 and the sixteenth capacitor C222 are connected in parallel. The capacitance reactance of the fifteenth capacitor C221 and the sixteenth capacitor C222 is 0.1 μ F, and the withstand voltage of the fifteenth capacitor C221 and the sixteenth capacitor C222 is 50V. The second ESD protection unit 132 includes an eighth ESD tube U34, and the eighth ESD tube U34 includes an I1 pin, an I2 pin, an O1 pin, and an O2 pin. One end of the fifteenth capacitor C221 is connected to the first input terminal CONN _ HDMI _ CLKP, and the other end of the fifteenth capacitor C221 is connected to the I1 pin of the eighth ESD tube U34. One end of the sixteenth capacitor C222 is connected to the second input terminal CONN _ HDMI _ CLKN, and the other end of the sixteenth capacitor C222 is connected to the I2 pin of the eighth ESD tube U34. When the first interface module 12 is connected to the display device, the first interface module 12 transmits the digital signal to the display device. When the second interface module 13 is connected to the display device, the second interface module 13 transmits the digital signal to the display device.

Referring to fig. 1, 2 and 3, the first interface module 12 includes a first interface chip unit 123, and the first interface chip unit 123 is connectable to a display device. The first interface chip unit 123 includes a TMDS Clock + pin and a TMDS Clock-pin, which are respectively connected to the first electrostatic protection unit 122, and are used for transmitting Clock differential signals. The TMDS Clock + pin is connected with the O1 pin of the first ESD tube U27, and the TMDS Clock-pin is connected with the O2 pin of the first ESD tube U27.

Referring to fig. 1, 2 and 3, the first interface chip unit 123 includes TMDS Data0+ pins and TMDS Data 0-pins, the TMDS Data0+ pins and the TMDS Data 0-pins are respectively connected to the first electrostatic protection unit 122, and the TMDS Data0+ pins and the TMDS Data 0-pins are used for transmitting a first set of Data differential signals. The pin TMDS Data0+ is connected with the pin O1 of the second ESD tube U28, and the pin TMDS Data 0-is connected with the pin O2 of the second ESD tube U28.

Referring to fig. 1, 2 and 3, the first interface chip unit 123 includes a TMDS Data1+ pin and a TMDS Data 1-pin, the TMDS Data1+ pin and the TMDS Data 1-pin are respectively connected to the first electrostatic protection unit 122, and the TMDS Data1+ pin and the TMDS Data 1-pin are used for transmitting a second set of Data differential signals. The pin TMDS Data1+ is connected with the pin O1 of the third ESD tube U30, and the pin TMDS Data 1-is connected with the pin O2 of the third ESD tube U30.

Referring to fig. 1, 2 and 3, the first interface chip unit 123 includes a TMDS Data2+ pin and a TMDS Data 2-pin, the TMDS Data2+ pin and the TMDS Data 2-pin are respectively connected to the first electrostatic discharge protection unit 122, and the TMDS Data2+ pin and the TMDS Data 2-pin are used for transmitting a third set of Data differential signals. The pin TMDS Data2+ is connected with the pin O1 of the fourth ESD tube U29, and the pin TMDS Data 2-is connected with the pin O2 of the fourth ESD tube U29.

Referring to fig. 1, 2 and 3, the first interface module 12 includes a first Power supply unit 123, and the first interface chip unit 123 includes a +5V Power pin. The first Power supply unit 123 is connected to the +5V Power pin, and the first Power supply unit 123 is configured to provide a working voltage to the first interface chip unit 123. The first Power supply unit 123 includes a first diode D17, a positive electrode of the first diode D17 is connected to the Power VCC, a negative electrode of the first diode D17 is connected to the +5V Power pin, and the first diode D17 is used for preventing the voltage of the first interface chip unit 123 from flowing backward to the Power VCC. The first power supply unit 123 further includes a first filter capacitor C207, one end of the first filter capacitor C207 is connected to the anode of the first diode D17, and the other end of the first filter capacitor C207 is grounded. The capacitance reactance of the first filter capacitor C207 is 0.05-0.15 muf, the withstand voltage of the first filter capacitor C207 is 50V, and the first filter capacitor C207 can filter the voltage output by the power source VCC.

Referring to fig. 1, 2 and 3, the first interface chip unit 123 includes a HOST pin. The first interface module 12 includes a first TVS diode TVS25, which is a transient voltage suppression diode. One end of the first TVS diode TVS25 is connected to the HOST pin, the other end of the first TVS diode TVS25 is grounded, and the first TVS diode TVS25 is used for performing electrostatic protection on the first interface chip unit 123. The HOST pin may be used to detect whether the display device is connected to the first interface chip unit 123, and the interface circuit compatible with the two interface modes further includes a fifth resistor R204, and the HOST pin is further connected to the fifth resistor R204. The first interface chip unit 123 includes a TMDS Data 0Shield pin, a TMDS Data 1Shield pin, a TMDS Data 2Shield pin, a TMDS Clock Shield pin, a DDC/CEC group pin, a GND1 pin, a GND2 pin, a GND3 pin, a GND4 pin, a TMDS Data 0Shield pin, a TMDS Data 1Shield pin, a TMDS Data 2Shield pin, a TMDS Clock Shield pin, a DDC/CEC group pin, a GND1 pin, a GND2 pin, a GND3 pin, and a GND4 pin, which are grounded.

On the basis of fig. 1 and fig. 2, please refer to fig. 3 and fig. 4, the first interface module 12 further includes a first data transmission unit 123. One end of the first data transmission unit 123 is connected to the host, and the other end of the first data transmission unit 123 is connected to the first interface chip unit 123. The first data transmission unit 123 is used to transmit information of the display device, including resolution, scanning frequency, and the like of the display device, to the host computer. The first data transmission unit 123 includes a ninth ESD tube U26, a first resistor R227, and a second resistor R228, wherein a pin O1 of the ninth ESD tube U26 is connected to a pin SCL of the first interface chip unit 123, and a pin O2 of the ninth ESD tube U26 is connected to a pin SDA of the first interface chip unit 123. One end of the first resistor R227 is connected to the I1 pin of the ninth ESD tube U26, and the other end of the first resistor R227 is connected to the host. The interface circuit compatible with the two interface modes further comprises a first pull-up resistor R221, and the resistance value of the first pull-up resistor R221 is 2.2K omega. One end of the first pull-up resistor R221 is connected to a 5V power source VCC, and the other end of the first pull-up resistor R221 is connected between the first resistor R227 and the host. One end of the second resistor R228 is connected to the I2 pin of the ninth ESD tube U26, and the other end of the second resistor R228 is connected to the host. The interface circuit compatible with the two interface modes further comprises a second pull-up resistor R222, and the resistance value of the second pull-up resistor R222 is 2.2K omega. One end of the second pull-up resistor R222 is connected to a 5V power source VCC, and the other end of the second pull-up resistor R222 is connected between the second resistor R228 and the host.

Referring to fig. 1, 2 and 3, the second interface module 13 includes a second interface chip unit 133, and the second interface chip unit 133 can be connected to a display device. The second interface chip unit 133 includes a TMDS CLK + pin and a TMDS CLK-pin, which are respectively connected to the second electrostatic discharge protection unit 132, and may be used to transmit a clock differential signal. The TMDS CLK + pin is connected to the O1 pin of the fifth ESD tube U32, and the TMDS CLK-pin is connected to the O2 pin of the fifth ESD tube U32.

Referring to fig. 1, 2 and 3, the second interface chip unit 133 includes TMDS D0+ pins and TMDS D0-pins, the TMDS D0+ pins and the TMDS D0-pins are respectively connected to the second esd protection unit 132, and the TMDS D0+ pins and the TMDS D0-pins are used for transmitting a first set of data differential signals. The TMDS D0+ pin is connected with the O1 pin of the sixth ESD tube U33, and the TMDS D0-pin is connected with the O2 pin of the sixth ESD tube U33.

Referring to fig. 1, 2 and 3, the second interface chip unit 133 includes TMDS D1+ pins and TMDS D1-pins, the TMDS D1+ pins and the TMDS D1-pins are respectively connected to the second esd protection unit 132, and the TMDS D1+ pins and the TMDS D1-pins are used for transmitting a second set of data differential signals. The TMDS D1+ pin is connected with the O1 pin of the seventh ESD tube U35, and the TMDS D1+ pin is connected with the O2 pin of the seventh ESD tube U35.

Referring to fig. 1, 2 and 3, the second interface chip unit 133 includes TMDS D2+ pins and TMDS D2-pins, the TMDS D2+ pins and the TMDS D2-pins are respectively connected to the second esd protection unit 132, and the TMDS D2+ pins and the TMDS D2-pins are used for transmitting a third set of data differential signals. The TMDS D2+ pin is connected with the O1 pin of the eighth ESD tube U34, and the TMDS D2-pin is connected with the O2 pin of the eighth ESD tube U34.

Referring to fig. 1, 2 and 3, the second interface module 13 includes a second power supply unit 135, and the second interface chip unit 123 includes a +5V pin. The second power supply unit 123 is connected to the +5V pin, and the second power supply unit 123 is configured to provide a working voltage to the second interface chip unit. The second power supply unit 135 includes a second diode D18, a positive electrode of the second diode D18 is connected to the power VCC, a negative electrode of the second diode D18 is connected to the +5V pin, and the second diode D18 is used for preventing the voltage of the second interface chip unit 133 from flowing backward to the power VCC. The second power supply unit 135 further includes a second filter capacitor C208, one end of the second filter capacitor C208 is connected to the cathode of the second diode D18, and the other end of the second filter capacitor C208 is grounded. The capacitance reactance of the second filter capacitor C208 is 0.05-0.15 muf, the withstand voltage of the second filter capacitor C208 is 50V, and the second filter capacitor C208 can filter the voltage output by the power source VCC.

Referring to fig. 1, 2 and 3, the second interface chip unit 133 includes a Hot plus Delete pin, and the second interface module 13 includes a second TVS diode TVS26, where the Hot plus Delete pin is used to detect whether the display device is connected to the second interface chip unit. One end of the second TVS diode TVS26 is connected to the Hot Plu Delete pin, the other end of the second TVS diode TVS26 is grounded, and the second TVS diode TVS26 is used for performing electrostatic protection on the second interface chip unit 133. The second interface chip unit 133 includes a PE1 pin, a PE2 pin, a PE3 pin, a PE4 pin, an NC pin, and a GND pin, and the PE1 pin, the PE2 pin, the PE3 pin, the PE4 pin, the NC pin, and the GND pin are all grounded.

Referring to fig. 1, fig. 2 and fig. 3, the second interface module 13 further includes a second data transmission unit 134, and one end of the second data transmission unit 134 is connected to the host. The other end of the second data transmission unit 134 is connected to the second interface chip unit 133, and the second data transmission unit 134 is configured to transmit information of the display device to the host. The second data transmission unit 133 includes a tenth ESD tube U31, a third resistor R217, and a fourth resistor R218, wherein a pin O1 of the tenth ESD tube U31 is connected to a SCL pin of the second interface chip unit 133, and a pin O2 of the tenth ESD tube U31 is connected to an SDA pin of the second interface chip unit 133. One end of the third resistor R217 is connected to the I1 pin of the tenth ESD tube U31, and the other end of the third resistor R217 is connected to the host. One end of the fourth resistor R218 is connected to the I2 pin of the tenth ESD tube U31, and the other end of the fourth resistor R218 is connected to the host.

The utility model discloses a theory of operation does: when the circuit is in operation, the user connects the host connection input module 11. When the user connects the first interface chip unit 123 of the first interface module 12 with the display device, the first interface chip unit 123 receives the digital signal output by the host, and the first interface module 12 transmits the information of the display device to the host through the first data transmission unit 123. The digital signal includes a clock differential signal and three sets of data differential signals, and the clock differential signal is transmitted to the first ESD tube U27 of the first ESD protection unit 122 through the first capacitor C211 and the second capacitor C212 of the first filtering unit 121. The first ESD tube U27 then transmits the Clock differential signal to the TMDS Clock + pin and the TMDS Clock-pin of the first interface chip unit 123, which transmit the Clock differential signal to the display device.

The first group of data differential signals is transmitted to the second ESD tube U28 of the first ESD protection unit 122 through the third capacitor C217 and the fourth capacitor C218 of the first filtering unit 131. Subsequently, the second ESD tube U28 transmits the first set of Data differential signals to the TMDS Data0+ pin and the TMDS Data 0-pin of the first interface chip unit 123, and the TMDS Data0+ pin and the TMDS Data 0-pin transmit the first set of Data differential signals to the display device. The second group of data differential signals are transmitted to the third ESD tube U30 of the first ESD protection unit 122 through the fifth capacitor C215 and the sixth capacitor C216 of the first filtering unit. Subsequently, the third ESD tube U30 transmits the second set of Data differential signals to the TMDS Data1+ pin and the TMDS Data 1-pin of the first interface chip unit 123, and the TMDS Data1+ pin and the TMDS Data 1-pin transmit the second set of Data differential signals to the display device. The third group of data differential signals is transmitted to the fourth ESD tube U29 of the first ESD protection unit 122 through the seventh capacitor C213 and the eighth capacitor C214 of the first filtering unit. Subsequently, the fourth ESD transistor U29 transmits the third set of Data differential signals to the TMDS Data2+ pin and the TMDS Data 2-pin of the first interface chip unit 123, and the TMDS Data2+ pin and the TMDS Data 2-pin transmit the third set of Data differential signals to the display device.

When the user connects the second interface chip unit 133 of the second interface module 13 with the display device, the second interface chip unit 133 receives the digital signal output by the host, and the second interface module 13 transmits the information of the display device to the host through the second data transmission unit 134. The digital signal includes a clock differential signal and three sets of data differential signals, and the clock differential signal is transmitted to the fifth ESD tube U32 of the second ESD protection unit 132 through the ninth capacitor C219 and the tenth capacitor C220 of the second filtering unit. Subsequently, the fifth ESD tube U32 transmits the clock differential signal to the TMDS CLK + and TMDS CLK-pins of the second interface chip unit 133, which transmit the clock differential signal to the display device.

The first group of data differential signals are transmitted to the sixth ESD tube U33 of the second ESD protection unit 132 through the eleventh capacitor C225 and the twelfth capacitor C226 of the second filtering unit. Subsequently, the sixth ESD tube U33 transmits the first set of data differential signals to the TMDS D0+ pin and the TMDS D0-pin of the second interface chip unit 133, and the TMDS D0+ pin and the TMDS D0-pin transmit the first set of data differential signals to the display device. The second group of data differential signals are transmitted to the seventh ESD tube U35 through the thirteenth capacitor C223 and the fourteenth capacitor C224 of the second filtering unit. Subsequently, the seventh ESD tube U35 transmits the second set of data differential signals to the TMDS D1+ pin and the TMDS D1-pin of the second interface chip unit 133, and the TMDS D1+ pin and the TMDS D1-pin transmit the second set of data differential signals to the display device. The third group of data differential signals is transmitted to the eighth ESD tube U34 through the fifteenth capacitor C221 and the sixteenth capacitor C222 of the second filtering unit. Subsequently, the eighth ESD transistor U34 transmits the third set of data differential signals to the TMDS D2+ pin and the TMDS D2-pin of the second interface chip unit 133, and the TMDS D2+ pin and the TMDS D2-pin transmit the third set of data differential signals to the display device.

The utility model provides an interface circuit that can two kinds of compatible interface modes, this digital signal that can two kinds of compatible interface circuit accessible input module input host computer, this first interface module and second interface module all are connected with input module. When the first interface module is connected with the display device, the first interface module transmits the digital signal to the display device. When the second interface module is connected with the display device, the second interface module transmits the digital signal to the display device. The circuit can provide an HDMI interface and a DVI interface, so that a client can select a proper interface according to the condition of the display device, and the circuit can establish communication between the host and the display device. Because the HDMI interface and the DVI interface are respectively connected with the display equipment with different definition, the circuit can meet the requirement of using various display equipment by a user. The technical problem that the existing interface circuit is difficult to meet the requirements of users on using various display devices is effectively solved.

In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so that the scope of the present invention shall be determined by the scope of the appended claims.

Claims

1. An interface circuit compatible with two interface modes, comprising:

the input module is used for inputting a digital signal of the host;

2. The interface circuit according to claim 1, wherein the digital signals comprise Clock differential signals and three sets of data differential signals, the first interface module comprises a first interface chip unit, the first interface chip unit comprises a TMDS Clock + pin and a TMDS Clock-pin, and the TMDS Clock + pin and the TMDS Clock-pin are respectively connected to the first electrostatic discharge protection unit for transmitting the Clock differential signals; the first interface chip unit comprises a TMDSData0+ pin and a TMDSData 0-pin, wherein the TMDSData0+ pin and the TMDSData 0-pin are respectively connected with the first electrostatic protection unit and used for transmitting the first group of data differential signals;

the first interface chip unit comprises a TMDS Data1+ pin and a TMDS Data 1-pin, and the TMDS Data1+ pin and the TMDS Data 1-pin are respectively connected with the first electrostatic protection unit and used for transmitting a second group of Data differential signals; the first interface chip unit comprises a TMDS Data 2-pin and a TMDS Data2+ pin, and the TMDS Data2+ pin and the TMDS Data 2-pin are respectively connected with the first electrostatic protection unit and used for transmitting the third group of Data differential signals.

3. The interface circuit according to claim 2, wherein the second interface module comprises a second interface chip unit, the second interface chip unit comprises a TMDS CLK + pin and a TMDS CLK-pin, the TMDS CLK + pin and the TMDS CLK-pin are respectively connected to the second esd protection unit for transmitting the clock differential signal; the second interface chip unit comprises a TMDSD0+ pin and a TMDSD 0-pin, wherein the TMDSD0+ pin and the TMDSD 0-pin are respectively connected with the second electrostatic protection unit and are used for transmitting the first group of data differential signals;

the second interface chip unit comprises a TMDSD1+ pin and a TMDSD 1-pin, wherein the TMDSD1+ pin and the TMDSD 1-pin are respectively connected with the second electrostatic protection unit and are used for transmitting a second group of data differential signals; the second interface chip unit comprises a TMDSD2+ pin and a TMDSD 2-pin, wherein the TMDSD2+ pin and the TMDSD 2-pin are respectively connected with the second electrostatic protection unit and are used for transmitting the third group of data differential signals.

4. The interface circuit compatible with two interface modes according to claim 3, wherein the first interface module further comprises a first data transmission unit, one end of the first data transmission unit is connected to the host, and the other end of the first data transmission unit is connected to the first interface chip unit; the second interface module further comprises a second data transmission unit, one end of the second data transmission unit is connected with the host, the other end of the second data transmission unit is connected with the second interface chip unit, and the first data transmission unit or the second data transmission unit is used for transmitting information of the display device to the host.

5. The interface circuit according to claim 3, wherein the first interface chip unit comprises a HOST pin, the first interface module comprises a first TVS diode, one end of the first TVS diode is connected to the HOST pin, and the other end of the first TVS diode is grounded; the second interface chip unit comprises a Hot plus Delete pin, the first interface module comprises a second TVS diode, one end of the second TVS diode is connected with the Hot plus Delete pin, and the other end of the second TVS diode is grounded.

6. The interface circuit compatible with two interface modes according to claim 3, wherein the first interface module includes a first Power supply unit, the first interface chip unit includes a +5V Power pin, the first Power supply unit is connected to the +5V Power pin, and the first Power supply unit is configured to provide an operating voltage to the first interface chip unit;

7. The interface circuit according to claim 6, wherein the first Power supply unit comprises a first diode, an anode of the first diode is connected to a Power supply, and a cathode of the first diode is connected to the +5V Power pin;

8. The interface circuit compatible with two interface methods according to claim 7, wherein the first power supply unit further comprises a first filter capacitor, one end of the first filter capacitor is connected to the anode of the first diode, and the other end of the first filter capacitor is grounded; the second power supply unit further comprises a second filter capacitor, one end of the second filter capacitor is connected with the negative electrode of the second diode, and the other end of the second filter capacitor is grounded.

9. The interface circuit according to claim 8, wherein the first filter capacitor has a capacitance of 0.05-0.15 μ F, and the second filter capacitor has a capacitance of 0.05-0.15 μ F.

10. A numerical control apparatus comprising an interface circuit compatible with two interface modes according to any one of claims 1 to 9.