CN216956932U - EDP changes LVDS signal conversion circuit - Google Patents

EDP changes LVDS signal conversion circuit Download PDF

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Publication number
CN216956932U
CN216956932U CN202122557364.8U CN202122557364U CN216956932U CN 216956932 U CN216956932 U CN 216956932U CN 202122557364 U CN202122557364 U CN 202122557364U CN 216956932 U CN216956932 U CN 216956932U
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signal conversion
module
edp
conversion module
lvds
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李佳刚
罗章
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Huizhou Goldman Sachs Light Display Technology Co ltd
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Huizhou Goldman Sachs Light Display Technology Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The utility model relates to the technical field of circuits, in particular to an EDP (electronic data processing) to LVDS (low voltage differential signaling) signal conversion circuit, which is based on a CS5211 conversion chip and combined with a peripheral circuit to form a signal conversion circuit and realize the signal conversion from EDP to LVDS.

Description

EDP changes LVDS signal conversion circuit
Technical Field
The utility model relates to the technical field of circuits, in particular to a circuit for converting EDP (electronic data processing) signals into LVDS (low voltage differential signaling).
Background
With the development of times and the improvement of science and technology, various photoelectric products in China are continuously updated and updated in the process. The mainboard occupies an important position in photoelectric products, EDP signals are output by a plurality of mainboards at present, the serialization speed of an EDP interface is higher, three speeds of 1.6Gbps, 2.7Gbps and 5.4Gbps exist, the provided bandwidth is larger, only 2 pairs of high-speed differential lines are needed to complete 1080P60 high-definition video transmission at the speed of 2.7Gbps, the multifunctional high-definition video transmission system has a DHCP function, and the multifunctional high-definition video transmission system is widely applied to the fields of tablet computers, notebooks, all-in-one machines and the like. However, many liquid crystal panels only recognize the LVDS signals, so that a circuit system for converting EDP signals into LVDS signals is required, so that the main board and the screen can be well matched and lighted. Therefore, the circuit is born.
At present, the traditional mode is that the EDP mainboard is matched with the EDP screen, the LVDS mainboard is matched with the LVDS screen, the EDP mainboard cannot be matched when meeting the LVDS screen, only the screen or the mainboard can be replaced, waste is caused, the matching range is small, the EDP mainboard cannot be well matched with the LVDS screen, the cost is high, and waste is easily caused.
Therefore, the EDP mainboard is developed to be capable of adapting to the signal conversion circuit of the LVDS screen.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problems, the present invention provides a circuit for converting EDP to LVDS signal, which increases the adaptation range between the motherboard and the screen and reduces the cost.
In order to achieve the purpose, the utility model adopts the following technical scheme:
an EDP-to-LVDS signal conversion circuit, comprising:
the EDP input module is connected with an external mainboard to input an EDP signal and provide working voltage;
the signal conversion module receives the EDP signal conversion and outputs LVDS signals;
the filtering module is used for inputting an analog power supply and a digital power supply to the signal conversion module; the crystal oscillator module is used for providing a clock signal source for the signal conversion module;
and the LVDS output module is connected with the external XC board to output LVDS signals and provide working voltage.
Further, the crystal oscillator module includes a crystal X1, a capacitor C1, a capacitor C2 and a resistor R6, the capacitor C1 and the first end of the capacitor C2 are all grounded, the second end of the capacitor C2 is connected to the clock input terminal XTAL1 of the signal conversion module IC1, the second end of the capacitor C1 is connected to the clock output terminal XTALO of the signal conversion module IC1, the first end of the resistor R6 is connected to the second end of the capacitor C1, the second end of the resistor R6 is connected to the second end of the capacitor C2, the third end of the crystal X1 is connected to the second end of the capacitor C1, the first end of the crystal X1 is connected to the second end of the capacitor C2, and the second and fourth ends of the crystal X1 are grounded.
Further, the signal conversion circuit still includes the instruction module, the instruction module includes pilot lamp D1 and pilot lamp D2, pilot lamp D1 one end is connected the voltage input end EDP-3.3V of EDP input module, the pilot lamp D1 other end is connected signal conversion module IC's OLED foot, pilot lamp D2 one end is connected the voltage input end EDP-3.3V of EDP input module, the pilot lamp D2 other end is connected the GLED foot of signal conversion module for instruct signal conversion module operating condition and EDP signal input state.
Further, the signal conversion circuit further comprises a voltage stabilizing module, the voltage stabilizing module comprises a voltage stabilizing tube U1 and filter capacitors C5, C6 and C7, the input end of the voltage stabilizing tube U1 is connected with the voltage input end EDP3.3V of the EDP input module, the filter capacitor C5 is connected to the channel, the output end of the voltage stabilizing tube U1 is connected with the filter capacitors C6 and C7, and 1.8V is output after filtering.
Furthermore, the signal conversion module further comprises debugging ports GPIO _0, GPIO _1, GPIO _2 and GPIO _3, the four debugging ports are respectively and correspondingly connected with one ends of resistors R54, R55, R56 and R57, and the other ends of the resistors R54, R55, R56 and R57 are connected with a voltage input end EDP-3.3V of the EDP input module.
Further, the filtering module includes inductors L1, L2, and L3, a first end of the inductor L2 is connected to the EDP-3.3V of the voltage input terminal of the EDP input module, a second end of the inductor L2 is connected to the LVDD pin of the signal conversion module, and is configured to provide power for the LVDS output module and the debugging module, a first end of the inductor L1 is connected to the output terminal of the voltage regulator U1, a second end of the inductor L1 is connected to the analog power pin of the signal conversion module, so as to input analog power for the latter, a first end of the inductor L3 is connected to a first end of the inductor L1, and a second end of the inductor L3 is connected to the digital power pin of the signal conversion module, so as to input digital power for the latter.
Further, a second end of the inductor L1 is connected to the signal conversion module through a connection circuit, and is connected to capacitors C8, C9, C10, C11, and C12, specifically, one end of each of the capacitors C8, C9, C10, C11, and C12 is connected to a second end of the inductor L1, and the other end is grounded, a second end of the inductor L3 is connected to the signal conversion module through a connection circuit, and is connected to capacitors C17, C18, and C24, specifically, one end of each of the capacitors C17, C18, and C24 is connected to the second end of the inductor L3, and the other end is grounded, and a second end of the inductor L2 is connected to the signal conversion module through a connection circuit, and is connected to capacitors C13, C14, C15, and C25, specifically, one end of each of the capacitors C13, C14, C15, and C25 is connected to the second end of the inductor L2, and the other end is grounded.
Furthermore, the signal conversion module is connected with a debugging interface J1, which serves as a control instruction setting end and receives a control signal, a data end SDA of the debugging interface is connected with a pin S _ SDA of the signal conversion module, and a clock end SCL of the debugging interface is connected with a pin S _ SCL of the signal conversion module.
Furthermore, the EDP input module is configured with four main channels, two auxiliary channels and a hot plug detection channel, the main channels are DP _ IN _0P/0N, DP _ IN _1P/1N and are connected with the signal conversion module, the main channels are respectively connected with coupling capacitors C20, C21, C19 and C18 IN series, the auxiliary channels are DP _ IN _ AUXN/AUXP and are connected with the signal conversion module, and the hot plug detection channel is DP _ IN _ HPD and is connected with the signal conversion module.
Further, the signal conversion circuit further includes a memory module, the memory module is provided with a memory IC2 connected to the signal conversion module for modifying register settings, and specifically includes a memory IC2 and current limiting resistors R3, R4, R5, R7, R8, R9, a data end SDA of the memory IC2 is connected to a pin 12CM _ SDA of the signal conversion module, a data end SDA of the memory IC2 is connected to one end of a current limiting resistor R4, the other end of the current limiting resistor R4 is connected to a voltage input end EDP-3.3V of the EDP input module, a clock end SCL of the memory IC2 is connected to the pin 12CM _ SCL of the signal conversion module, a clock end SCL of the memory IC2 is connected to one end of the current limiting resistor R5, the other end of the current limiting resistor R5 is connected to a voltage input end EDP-3.3V of the EDP input module, a write-protection end WP 2 is connected to one end of the current limiting resistor R3, the other end of the current limiting resistor R3 is connected to a voltage input end EDP-3.3V of the EDP input module, the address input ends A0, A1 and A2 of the memory IC2 are connected with the voltage input end EDP-3.3V of the EDP input module, and the paths of the memory IC2 are respectively connected with current-limiting resistors R7, R8 and R9 in series.
The utility model has the beneficial effects that
The EDP-to-LVDS signal conversion circuit is simple in circuit and low in cost, and can convert the EDP signal into the LVDS signal, so that an EDP mainboard is matched with an LVDS screen, and resource waste is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a schematic diagram of a signal conversion circuit according to an embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a signal conversion module according to embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of a memory module according to embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of a voltage stabilization module according to embodiment 1 of the present invention;
FIG. 5 is a schematic diagram of a filtering module according to embodiment 1 of the present invention;
FIG. 6 is a schematic diagram of an indicating module according to embodiment 1 of the present invention;
fig. 7 is a schematic diagram of a crystal oscillator module according to embodiment 1 of the present invention;
FIG. 8 is a schematic diagram of an EDP input module according to embodiment 1 of the present invention;
fig. 9 is a schematic diagram of an LVDS output module according to an embodiment 1 of the utility model.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the intended purpose of the utility model, the following detailed description of the embodiments, structures, features and effects according to the present invention will be made with reference to the accompanying drawings and preferred embodiments.
Example 1
As shown in fig. 1, the present invention provides an EDP to LVDS signal conversion circuit for converting an EDP signal into an LVDS signal, the signal conversion circuit including: the EDP input module CN1 is connected with an external mainboard to input an EDP signal and provide working voltage of 3.3V, and the working voltage of 3.3V is reduced from external 12V voltage to 3.3V through the EDP input module CN 1; the signal conversion module IC1 receives the EDP signal for conversion and outputs an LVDS signal; the filtering module is used for inputting an analog power supply and a digital power supply to the signal conversion module; the crystal oscillator module is used for providing a clock signal source for the signal conversion module; the LVDS output module CN2 is connected to the external XC board to output LVDS signals and provide operating voltage, and in this embodiment, the signal conversion module IC1 is developed based on CS5211 adapter chip.
The crystal oscillator module comprises a crystal X1, a capacitor C1, a capacitor C2 and a resistor R6, the first end of the capacitor C1 and the first end of the capacitor C2 are all grounded, the second end of the capacitor C2 is connected with the clock input end XTAL1 of the signal conversion module, the second end of the capacitor C1 is connected with the clock output end XTALO of the signal conversion module, the first end of the resistor R6 is connected with the second end of the capacitor C1, the second end of the resistor R6 is connected with the second end of the capacitor C2, the third end of the crystal X1 is connected with the second end of the capacitor C1, the first end of the crystal X1 is connected with the second end of the capacitor C2, the second and fourth ends of the crystal X1 are grounded, and the crystal oscillator module is used for providing a precise external clock signal to the signal conversion module IC1 as a reference clock of the internal clock of the signal conversion module IC 1.
The signal conversion circuit further comprises an indicating module, the indicating module comprises indicating lamps D1 and D2, triodes Q1 and Q2, D1 and D2 are light emitting diodes, D1 is yellow, D2 is green and is used for distinguishing, Q1 and Q2 are NPN type triodes, the anode of the indicating lamp D1 is connected with the EDP input module CN1, the EDP-3.3V is connected in series with a resistor R13 on a path, the cathode of the indicating lamp D1 is connected with the collector of the triode Q1, the base of the triode Q1 is connected with the signal conversion module, the resistor R16 is connected in series with the path, the anode of the indicating lamp D2 is connected with the EDP-3.3V of the EDP input module CN1, the cathode of the indicating lamp D2 is connected with the GLED pin of the signal conversion module and is used for indicating the working state of the signal conversion module and the EDP signal input state, if the chip is in the working state, the output pin 3657 of the signal conversion module 1 is at high level, q2 is on and D2 lights up. When the EDP signal is input, pin 58 of the signal conversion module IC1 outputs high level, Q1 is conducted, and D1 is lighted.
The signal conversion circuit further comprises a voltage stabilizing module, the voltage stabilizing module comprises a voltage stabilizing tube U1 and filter capacitors C5, C6 and C7, the input end of the voltage stabilizing tube U1 is connected with the voltage input end EDP-3.3V of the EDP input module CN1, the voltage of the 3.3V is subjected to filtering by the filter capacitor C5, then is subjected to voltage reduction by the voltage stabilizing tube U1, and then is subjected to filtering by the filter capacitors C6 and C7 to output 1.8V voltage. 1.8V voltage is input into a 1-pin hard piece reset end of a signal conversion module IC1 through a current-limiting resistor R12 to start the operation, a1 pin of the signal conversion module IC1 plays a role of a switch, the 1 pin of the signal conversion module IC1 is also connected with a capacitor C4, one end of the capacitor C4 is connected with the 1 pin of the signal conversion module IC1, the other end of the capacitor C4 is grounded, the inductor L1 isolates high-frequency interference and filters capacitors C8, C9, 10, C11 and C12 to input analog power supply ends of 3,4 and 60 pins of a signal conversion module IC1, and the inductor L3 isolates high-frequency interference and filters C16, C17 and C24 to input digital power supply ends of 7 and 42 pins of the signal conversion module IC 1.
The signal conversion module IC1 further comprises debugging ports GPIO _0, GPIO _1, GPIO _2 and GPIO _3, the four debugging ports are respectively and correspondingly connected with one ends of resistors R54, R55, R56 and R57, and the other ends of the resistors R54, R55, R56 and R57 are connected with the voltage input end EDP-3.3V of the EDP input module CN 1.
The filtering module comprises inductors L1, L2 and L3, a first end of the inductor L2 is connected to the voltage input end EDP-3.3V of the EDP input module CN1, a second end of the inductor L2 is connected to the LVDD pin of the signal conversion module IC1, and is used for providing power for the LVDS output module CN2 and the debugging module, a first end of the inductor L1 is connected to the output end of the regulator tube U1, a second end of the inductor L1 is connected to the analog power pin of the signal conversion module IC1, and inputs an analog power for the latter, a first end of the inductor L3 is connected to a first end of the inductor L3, a second end of the inductor L3 is connected to the digital power pin of the signal conversion module IC 3, and inputs a digital power for the latter, a connection path between the second end of the inductor L3 and the signal conversion module IC 3 is connected to capacitors C3, C3 and C3, and a second end of the inductor 3 is connected to the second end of the C3, the other end of the inductor L3 is grounded, a second end of the inductor L3 is connected to a connection circuit of the signal conversion module, where the second end of the inductor L3 is connected to capacitors C17, C18 and C24, specifically, one ends of the capacitors C17, C18 and C24 are connected to a second end of the inductor L3, the other end of the capacitors C2 is grounded, a second end of the inductor L2 is connected to a connection circuit of the signal conversion module, where the capacitors C13, C14, C15 and C25 are connected, specifically, one ends of the capacitors C13, C14, C15 and C25 are connected to a second end of the inductor L2, and the other end of the capacitors is grounded.
The signal conversion module is connected with a debugging interface J1, which is used as a control instruction setting end and receives a control signal to convert an EDP signal into an LVDS signal, the control instruction setting end comprises a data end SDA and is connected with a pin 54 of the signal conversion module, and a clock end SCL of the debugging interface is connected with a pin 53 of the signal conversion module.
The EDP input module CN1 is configured with two main channels, an auxiliary channel and a hot plug detection channel, the main channel is DP _ IN _0P/0N, DP _ IN _1P/1N and is connected to the signal conversion module, the main channel is respectively connected IN series with coupling capacitors C20, C21, C19 and C18, the auxiliary channel is DP _ IN _ AUXN/AUXP and is respectively connected to pins 43 and 44 of the signal conversion module IC1, the hot plug detection channel is DP _ IN _ HPD and is connected to pin 59 of the signal conversion module IC1, the channel is further connected with a resistor R10 and a resistor R20, a first end of the resistor R10 is connected to the hot plug detection channel, the other end is connected to pin 59 of the signal conversion module IC1, one end of the resistor R20 is connected to the first end of the resistor R10, and the other end is grounded, IN this embodiment, the LVDS output module CN2 is configured with eight output channels, which are LVDS _ dsa pin 0/N _0, LVDSA _ DAT _ N1/P1, LVDSA _ DAT _ N2/P2, LVDSA _ DAT _ N3/P3, LVDSB _ DAT _ N0/P0, LVDSB _ DAT _ N1/P1, LVDSB _ DAT _ N2/P2 and LVDSB _ DAT _ N3/P3, each four output channels are provided with a group of clock pins, specifically LVDSA _ CLK-/+, LVDSB _ CLK-/+, and two groups of clock pins transmit signals faster than one group of clock pins; each set of clock is combined with four sets of LVDS signals, the RGB signals are transmitted in the output channel, and the transmission rate is controlled by the clock period.
The signal conversion circuit further comprises a memory module, the memory module is provided with a memory IC2 connected with the signal conversion module IC1 and used for modifying register settings, and specifically comprises a memory IC2 and current-limiting resistors R3, R4, R5, R7, R8 and R9, a memory IC2 data end SDA is connected with a 12CM _ SDA pin of the signal conversion module, a memory IC2 data end SDA is connected with one end of a current-limiting resistor R4, the other end of the current-limiting resistor R4 is connected with a voltage input end EDP-3.3V of the EDP input module CN1, a memory IC2 clock end SCL is connected with the 12CM _ SCL pin of the signal conversion module, a memory IC2 clock end SCL is connected with one end of the current-limiting resistor R5, the other end of the current-limiting resistor R5 is connected with the voltage input end EDP-3.3V of the EDP input module CN1, a memory IC2 write protection end WP-limiting resistor R3, the other end of the current-limiting resistor R3 is connected with an EDP input end EDP 3-3V of the EDP input module CN 46, the address input ends A0, A1 and A2 of the memory IC2 are connected with the voltage input end EDP-3.3V of the EDP input module CN1, and the paths of the memory IC2 are respectively connected with current-limiting resistors R7, R8 and R9 in series.
And (3) signal conversion process:
the EDP signal is input from CN1, the differential data signal output by the main channel is input from pins 3,4 and 6,7 of CN1 through coupling capacitors C18, C19, C20, C21 to pins 60,61,63,64 of IC1, the AUX auxiliary channel differential signal is input from pins 9,10 of CN1 through coupling capacitors C22, C23 to pins 33,34 of IC1, the HPD hot plug detection channel is input from pin 17 of CN1 to pin 58 of IC1 in one way, R20 is pull-down resistor, and R10 is current-limiting resistor. After conversion by IC1, the dual 8-channel LVDS low-voltage differential signal is output to CN 2.
Example 2
A conversion processor comprises a mainboard, a signal conversion circuit and an LVDS display module, wherein the input end of the signal conversion circuit is electrically connected with the mainboard to receive an EDP signal sent by the processor and convert the EDP signal into an LVDS signal, and the output end of the signal conversion circuit is electrically connected with the LVDS display module to send the processed LVDS signal to the LVDS display module.
Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present invention.

Claims (10)

1. An EDP to LVDS signal conversion circuit, comprising:
the EDP input module is connected with an external mainboard to input an EDP signal and provide working voltage;
the signal conversion module receives the EDP signal conversion and outputs LVDS signals;
the filtering module is used for inputting an analog power supply and a digital power supply to the signal conversion module;
the crystal oscillator module is used for providing a clock signal source for the signal conversion module;
and the LVDS output module is connected with the external XC board to output LVDS signals and provide working voltage.
2. The EDP to LVDS signal conversion circuit according to claim 1, wherein: the crystal oscillator module comprises a crystal X1, a capacitor C1, a capacitor C2 and a resistor R6, the capacitor C1 and the first end of the capacitor C2 are all grounded, the second end of the capacitor C2 is connected with the clock input end XTAL1 of the signal conversion module, the second end of the capacitor C1 is connected with the clock output end XTALO of the signal conversion module, the first end of the resistor R6 is connected with the second end of the capacitor C1, the second end of the resistor R6 is connected with the second end of the capacitor C2, the third end of the crystal X1 is connected with the second end of the capacitor C1, the first end of the crystal X1 is connected with the second end of the capacitor C2, and the second and fourth ends of the crystal X1 are grounded.
3. The EDP-to-LVDS signal conversion circuit according to claim 1, wherein: the signal conversion circuit still includes the pilot module, the pilot module includes pilot lamp D1 and pilot lamp D2, pilot lamp D1 one end is connected the voltage input end EDP-3.3V of EDP input module, the pilot lamp D1 other end is connected the OLED foot of signal conversion module, pilot lamp D2 one end is connected the voltage input end EDP-3.3V of EDP input module, the pilot lamp D2 other end is connected the GLED foot of signal conversion module for indicate signal conversion module operating condition and EDP signal input state.
4. The EDP to LVDS signal conversion circuit according to claim 1, wherein: the signal conversion circuit further comprises a voltage stabilizing module, the voltage stabilizing module comprises a voltage stabilizing tube U1 and filter capacitors C5, C6 and C7, the input end of the voltage stabilizing tube U1 is connected with the voltage input end EDP3.3V of the EDP input module, the filter capacitor C5 is connected to the channel, the output end of the voltage stabilizing tube U1 is connected with the filter capacitors C6 and C7, and 1.8V is output after filtering.
5. The EDP-to-LVDS signal conversion circuit according to claim 1, wherein: the signal conversion module further comprises debugging ports GPIO _0, GPIO _1, GPIO _2 and GPIO _3, the four debugging ports are respectively and correspondingly connected with one ends of resistors R54, R55, R56 and R57, and the other ends of the resistors R54, R55, R56 and R57 are connected with a voltage input end EDP-3.3V of the EDP input module.
6. The EDP-to-LVDS signal conversion circuit according to claim 4, wherein: the filtering module comprises inductors L1, L2 and L3, wherein a first end of the inductor L2 is connected with an EDP-3.3V voltage input end of the EDP input module, a second end of the inductor L2 is connected with an LVDD pin of the signal conversion module and used for providing power for the LVDS output module and the debugging module, a first end of the inductor L1 is connected with an output end of the voltage regulator tube U1, a second end of the inductor L1 is connected with an analog power pin of the signal conversion module and used for inputting analog power for the latter, a first end of the inductor L3 is connected with a first end of the inductor L1, and a second end of the inductor L3 is connected with a digital power pin of the signal conversion module and used for inputting digital power for the latter.
7. The EDP-to-LVDS signal conversion circuit of claim 6, wherein: the second end of the inductor L1 is connected with the signal conversion module, the second end of the inductor L3 is connected with the signal conversion module, and the second end of the inductor L2 is connected with the signal conversion module.
8. The EDP-to-LVDS signal conversion circuit according to claim 1, wherein: the signal conversion module is connected with a debugging interface J1, which is used as a control instruction setting end and receives a control signal, a debugging interface data end SDA is connected with the signal conversion module S _ SDA pin, and a debugging interface clock end SCL is connected with the signal conversion module S _ SCL pin.
9. The EDP to LVDS signal conversion circuit according to claim 1, wherein: the EDP input module is provided with four main channels, two auxiliary channels and a hot plug detection channel, the main channels are DP _ IN _0P/0N, DP _ IN _1P/1N and are connected with the signal conversion module, the auxiliary channels are DP _ IN _ AUXN/AUXP and are connected with the signal conversion module, and the hot plug detection channel is DP _ IN _ HPD and is connected with the signal conversion module.
10. The EDP-to-LVDS signal conversion circuit according to claim 1, wherein: the signal conversion circuit further comprises a storage module, wherein the storage module is provided with a memory IC2 connected with the signal conversion module and used for modifying register setting, a data end SDA of a memory IC2 is connected with a pin 12CM _ SDA of the signal conversion module, and a clock end SCL of a memory IC2 is connected with a pin 12CM _ SCL of the signal conversion module.
CN202122557364.8U 2021-10-19 2021-10-19 EDP changes LVDS signal conversion circuit Active CN216956932U (en)

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CN202122557364.8U CN216956932U (en) 2021-10-19 2021-10-19 EDP changes LVDS signal conversion circuit

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CN202122557364.8U CN216956932U (en) 2021-10-19 2021-10-19 EDP changes LVDS signal conversion circuit

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CN216956932U true CN216956932U (en) 2022-07-12

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