CN217360133U - Distributed non-contact fault acquisition system - Google Patents
Distributed non-contact fault acquisition system Download PDFInfo
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- CN217360133U CN217360133U CN202220520279.6U CN202220520279U CN217360133U CN 217360133 U CN217360133 U CN 217360133U CN 202220520279 U CN202220520279 U CN 202220520279U CN 217360133 U CN217360133 U CN 217360133U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
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Abstract
The utility model discloses a distributing type non-contact fault collection system. The distributed non-contact fault acquisition system comprises: the first acquisition unit comprises a first magnetic field sensor, a first differential-to-single-ended circuit and a first operational amplifier circuit, wherein the first magnetic field sensor is arranged along the transmission direction of the power transmission line; the second acquisition unit comprises a second magnetic field sensor and a second differential-to-single-ended circuit, the second magnetic field sensor is electrically connected with the second differential-to-single-ended circuit, and the second magnetic field sensor is arranged perpendicular to the transmission direction of the transmission line; third acquisition unit, change single-ended circuit, filter circuit and third operational amplifier circuit including third magnetic field sensor, third difference, third magnetic field sensor sets up along the reverse direction of the transmission direction of power transmission line, the utility model discloses set up magnetic field acquisition unit respectively in the equidirectional not, the multiple spot position is gathered, gathers more accurately.
Description
Technical Field
The utility model relates to a transmission line trouble collection technology field especially relates to a distributing type non-contact trouble collection system.
Background
The fixed collection of present transmission line is usually at a line tower collection equipment, but because the locating position is put at will, does not have the pointed processing, leads to the signal of gathering inaccurate, easily leaks out the fault signal.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to provide a distributed non-contact fault collection system that collection precision is high.
In order to solve the above problem, the utility model provides a distributing type non-contact fault collection system, distributing type non-contact fault collection system includes:
the first acquisition unit comprises a first magnetic field sensor, a first differential-to-single-ended circuit and a first operational amplifier circuit, wherein the first magnetic field sensor is arranged along the transmission direction of the power transmission line, the first magnetic field sensor is electrically connected with the first differential-to-single-ended circuit, the first magnetic field sensor outputs differential signals, and a single-ended signal is obtained through processing of the first differential-to-single-ended circuit; the first differential-to-single-ended circuit is electrically connected with a first operational amplifier circuit, and the first operational amplifier circuit amplifies a single-ended signal to obtain a first output signal;
the second magnetic field sensor is electrically connected with the second differential-to-single-ended circuit and arranged perpendicular to the transmission direction of the power transmission line, and outputs a differential signal which is processed by the second differential-to-single-ended circuit;
the third acquisition unit comprises a third magnetic field sensor, a third differential-to-single-ended circuit, a filter circuit and a third operational amplifier circuit, wherein the third magnetic field sensor is arranged along the opposite direction of the transmission direction of the power transmission line; the third magnetic field sensor is electrically connected with the third differential-to-single-ended circuit, outputs a differential signal, and obtains a single-ended signal through processing of the third differential-to-single-ended circuit; the third differential-to-single-ended circuit is electrically connected with the filter circuit, the filter circuit filters the single-ended signal, the filter circuit is electrically connected with the third operational amplifier circuit, and the third operational amplifier circuit processes and outputs a second output signal.
Further, the first differential-to-single-ended circuit comprises a processor U1, a first pin of the processor U1 is electrically connected with an 8 th pin of the processor U1 through an adjustable resistor R1, the first magnetic field sensor is electrically connected with a 2 nd pin and a 3 rd pin of the processor U1, a 4 th pin of the processor U1 is grounded through a capacitor C7, a capacitor C5 and a capacitor C6 are connected in parallel with a capacitor C7, a 6 th pin of the processor U1 is sequentially connected in series with a resistor R3, a capacitor C11 and an operational amplifier circuit to be electrically connected, a 7 th pin of the processor U1 is grounded through a capacitor C1, and the capacitor C2 is connected in parallel with the capacitor C1.
Further, the first operational amplifier circuit comprises an operational amplifier chip U2 and a capacitor C10, the first differential-to-single-ended circuit is electrically connected with a 3 rd pin of the operational amplifier chip U2, a 5 th pin of the operational amplifier chip U2 is electrically connected with the capacitor C10 and then grounded, a 4 th pin of the operational amplifier chip U2 is electrically connected with a1 st pin, and a1 st pin of the operational amplifier chip U2 outputs a first output signal.
Further, the second differential-to-single-ended circuit comprises a processor U3, a first pin of the processor U3 is electrically connected with an 8 th pin of the processor U3 through an adjustable resistor R5, the first magnetic field sensor is electrically connected with a 2 nd pin and a 3 rd pin of the processor U3, a 4 th pin of the processor U3 is grounded through a capacitor C14, a capacitor C12 and a capacitor C13 are connected in parallel with a capacitor C14, a 6 th pin of the processor U3 is connected with a resistor R7 and outputs a second output signal, a 7 th pin of the processor U3 is grounded through a capacitor C8, and the capacitor C9 is connected in parallel with the capacitor C8.
Further, the third differential-to-single-ended circuit comprises a processor U7, a first pin of the processor U7 is electrically connected with an 8 th pin of the processor U7 through an adjustable resistor R9, the first magnetic field sensor is electrically connected with a 2 nd pin and a 3 rd pin of the processor U7, a 4 th pin of the processor U7 is grounded through a capacitor C24, a capacitor C22 and a capacitor C23 are connected in parallel with the capacitor C24, a 6 th pin of the processor U7 is sequentially connected in series with a resistor R11, a capacitor C21 and an operational amplifier circuit to be electrically connected, a 7 th pin of the processor U7 is grounded through a capacitor C15, and the capacitor C16 is connected in parallel with the capacitor C15.
Further, the first operational amplifier circuit comprises a processor U5, a processor U6, a processor U8 and a processor U9, a first pin of the processor U5 is electrically connected to a 4 th pin of the processor U5, a 2 nd pin of the processor U5 is grounded, a 3 rd pin of the processor U5 is electrically connected to a capacitor C18, the capacitor C18 is electrically connected to the differential-to-single-ended circuit and a resistor R15 through a capacitor C17, the resistor R15 is electrically connected to a 3 rd pin through a resistor R16, the resistor R15 is also electrically connected to a1 st pin of the processor U8 through a capacitor C25, the capacitor C18 is also electrically connected to a1 st pin of the processor U8 through a resistor R12, a1 st pin of the processor U8 is also electrically connected to a 4 th pin thereof, a 2 nd pin of the processor U8 is grounded, a 3 rd pin of the processor U8 is electrically connected to a 4 th pin of the processor U5 through a resistor VR1, the first pin of the processor U6 is electrically connected to the 4 th pin of the processor U6, the 2 nd pin of the processor U6 is grounded, the 3 rd pin of the processor U6 is electrically connected to the capacitor C20, the capacitor C20 is electrically connected to the 4 th pin of the processor U5 and the resistor R17 through the capacitor C19, the resistor R17 is electrically connected to the 3 rd pin through the resistor R18, the resistor R17 is also electrically connected to the 1 st pin of the processor U9 through the capacitor C26, the capacitor C20 is also electrically connected to the 1 st pin of the processor U9 through the resistor R13, the 1 st pin of the processor U9 is also electrically connected to the 4 th pin thereof, the 2 nd pin of the processor U9 is grounded, the 3 rd pin of the processor U9 is electrically connected to the 4 th pin of the processor U6 through the resistor VR2, and the 1 st pin of the processor U6 is also electrically connected to the third operational amplifier circuit.
Further, the third operational amplifier circuit includes an operational amplifier chip U10 and a capacitor C10, the first differential-to-single-ended circuit is electrically connected to a 3 rd pin of the operational amplifier chip U10, a 5 th pin of the operational amplifier chip U10 is electrically connected to the capacitor C10 and then grounded, a 4 th pin of the operational amplifier chip U10 is electrically connected to a1 st pin, and a1 st pin of the operational amplifier chip U10 outputs a third output signal.
The utility model discloses distributing type non-contact fault collection system sets up magnetic field collection unit respectively in the equidirectional, and the multiple spot position is gathered, gathers more accurately, and carries out the pertinence circuit optimization to different positions, ensures that the information of gathering is accurate, and the precision is high.
Drawings
Fig. 1 is a schematic diagram of a preferred embodiment of a distributed non-contact fault collection system of the present invention.
Fig. 2 is a circuit diagram of a first differential to single-ended circuit.
Fig. 3 is a circuit diagram of the first operational amplifier circuit.
Fig. 4 is a circuit diagram of a second differential to single-ended circuit.
Fig. 5 is a circuit diagram of a third differential to single-ended circuit.
Fig. 6 is an enlarged view of the filter circuit.
Fig. 7 is a circuit diagram of a third operational amplifier circuit.
Detailed Description
The present invention will be further explained with reference to the accompanying drawings.
As shown in fig. 1, the preferred embodiment of the distributed non-contact fault collection system of the present invention includes a first collection unit 100, a second collection unit 200 and a third collection unit 300, wherein the first collection unit 100, the second collection unit 200 and the third collection unit 300 are all used for collecting the spatial magnetic field variation of the power transmission line, and respectively process and output the collected magnetic field signal as a first output signal, a second output signal and a third output signal.
The first acquisition unit 100 comprises a first magnetic field sensor 101, a first differential-to-single-ended circuit 102 and a first operational amplifier circuit 103, wherein the first magnetic field sensor 101 is arranged along the transmission direction of the transmission line; the first magnetic field sensor 101 is electrically connected with the first differential-to-single-ended circuit 102, the first magnetic field sensor 101 outputs a differential signal, and a single-ended signal is obtained by processing the differential signal through the first differential-to-single-ended circuit 102; the first differential-to-single-ended circuit 102 is electrically connected to a first operational amplifier circuit 103, and the first operational amplifier circuit 103 amplifies a single-ended signal to obtain a first output signal. The magnetic field signal at the position of the first magnetic field sensor 101 is weaker, and the electric signal is enhanced through the first operational amplifier circuit 103, so that the change of the magnetic field can be accurately acquired by the first acquisition unit 100, and the accuracy of signal acquisition is improved.
As shown in fig. 2, the first differential-to-single-ended circuit 102 includes a processor U1, an adjustable resistor R1, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C5, a capacitor C6, a capacitor C7, and a capacitor C11. The processor U1 adopts an INA128UA/2K5 chip, a first pin of the processor U1 is electrically connected with one end of an adjustable resistor R1, and the other end of the adjustable resistor U1 is electrically connected with an 8 th pin of the processor U1. The output of the first magnetic field sensor 101 is electrically connected to the 2 nd and 3 rd pins of the processor U1. The 4 th pin of the processor U1 is electrically connected to one end of the capacitor C7, the other end of the capacitor C7 is grounded, and the capacitor C5 and the capacitor C6 are connected in parallel with the capacitor C7. The 5 th pin of the processor U1 is grounded. The 6 th pin of the processor U1 is electrically connected with one end of the resistor R3, the other end of the resistor R3 is electrically connected with one end of the capacitor C11, and the other end of the capacitor C11 is electrically connected with the operational amplifier circuit. The 7 th pin of the processor U1 is electrically connected to one end of a capacitor C1, the other end of the capacitor C1 is grounded, and the capacitor C2 is connected in parallel with the capacitor C1.
As shown in fig. 3, the first operational amplifier circuit 103 includes an operational amplifier chip U2 and a capacitor C10, and the operational amplifier chip U2 employs GS 8551-TR. The first differential-to-single-ended circuit 102 is electrically connected with a 3 rd pin of the operational amplifier chip U2, a 2 nd pin of the operational amplifier chip U2 is grounded, a 5 th pin of the operational amplifier chip U2 is grounded after being electrically connected with the capacitor C10, a 4 th pin of the operational amplifier chip U2 is electrically connected with a1 st pin, and a1 st pin of the operational amplifier chip U2 outputs a first output signal.
The second acquisition unit 200 comprises a second magnetic field sensor 201 and a second differential-to-single-ended circuit 202, the second magnetic field sensor 201 is electrically connected with the second differential-to-single-ended circuit 202, and the second magnetic field sensor 201 is arranged perpendicular to the transmission direction of the power transmission line; the second magnetic field sensor 201 outputs a differential signal, and a single-ended signal, i.e., a second output signal, is obtained through processing by the second differential-to-single-ended circuit 202; because the position of second magnetic field sensor 201, the magnetic field signal is strong, and does not have the clutter, consequently only need with differential signal trun into single-ended signal can to subsequent electronic equipment discerns this signal.
As shown in fig. 4, the second differential-to-single-ended circuit 202 includes a processor U3, an adjustable resistor R5, a resistor R7, a capacitor C8, a capacitor C9, a capacitor C12, a capacitor C13, and a capacitor C14. The processor U3 adopts an INA128UA/2K5 chip, a1 st pin of the processor U3 is electrically connected with one end of an adjustable resistor U3, and the other end of the adjustable resistor R5 is electrically connected with an 8 th pin of the processor U3. The output of the first magnetic field sensor 101 is electrically connected to the 2 nd and 3 rd pins of the processor U3. The 4 th pin of the processor U3 is electrically connected to one end of the capacitor C14, the other end of the capacitor C14 is grounded, and the capacitor C12 and the capacitor C13 are connected in parallel with the capacitor C14. The 5 th pin of the processor U3 is grounded. The 6 th pin of the processor U3 is electrically connected to one end of the resistor R7, and the other end of the resistor R7 outputs a second output signal. The 7 th pin of the processor U3 is electrically connected to one end of a capacitor C8, the other end of the capacitor C8 is grounded, and the capacitor C9 is connected in parallel with the capacitor C8.
The third acquisition unit 300 includes a third magnetic field sensor 301, a third differential-to-single-ended circuit 302, a filter circuit 303, and a third operational amplifier circuit 304, where the third magnetic field sensor 301 is arranged along a direction opposite to a transmission direction of the power transmission line; the third magnetic field sensor 301 is electrically connected to the third differential-to-single-ended circuit 302, and the third magnetic field sensor 301 outputs a differential signal, which is processed by the third differential-to-single-ended circuit 302 to obtain a single-ended signal; the third differential-to-single-ended circuit 302 is electrically connected to a filter circuit 303, and the filter circuit 303 filters the single-ended signal to a third output signal. The magnetic field signal at the position of the third magnetic field sensor 301 has a clutter, the signal interference of the power frequency of 50Hz of the power transmission line is eliminated through the filter circuit 303, the accuracy of the acquired signal is ensured, the change of the magnetic field which can be accurately acquired by the third acquisition unit 300 is ensured, and the accuracy of signal acquisition is improved.
As shown in fig. 5, the third differential-to-single-ended circuit 302 includes a processor U7, an adjustable resistor R9, a resistor R11, a capacitor C15, a capacitor C16, a capacitor C22, a capacitor C23, a capacitor C24, and a capacitor C21. The processor U7 adopts an INA128UA/2K5 chip, a first pin of the processor U7 is electrically connected with one end of an adjustable resistor R9, and the other end of the adjustable resistor U7 is electrically connected with an 8 th pin of the processor U7. The output of the first magnetic field sensor 101 is electrically connected to the 2 nd and 3 rd pins of the processor U7. The 4 th pin of the processor U7 is electrically connected to one end of the capacitor C24, the other end of the capacitor C24 is grounded, and the capacitor C22 and the capacitor C23 are connected in parallel with the capacitor C24. The 5 th pin of the processor U7 is grounded. The 6 th pin of the processor U7 is electrically connected with one end of the resistor R11, the other end of the resistor R11 is electrically connected with one end of the capacitor C21, and the other end of the capacitor C21 is electrically connected with the operational amplifier circuit. The 7 th pin of the processor U7 is electrically connected to one end of a capacitor C15, the other end of the capacitor C15 is grounded, and the capacitor C16 is connected in parallel with the capacitor C15.
As shown in fig. 6, the filter circuit 303 includes a processor U5, a processor U6, a processor U8, a processor U9, a resistor R12, a resistor R15, a resistor R16, a resistor VR1, a resistor R13, a resistor R17, a resistor R18, a resistor VR2, a capacitor C17, a capacitor C18, a capacitor C25, a capacitor C19, a capacitor C20, and a capacitor C26, where each of the processor U5, the processor U6, the processor U8, and the processor U9 is GS 8551-TR. The first pin of processor U5 with processor U5's 4 th pin is connected, processor U5's 2 nd pin ground, processor U5's 3 rd pin is connected with electric capacity C18 electricity, electric capacity C18 changes single-ended circuit and resistance R15 electricity through electric capacity C17 and difference and is connected, resistance R15 is connected with 3 rd pin electricity through resistance R16, resistance R15 still is connected with processor U8's 1 st pin electricity through electric capacity C25, electric capacity C18 still is connected with processor U8's 1 st pin electricity through resistance R12. The 1 st pin of the processor U8 is also electrically connected with the 4 th pin thereof, the 2 nd pin of the processor U8 is grounded, and the 3 rd pin of the processor U8 is electrically connected with the 4 th pin of the processor U5 through a resistor VR 1. The first pin of processor U6 with processor U6's 4 th pin is connected, processor U6's 2 nd pin ground, processor U6's 3 rd pin is connected with electric capacity C20 electricity, electric capacity C20 is connected with processor U5's 4 th pin and resistance R17 electricity through electric capacity C19, resistance R17 is connected with 3 rd pin electricity through resistance R18, resistance R17 still is connected with processor U9's 1 st pin electricity through electric capacity C26, electric capacity C20 still is connected with processor U9's 1 st pin electricity through resistance R13. The 1 st pin of the processor U9 is further electrically connected to the 4 th pin thereof, the 2 nd pin of the processor U9 is grounded, the 3 rd pin of the processor U9 is electrically connected to the 4 th pin of the processor U6 through a resistor VR2, and the 1 st pin of the processor U6 is further electrically connected to the third operational amplifier circuit 304.
As shown in fig. 7, the third operational amplifier circuit 304 includes an operational amplifier chip U10 and a capacitor C10, and the operational amplifier chip U10 employs GS 8551-TR. The first differential-to-single-ended circuit 102 is electrically connected with a 3 rd pin of the operational amplifier chip U10, a 2 nd pin of the operational amplifier chip U10 is grounded, a 5 th pin of the operational amplifier chip U10 is grounded after being electrically connected with the capacitor C10, a 4 th pin of the operational amplifier chip U10 is electrically connected with a1 st pin, and a1 st pin of the operational amplifier chip U10 outputs a third output signal.
The utility model discloses set up magnetic field collection unit respectively in the not equidirectional in magnetic field, the multiple spot position is gathered, gathers more accurately, and carries out the pertinence circuit optimization to different positions, ensures that the information of gathering is accurate, and the precision is high.
The above is only the embodiment of the present invention, not the limitation of the patent scope of the present invention, all the equivalent structures made by the contents of the specification and the drawings are directly or indirectly applied to other related technical fields, all the same principle is within the patent protection scope of the present invention.
Claims (7)
1. A distributed non-contact fault acquisition system is characterized in that: the method comprises the following steps:
the first acquisition unit comprises a first magnetic field sensor, a first differential-to-single-ended circuit and a first operational amplifier circuit, wherein the first magnetic field sensor is arranged along the transmission direction of the power transmission line, the first magnetic field sensor is electrically connected with the first differential-to-single-ended circuit, the first magnetic field sensor outputs differential signals, and a single-ended signal is obtained through processing of the first differential-to-single-ended circuit; the first differential-to-single-ended circuit is electrically connected with a first operational amplifier circuit, and the first operational amplifier circuit amplifies a single-ended signal to obtain a first output signal;
the second magnetic field sensor is electrically connected with the second differential-to-single-ended circuit and arranged perpendicular to the transmission direction of the power transmission line, and outputs a differential signal which is processed by the second differential-to-single-ended circuit;
the third acquisition unit comprises a third magnetic field sensor, a third differential-to-single-ended circuit, a filter circuit and a third operational amplifier circuit, wherein the third magnetic field sensor is arranged along the opposite direction of the transmission direction of the power transmission line; the third magnetic field sensor is electrically connected with the third differential-to-single-ended circuit, outputs a differential signal, and obtains a single-ended signal through processing of the third differential-to-single-ended circuit; the third differential-to-single-ended circuit is electrically connected with the filter circuit, the filter circuit filters the single-ended signal, the filter circuit is electrically connected with the third operational amplifier circuit, and the third operational amplifier circuit processes and outputs a second output signal.
2. The distributed non-contact fault collection system of claim 1, wherein: the first differential-to-single-ended circuit comprises a processor U1, a first pin of the processor U1 is electrically connected with an 8 th pin of the processor U1 through an adjustable resistor R1, a first magnetic field sensor is electrically connected with a 2 nd pin and a 3 rd pin of the processor U1, a 4 th pin of the processor U1 is grounded through a capacitor C7, a capacitor C5 and a capacitor C6 are connected with a capacitor C7 in parallel, a 6 th pin of the processor U1 is sequentially connected with a resistor R3, a capacitor C11 and an operational amplifier circuit in series and electrically connected, a 7 th pin of the processor U1 is grounded through a capacitor C1, and the capacitor C2 is connected with the capacitor C1 in parallel.
3. The distributed non-contact fault collection system of claim 1, wherein: the first operational amplifier circuit comprises an operational amplifier chip U2 and a capacitor C10, a 3 rd pin of the first differential-to-single-ended circuit and an operational amplifier chip U2 is electrically connected, a 5 th pin of the operational amplifier chip U2 is electrically connected with the capacitor C10 and then grounded, a 4 th pin of the operational amplifier chip U2 is electrically connected with a1 st pin, and a1 st pin of the operational amplifier chip U2 outputs a first output signal.
4. The distributed non-contact fault collection system of claim 1, wherein: the second differential-to-single-ended circuit comprises a processor U3, a first pin of the processor U3 is electrically connected with an 8 th pin of the processor U3 through an adjustable resistor R5, a first magnetic field sensor is electrically connected with a 2 nd pin and a 3 rd pin of the processor U3, a 4 th pin of the processor U3 is grounded through a capacitor C14, a capacitor C12 and a capacitor C13 are connected in parallel with a capacitor C14, a 6 th pin of the processor U3 is connected with a resistor R7 and outputs a second output signal, a 7 th pin of the processor U3 is grounded through a capacitor C8, and the capacitor C9 is connected in parallel with the capacitor C8.
5. The distributed non-contact fault collection system of claim 1, wherein: the third differential-to-single-ended circuit comprises a processor U7, a first pin of the processor U7 is electrically connected with an 8 th pin of the processor U7 through an adjustable resistor R9, a first magnetic field sensor is electrically connected with a 2 nd pin and a 3 rd pin of the processor U7, a 4 th pin of the processor U7 is grounded through a capacitor C24, a capacitor C22 and a capacitor C23 are connected with a capacitor C24 in parallel, a 6 th pin of the processor U7 is sequentially connected with a resistor R11, a capacitor C21 and an operational amplifier circuit in series, a 7 th pin of the processor U7 is grounded through a capacitor C15, and the capacitor C16 is connected with the capacitor C15 in parallel.
6. The distributed non-contact fault collection system of claim 1, wherein: the first operational amplifier circuit comprises a processor U5, a processor U6, a processor U8 and a processor U9, a first pin of the processor U5 is electrically connected with a 4 th pin of the processor U5, a 2 nd pin of the processor U5 is grounded, a 3 rd pin of the processor U5 is electrically connected with a capacitor C18, the capacitor C17 is electrically connected with a differential single-ended circuit and a resistor R15 through a capacitor C639, the resistor R15 is electrically connected with a 3 rd pin through a resistor R16, the resistor R15 is also electrically connected with a1 st pin of the processor U8 through a capacitor C25, the capacitor C18 is also electrically connected with a1 st pin of the processor U12 through a resistor R12, the 1 st pin of the processor U12 is also electrically connected with a 4 th pin thereof, the 2 nd pin of the processor U12 is grounded, the 3 rd pin of the processor U12 is electrically connected with the first pin of the processor U12 through the resistor R12, the first pin of the processor U12 is electrically connected with the first pin of the processor U12, the 2 nd pin of the processor U6 is grounded, the 3 rd pin of the processor U6 is electrically connected with a capacitor C20, the capacitor C20 is electrically connected with the 4 th pin of the processor U5 and a resistor R17 through a capacitor C19, the resistor R17 is electrically connected with the 3 rd pin through a resistor R18, the resistor R17 is also electrically connected with the 1 st pin of the processor U9 through a capacitor C26, the capacitor C20 is also electrically connected with the 1 st pin of the processor U9 through a resistor R13, the 1 st pin of the processor U9 is also electrically connected with the 4 th pin thereof, the 2 nd pin of the processor U9 is grounded, the 3 rd pin of the processor U9 is electrically connected with the 4 th pin of the processor U6 through a resistor VR2, and the 1 st pin of the processor U6 is also electrically connected with a third operational amplifier circuit.
7. The distributed non-contact fault collection system of claim 1, wherein: the third operational amplifier circuit includes that the fortune is put chip U10 and electric capacity C10, the 3 rd stitch electricity of chip U10 is put to first difference commentaries on classics single-ended circuit and fortune, the 5 th stitch that chip U10 was put to fortune is connected the back ground connection with electric capacity C10 electricity, the 4 th stitch and the 1 st stitch electricity of chip U10 are put to fortune are connected, the 1 st needle output third output signal of chip U10 is put to fortune.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220520279.6U CN217360133U (en) | 2022-03-11 | 2022-03-11 | Distributed non-contact fault acquisition system |
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| CN202220520279.6U CN217360133U (en) | 2022-03-11 | 2022-03-11 | Distributed non-contact fault acquisition system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115639408A (en) * | 2022-12-23 | 2023-01-24 | 中大智能科技股份有限公司 | High-precision soil conductivity self-adaptive monitoring system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115639408A (en) * | 2022-12-23 | 2023-01-24 | 中大智能科技股份有限公司 | High-precision soil conductivity self-adaptive monitoring system |
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