CN217335117U - Power supply wake-up circuit, power supply circuit and passive protection device - Google Patents
Power supply wake-up circuit, power supply circuit and passive protection device Download PDFInfo
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- CN217335117U CN217335117U CN202123446079.5U CN202123446079U CN217335117U CN 217335117 U CN217335117 U CN 217335117U CN 202123446079 U CN202123446079 U CN 202123446079U CN 217335117 U CN217335117 U CN 217335117U
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Abstract
The utility model provides a power supply wake-up circuit, a power supply circuit and a passive protection device, wherein the power supply wake-up circuit comprises a key trigger circuit, a power supply enabling circuit and a wake-up self-locking circuit, and the input end of the power supply enabling circuit and the input end of the wake-up self-locking circuit are both connected with the output end of the key trigger circuit; the awakening self-locking circuit comprises a battery terminal, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a first diode and a system voltage output terminal, wherein the battery terminal is electrically connected with a source electrode of the first PMOS tube, a drain electrode of the first PMOS tube is electrically connected with the system voltage output terminal, the source electrode of the first PMOS tube and the drain electrode of the first NMOS tube are both electrically connected with a grid electrode of the first PMOS tube, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is electrically connected with an output end of the key trigger circuit; the anode of the first diode is electrically connected with the system voltage output terminal, and the cathode of the first diode is electrically connected with the grid electrode of the first NMOS tube. The utility model discloses a power wake-up circuit can reduce the reliance to MCU, and interference killing feature is strong, the dependable performance.
Description
Technical Field
The utility model relates to a circuit protection field is concrete, relates to a power wake-up circuit, still relates to an applied this power wake-up circuit's power supply circuit, still relates to an applied this power supply circuit's passive protection device.
Background
Passive protection devices are generally arranged in power-free equipment such as an existing switching station, a power distribution station and a ring main unit, and provide interphase overcurrent protection, zero-sequence overcurrent protection or non-electric quantity protection for a feeder line and a transformer in a power distribution network.
However, in the conventional passive protection device, when the circuit needs to be woken up, the circuit needs to be woken up and maintain a wakening state by the MCU control device after being triggered by the key and waiting for normal operation of the MCU, which is highly dependent on reliability and stability of the MCU, and the wakening mode is single, so that when the MCU is halted due to interference, the system power supply is easily turned off by mistake, which is difficult to maintain the wakening state, and the reliability is low. Therefore, better optimized solutions need to be considered.
Disclosure of Invention
The utility model discloses a first purpose provides a reduce to MCU's reliance, the power wake-up circuit that the interference killing feature is strong, the dependable performance.
The second purpose of the utility model is to provide a reduce to MCU's dependence, the power supply circuit that the interference killing feature is strong, the dependable performance.
The third purpose of the utility model is to provide a reduce to MCU's dependence, passive protection device that the interference killing feature is strong, the dependable performance.
In order to achieve the first object, the utility model provides a power supply wake-up circuit, which comprises a key trigger circuit, a power supply enable circuit and a wake-up self-locking circuit, wherein the input end of the power supply enable circuit and the input end of the wake-up self-locking circuit are both connected with the output end of the key trigger circuit; the awakening self-locking circuit comprises a battery terminal, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a first diode and a system voltage output terminal, wherein the battery terminal is electrically connected with a source electrode of the first PMOS tube, a drain electrode of the first PMOS tube is electrically connected with the system voltage output terminal, the source electrode of the first PMOS tube and the drain electrode of the first NMOS tube are both electrically connected with a grid electrode of the first PMOS tube, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is electrically connected with an output end of the key trigger circuit; the anode of the first diode is electrically connected with the system voltage output terminal, and the cathode of the first diode is electrically connected with the grid electrode of the first NMOS tube.
According to the above technical scheme, the utility model discloses a power awakening circuit awakens up self-locking circuit through the setting, can trigger when button trigger circuit trigger power supply enable circuit work and awaken up self-locking circuit and supply power auto-lock, maintains system voltage output terminal and provides voltage to system circuit to reduce the reliance to MCU, not disturbed by MCU's crash, the interference killing feature is strong, the dependable performance.
In a further scheme, the awakening self-locking circuit further comprises a power-off control terminal, and the power-off control terminal is electrically connected with the grid electrode of the first NMOS tube.
Therefore, the power-off control terminal is arranged, and the self-locking circuit can be conveniently controlled to be awakened to be powered off.
In a further scheme, the key trigger circuit comprises a key input terminal, a first capacitor and a second NMOS tube, a drain electrode and a grid electrode of the second NMOS tube are electrically connected with the key input terminal, a source electrode of the second NMOS tube is grounded, the first capacitor is connected in parallel with the source electrode and the grid electrode of the second NMOS tube, and an input end of the power supply enabling circuit and an input end of the awakening self-locking circuit are electrically connected with the drain electrode of the second NMOS tube.
Therefore, the key trigger circuit can be cut off when a high level is input by the key input terminal by arranging the second NMOS tube, so that the high level is transmitted to the power supply enabling circuit and the awakening self-locking circuit, and the capacitor is charged at the same time. When the key input terminal is changed into a low level, the capacitor discharges to delay the cut-off of the second NMOS tube, so that the time of outputting the high level is prolonged, and the sensitivity of key triggering is improved.
In a further scheme, the key trigger circuit further comprises a second diode, the anode of the second diode is electrically connected with the drain electrode of the second NMOS tube, and the cathode of the second diode is electrically connected with the input end of the awakening self-locking circuit.
Therefore, the second diode is arranged at the drain electrode of the second NMOS tube and the input end of the awakening self-locking circuit, and the situation that the grid voltage of the first NMOS tube is insufficient and self-locking cannot be achieved due to current backflow can be prevented.
In a further scheme, the power supply enabling circuit comprises a power supply enabling terminal and a third diode, wherein the anode of the third diode is electrically connected with the drain of the second NMOS tube, and the cathode of the third diode is electrically connected with the power supply enabling terminal.
Therefore, the third diode is arranged between the power supply enabling terminal and the drain electrode of the second NMOS tube, and current backflow can be prevented.
In a further scheme, the power supply wake-up circuit further comprises a CPU control trigger circuit, the CPU control trigger circuit is provided with a CPU connecting end and a fourth diode, the anode of the fourth diode is electrically connected with the CPU connecting end, and the cathode of the fourth diode is electrically connected with the power supply enabling terminal.
Therefore, the CPU control trigger circuit is arranged, and the CPU can send high level to the power supply enable terminal, so as to trigger the power supply enable.
In order to achieve the second object, the present invention provides a power circuit, which includes a battery circuit, a key circuit and a power wake-up circuit, wherein the power wake-up circuit adopts the above power wake-up circuit; the key circuit is electrically connected with the input end of the key trigger circuit, and the output end of the power supply enabling circuit is electrically connected with the battery circuit.
In order to realize the third objective, the utility model provides a passive protection device is provided with power supply circuit, and power supply circuit adopts above-mentioned power supply circuit.
Drawings
Fig. 1 is a schematic block circuit diagram of an embodiment of the passive protection device of the present invention.
Fig. 2 is a schematic circuit diagram of a power circuit in an embodiment of the passive protection device of the present invention.
Fig. 3 is a schematic circuit diagram of a power wake-up circuit in an embodiment of the passive protection device of the present invention.
Fig. 4 is a schematic circuit diagram of a relay control circuit in an embodiment of the passive protection device of the present invention.
The present invention will be further explained with reference to the drawings and examples.
Detailed Description
As shown in fig. 1, in the present embodiment, the passive protection device includes a power supply circuit 1, a main control circuit 2, a relay control circuit 3, and a trip coil 4. The power supply circuit 1 supplies power to the main control circuit 2, the relay control circuit 3, and the trip coil 4. Relay control circuit 3 is connected with main control circuit 2 electricity, and trip coil 4 is connected with relay control circuit 3 electricity, and when passive protection device detected that the protected circuit appears unusually, main control circuit 2 controlled trip coil 4 through relay control circuit 3 and switched on to the route of disconnection protected circuit is protected.
In this embodiment, referring to fig. 2, the power supply circuit 1 includes a key circuit 11, a power wake-up circuit 12, a power supply circuit 13, a power management circuit 14, and a battery circuit 15, where the key circuit 11 is used for power switch control, the power wake-up circuit 12 is used for wake-up control of a power supply, the power supply circuit 13 is used for obtaining an external power supply to supply power, the power management circuit 14 is used for management control of a power supply, and the battery circuit 15 is used for electric energy storage and release. The key circuit 11, the power supply circuit 13, the power management circuit 14 and the battery circuit 15 all adopt well-known circuit modules, and are not described herein again.
In this embodiment, referring to fig. 3, the power wake-up circuit 12 includes a key trigger circuit 121, a power enable circuit 122, a CPU control trigger circuit 123, and a wake-up self-locking circuit 124. The input end of the power supply enabling circuit 122 and the input end of the wake-up self-locking circuit 124 are both connected with the output end of the key triggering circuit 121. The output of the power supply enable circuit 122 is electrically connected to the battery circuit 15.
The KEY trigger circuit 121 comprises a KEY input terminal KEY-UP, a capacitor C1, a diode D1 and an NMOS transistor Q1, a drain and a gate of the NMOS transistor Q1 are electrically connected with the KEY input terminal KEY-UP, a source of the NMOS transistor Q1 is grounded, the capacitor C1 is connected in parallel with a source and a gate of the NMOS transistor Q1, an input end of the power enable circuit 122 and an input end of the wake-UP self-locking circuit 124 are electrically connected with a drain of the NMOS transistor Q1, an anode of the diode D1 is electrically connected with a drain of the NMOS transistor Q1, and a cathode of the diode D1 is electrically connected with an input end of the wake-UP self-locking circuit 124. The KEY triggering circuit 121 is electrically connected to the KEY circuit 11 through the KEY input terminal KEY-UP.
The power enable circuit 122 includes a power enable terminal 1221 and a diode D2, an anode of the diode D2 is electrically connected to a drain of the NMOS transistor Q1, and a cathode of the diode D2 is electrically connected to the power enable terminal 1221.
The CPU control trigger circuit 123 is provided with a CPU connection terminal CPU-UP and a diode D3, the anode of the diode D3 is electrically connected with the CPU connection terminal CPU-UP, the cathode of the diode D3 is electrically connected with the power enable terminal 1221123, and the CPU connection terminal CPU-UP is electrically connected with the main control circuit 2.
The awakening self-locking circuit 124 comprises a battery terminal BAT, a PMOS tube Q2, an NMOS tube Q3, a diode D4 and a system voltage output terminal 1241, the battery circuit 15 is electrically connected with the battery terminal BAT, the battery terminal BAT is electrically connected with the source electrode of the PMOS tube Q2, the drain electrode of the PMOS tube Q2 is electrically connected with the system voltage output terminal 1241, the source electrode of the PMOS tube Q2 and the drain electrode of the NMOS tube Q3 are both electrically connected with the gate electrode of the PMOS tube Q2, the source electrode of the NMOS tube Q3 is grounded, the gate electrode of the NMOS tube Q3 is electrically connected with the output end of the key trigger circuit 121, the anode electrode of the diode D4 is electrically connected with the system voltage output terminal 1241, and the cathode electrode of the diode D4 is electrically connected with the gate electrode of the NMOS tube Q3.
The wake-up self-locking circuit 124 further comprises a power-OFF control terminal CPU-OFF electrically connected with the gate of the NMOS transistor Q3, and the power-OFF control terminal CPU-OFF electrically connected with the main control circuit 2.
In this embodiment, when the power wake-up circuit 12 is in operation, the key circuit 11 sends a high level to the key trigger circuit 121, and at this time, the power enable terminal 1221 receives the high level, so as to control the battery circuit 15 to be powered on. Meanwhile, the gate of the NMOS transistor Q3 obtains a high level, and the NMOS transistor Q3 is turned off, so that the gate of the PMOS transistor Q2 is at a high level, and the PMOS transistor Q2 is turned on, so that the battery circuit 15 supplies power to the system voltage output terminal 1241. When the system voltage output terminal 1241 is at a high level, the gate of the NMOS transistor Q3 is also at a high level due to the presence of the diode D4, so as to achieve the self-locking effect, and make the PMOS transistor Q2 be in a continuous conducting state. When the power supply of the system voltage output terminal 1241 needs to be turned OFF, a low level is sent to the power-OFF control terminal CPU-OFF through the main control circuit 2, so that the gate of the NMOS transistor Q3 is in a low level state, the NMOS transistor Q3 is turned on, the PMOS transistor Q2 is turned OFF, and the power supply of the system voltage output terminal 1241 is stopped. In addition, a high level can be sent to the CPU connection end CPU-UP through the main control circuit 2, so that the battery circuit 15 is controlled to be powered on.
In the present embodiment, referring to fig. 4, the relay control circuit 3 includes a double-pole double-throw relay switch K1, a control terminal 31, a power supply terminal CO +, a first output terminal TQ + and a second output terminal TQ-, a first electromagnetic end of the double-pole double-throw relay switch K1 is electrically connected to the control terminal 31, the power supply terminal CO + is electrically connected to a common end of a first switch in the double-pole double-throw relay switch K1, the first output terminal TQ + is electrically connected to a normally open terminal of the first switch, the second output terminal TQ-is electrically connected to a normally open terminal of a second switch in the double-pole double-throw relay switch K1, a common end of the second switch is grounded, a capacitor C2 is connected in parallel between the normally open terminal of the first switch and the common end of the first switch, a capacitor C3 is connected in parallel between the normally open terminal of the second switch and the common end of the second switch, and capacitance values of the capacitors C2 and C3 are equal. The control terminal 31 is electrically connected to the main control circuit 2, the power supply terminal CO + is electrically connected to the power supply circuit 1, the first output terminal TQ + is electrically connected to the anode of the trip coil 4, and the second output terminal TQ-is electrically connected to the cathode of the trip coil 4. An NPN triode Q4 is arranged between the first electromagnetic end of the double-pole double-throw relay switch K1 and the control terminal 31, the base electrode of the NPN triode Q4 is electrically connected with the control terminal 31, the emitting electrode of the NPN triode Q4 is grounded, and the collecting electrode of the NPN triode Q4 is electrically connected with the first electromagnetic end. A diode D6 is connected in parallel between the first electromagnetic end and the second electromagnetic end, the anode of the diode D6 is electrically connected with the first electromagnetic end, and the cathode of the diode D6 is electrically connected with the second electromagnetic end.
In this embodiment, the relay control circuit 3 further includes an anti-surge circuit 32, and the anti-surge circuit 32 is connected in parallel to a branch between the power supply terminal CO + and the common terminal of the first switch. The surge protection circuit 32 comprises a first voltage dependent resistor RV1 and a second voltage dependent resistor RV2, wherein the first end of the first voltage dependent resistor RV1 is electrically connected with a branch between a power supply terminal CO + and the common end of the first switch, the second end of the first voltage dependent resistor RV1 is electrically connected with the first end of the second voltage dependent resistor RV2, and the second end of the second voltage dependent resistor RV2 is connected with the ground wire. Anti-surge circuit 32 further includes a diode D5, a cathode of diode D5 is electrically connected to a branch between supply terminal CO + and the common terminal of the first switch, an anode of diode D5 is grounded, and an anode of diode D5 is further electrically connected to the first terminal of second varistor RV 2.
The relay control circuit 3 further comprises a filter inductor L1 and an energy storage capacitor E1, an anode of the energy storage capacitor E1 is electrically connected with the power supply terminal CO +, a cathode of the energy storage capacitor E1 is grounded, a first end of the filter inductor L1 is electrically connected with a cathode of the energy storage capacitor E1, and a second end of the filter inductor L1 is electrically connected with a first end of a second piezoresistor RV 2. When the circuit is normal, the energy storage capacitor E1 stores energy, and when the power supply terminal CO + is powered off, the energy storage capacitor E1 discharges energy, so as to supply power to the trip coil 4, thereby playing a passive protection role.
A diode D7 and a capacitor C4 are further arranged between the power supply terminal CO + and the common end of the first switch, the anode of the diode D7 is electrically connected with the power supply terminal CO +, the cathode of the diode D7 is electrically connected with the common end of the first switch, the first end of the capacitor C4 is electrically connected with the anode of the diode D7, and the second end of the capacitor C4 is electrically connected with the cathode of the diode D7. A diode D7 is connected in series between the power supply terminal CO + and the common end of the first switch, so that the power circuit 1 can be prevented from being damaged by current backflow, and meanwhile, the diode D7 is connected with a capacitor C4 in parallel, so that the filtering effect can be further achieved.
In this embodiment, relay control circuit 3 has electric capacity C2 through parallelly connected between the public end at the normally open terminal of first switch and first switch, it has electric capacity C3 to parallelly connected between the normally open terminal of second switch and the public end of second switch, electric capacity C2 makes equipotential between the normally open terminal of first switch and the public end of first switch, electric capacity C3 makes equipotential between the normally open terminal of second switch and the public end of second switch, thereby avoid making when surge voltage appears in the circuit, the phenomenon of puncturing appears, improve anti surge impact ability.
The passive protection device of this embodiment during operation, if master control circuit 2 detects that protected circuit breaks down and needs to break off the route and protect, master control circuit 2 sends the high level to control terminal 31 to make the normally open terminal of first switch and the public end intercommunication of first switch, the normally open terminal of second switch and the public end intercommunication of second switch, thereby switch on trip coil 4, and then the route of disconnection protected circuit is protected.
It should be noted that the above is only a preferred embodiment of the present invention, but the design concept of the present invention is not limited thereto, and all insubstantial modifications made by using the design concept of the present invention also fall within the protection scope of the present invention.
Claims (8)
1. A power supply wake-up circuit is characterized by comprising a key trigger circuit, a power supply enabling circuit and a wake-up self-locking circuit, wherein the input end of the power supply enabling circuit and the input end of the wake-up self-locking circuit are connected with the output end of the key trigger circuit;
the awakening self-locking circuit comprises a battery terminal, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a first diode and a system voltage output terminal, wherein the battery terminal is electrically connected with a source electrode of the first PMOS tube, a drain electrode of the first PMOS tube is electrically connected with the system voltage output terminal, the source electrode of the first PMOS tube and the drain electrode of the first NMOS tube are both electrically connected with a grid electrode of the first PMOS tube, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is electrically connected with an output end of the key trigger circuit;
the anode of the first diode is electrically connected with the system voltage output terminal, and the cathode of the first diode is electrically connected with the grid electrode of the first NMOS tube.
2. Power wake-up circuit according to claim 1,
the awakening self-locking circuit further comprises a power-off control terminal, and the power-off control terminal is electrically connected with the grid electrode of the first NMOS tube.
3. Power wake-up circuit according to claim 1 or 2,
the key trigger circuit comprises a key input terminal, a first capacitor and a second NMOS tube, wherein the drain electrode and the grid electrode of the second NMOS tube are electrically connected with the key input terminal, the source electrode of the second NMOS tube is grounded, the first capacitor is connected in parallel with the source electrode and the grid electrode of the second NMOS tube, and the input end of the power supply enabling circuit and the input end of the awakening self-locking circuit are electrically connected with the drain electrode of the second NMOS tube.
4. Power wake-up circuit according to claim 3,
the key trigger circuit further comprises a second diode, the anode of the second diode is electrically connected with the drain electrode of the second NMOS tube, and the cathode of the second diode is electrically connected with the input end of the awakening self-locking circuit.
5. Power wake-up circuit according to claim 3,
the power supply enabling circuit comprises a power supply enabling terminal and a third diode, wherein the anode of the third diode is electrically connected with the drain electrode of the second NMOS tube, and the cathode of the third diode is electrically connected with the power supply enabling terminal.
6. Power wake-up circuit according to claim 5,
the power supply wake-up circuit further comprises a CPU control trigger circuit, the CPU control trigger circuit is provided with a CPU connecting end and a fourth diode, the anode of the fourth diode is electrically connected with the CPU connecting end, and the cathode of the fourth diode is electrically connected with a power supply enabling terminal.
7. A power circuit comprises a battery circuit, a key circuit and a power wake-up circuit, and is characterized in that,
the power supply wake-up circuit adopts the power supply wake-up circuit of any one of claims 1 to 6;
the key circuit is electrically connected with the input end of the key trigger circuit, and the output end of the power supply enabling circuit is electrically connected with the battery circuit.
8. A passive protection device is provided with a power supply circuit, which is characterized in that,
the power supply circuit applies the power supply circuit of claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123446079.5U CN217335117U (en) | 2021-12-31 | 2021-12-31 | Power supply wake-up circuit, power supply circuit and passive protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123446079.5U CN217335117U (en) | 2021-12-31 | 2021-12-31 | Power supply wake-up circuit, power supply circuit and passive protection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217335117U true CN217335117U (en) | 2022-08-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123446079.5U Active CN217335117U (en) | 2021-12-31 | 2021-12-31 | Power supply wake-up circuit, power supply circuit and passive protection device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217335117U (en) |
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2021
- 2021-12-31 CN CN202123446079.5U patent/CN217335117U/en active Active
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