CN217332571U - Analog quantity signal conditioning circuit - Google Patents
Analog quantity signal conditioning circuit Download PDFInfo
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- CN217332571U CN217332571U CN202220025571.0U CN202220025571U CN217332571U CN 217332571 U CN217332571 U CN 217332571U CN 202220025571 U CN202220025571 U CN 202220025571U CN 217332571 U CN217332571 U CN 217332571U
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Abstract
The utility model provides an analog signal conditioning circuit in the technical field of power electronics, which comprises a resistor R1, a resistor R2, a resistor R3, a power VCC, an ADC chip and a DSP chip; one end of the resistor R2 is connected with a power supply VCC, and the other end of the resistor R2 is connected with one end of the resistor R1, one end of the resistor R3 and the input end of the ADC chip; the other end of the resistor R3 is grounded; and the output end of the ADC chip is connected with the DSP chip. The utility model has the advantages that: the circuit structure is greatly simplified, and the cost is greatly reduced.
Description
Technical Field
The utility model relates to a power electronic technology field indicates an analog signal conditioning circuit very much.
Background
With the rapid development of new energy industry, the power electronic technology is widely developed and applied. In the technical field of power electronics, analog quantity signals such as voltage and current are required to be collected and sent to a DSP chip for control, and the voltage input range of common ADC chips and DSP chips in the market is generally 0-3.3V.
The output voltage range of the acquired signal of the analog quantity signal mainly has two conditions, one is that the output voltage range of the unipolar voltage signal converted after isolation or amplification is 0-3V or 0-6V, and the signal only needs to be divided by a simple resistor or directly transmitted to an ADC chip for sampling; and the other is that the voltage or current signal of the power grid is converted into a voltage output signal after being isolated or amplified, the output voltage range of the voltage output signal is between +/-3V and +/-6V, at the moment, the negative analog quantity signal needs to be lifted, and the positive analog quantity signal needs to be reduced to finally reach 0-3.3V.
For the lifting of the analog quantity signal, the conventional conditioning circuit adopts an operational amplifier for lifting, as shown in fig. 2. According to the virtual break of the operational amplifier, it is known that no current flows through the non-inverting input terminal of the operational amplifier, the current flowing through the resistor R1 'and the resistor R2' are equal, and the current flowing through the resistor R3 'and the resistor R4' are also equal, and the following is derived:
the virtual short of the operational amplifier indicates that: vp is Vn;
further derivation yields:
let R1 ═ R3', R2 ═ R4';
then the above equation reduces to:
from the above equation, the output voltage Vout is in a linear relationship with the input voltage Vin, and the input voltage Vin is amplified or reduced by the resistor R1', the resistor R2', the resistor R3', and the resistor R4', and then the bias voltage V is applied thereto REF The result of (d) is the output voltage Vout.
However, the conventional conditioning circuit has a complicated structure and requires an additional amountThe external reference voltage is used as the bias voltage V REF And the operational amplifier is not low in cost, so that the cost of the whole conditioning circuit is high. Therefore, how to provide an analog signal conditioning circuit to simplify the circuit structure and reduce the cost is a technical problem to be solved urgently.
Disclosure of Invention
The to-be-solved technical problem of the utility model lies in providing an analog quantity signal conditioning circuit, realizes simplifying circuit structure, reduce cost.
The utility model discloses a realize like this: an analog signal conditioning circuit comprises a resistor R1, a resistor R2, a resistor R3, a power supply VCC, an ADC chip and a DSP chip;
one end of the resistor R2 is connected with a power supply VCC, and the other end of the resistor R2 is connected with one end of the resistor R1, one end of the resistor R3 and the input end of the ADC chip; the other end of the resistor R3 is grounded; and the output end of the ADC chip is connected with the DSP chip.
The utility model has the advantages that:
be used for the regulation (voltage lifting) of analog quantity signal through setting up resistance R1, resistance R2 and resistance R3, owing to be passive device and simple structure, need not to external reference voltage again in the tradition, need not the fortune that use cost is high and put, final very big simplification circuit structure, very big cost is reduced, and very big promotion the reliability of circuit.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a circuit diagram of the analog signal conditioning circuit of the present invention.
Fig. 2 is a circuit diagram of a conventional conditioning circuit.
Fig. 3 is a schematic diagram of the waveform of the analog signal lifting of the present invention.
Detailed Description
The embodiment of the utility model provides an analog quantity signal conditioning circuit has solved that prior art well conditioning circuit structure is complicated, need increase extra reference voltage as bias voltage, and the cost of fortune is put is not low, leads to the higher technical problem of cost of whole conditioning circuit, has realized very big simplification circuit structure, and then very big reduction the technical effect of cost.
The embodiment of the utility model provides an in technical scheme for solving above-mentioned problem, the general thinking is as follows: the resistor R1, the resistor R2 and the resistor R3 which are passive devices are arranged for conditioning analog quantity signals, so that the circuit structure is simplified, and the cost is reduced.
For better understanding of the above technical solutions, the following detailed descriptions will be provided in conjunction with the drawings and the detailed description of the embodiments.
Referring to fig. 1 to fig. 3, a preferred embodiment of an analog signal conditioning circuit of the present invention includes a resistor R1, a resistor R2, a resistor R3, a power VCC, an ADC chip, and a DSP chip; the resistor R1 is used as an input resistor; the resistor R2 is used as a pull-up resistor; the resistor R3 is used as a pull-down resistor; the ADC chip is used for converting the acquired analog signals into digital signals, and in the specific implementation, the ADC chip capable of realizing the function is selected from the prior art, and is not limited to any type, so that the ADC chip can be obtained by a person skilled in the art without creative work; the DSP chip is used for processing the digital signal input by the ADC chip, and in specific implementation, the DSP chip capable of implementing the function is selected from the prior art, and is not limited to any model, which is available to those skilled in the art without creative work.
One end of the resistor R2 is connected with a power supply VCC, and the other end of the resistor R2 is connected with one end of the resistor R1, one end of the resistor R3 and the input end of the ADC chip; the other end of the resistor R3 is grounded; and the output end of the ADC chip is connected with the DSP chip.
The utility model discloses the theory of operation:
the sampling signal is input into the ADC chip through the resistor R1, and the ADC chip converts the received sampling signal from an analog signal into a digital signal and inputs the digital signal into the DSP chip for further calculation processing.
The analog quantity signal conditioning principle is as follows:
according to kirchhoff's current law, assuming that the current entering a node is positive and the current leaving the node is negative, the algebraic sum of all the currents related to this node is equal to zero, so:
i 1 +i 2 +i 3 +i 4 ＝0；
since the output terminal is a high impedance circuit, i can be obtained 4 0, and then obtaining:
Vout＝k*Vin+b；
constant number
Constant number
As can be seen from the formula Vout ═ k × Vin + b, the output signal Vout and the input signal Vin are in a linear relationship, and the input sampling signal can be narrowed down to an appropriate range.
To sum up, the utility model has the advantages that:
be used for the regulation (voltage lifting) of analog quantity signal through setting up resistance R1, resistance R2 and resistance R3, owing to be passive device and simple structure, need not to connect reference voltage again to the tradition, need not the fortune that use cost is high to put, final very big simplification circuit structure, very big reduction the cost, and very big promotion the reliability of circuit.
Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.
Claims (1)
1. An analog signal conditioning circuit, comprising: comprises a resistor R1, a resistor R2, a resistor R3, a power VCC, an ADC chip and a DSP chip;
one end of the resistor R2 is connected with a power supply VCC, and the other end of the resistor R2 is connected with one end of the resistor R1, one end of the resistor R3 and the input end of the ADC chip; the other end of the resistor R3 is grounded; and the output end of the ADC chip is connected with the DSP chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220025571.0U CN217332571U (en) | 2022-01-06 | 2022-01-06 | Analog quantity signal conditioning circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220025571.0U CN217332571U (en) | 2022-01-06 | 2022-01-06 | Analog quantity signal conditioning circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217332571U true CN217332571U (en) | 2022-08-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220025571.0U Active CN217332571U (en) | 2022-01-06 | 2022-01-06 | Analog quantity signal conditioning circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN217332571U (en) |
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2022
- 2022-01-06 CN CN202220025571.0U patent/CN217332571U/en active Active
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