CN217282937U

CN217282937U - Drive circuit of two-bus system

Info

Publication number: CN217282937U
Application number: CN202220867921.8U
Authority: CN
Inventors: 于鹏飞
Original assignee: Zhejiang Huaxiao Technology Co ltd
Current assignee: Zhejiang Huaxiao Technology Co ltd
Priority date: 2022-04-15
Filing date: 2022-04-15
Publication date: 2022-08-23
Anticipated expiration: 2032-04-15

Abstract

The present application relates to a drive circuit of a two-bus system, including: the method comprises the following steps: the device comprises a code sending circuit, a stream discharging circuit and a code receiving circuit; the output end of the code sending circuit is used for outputting a high level or a low level; the leakage circuit is respectively connected with the output end of the code sending circuit and the signal bus, and is used for discharging the electric quantity on the signal bus when the output end of the code sending circuit outputs a high level; the bleeder circuit comprises: first triode, second triode, first resistance, second resistance, third resistance, fourth resistance, fifth resistance, sixth resistance, first MOS pipe, first diode and second diode, through this application, solved the problem that the drive circuit fault-tolerance of two bus systems is low among the correlation technique, realized improving the technological effect of the fault-tolerance of the drive circuit of two bus systems.

Description

Drive circuit of two-bus system

Technical Field

The present disclosure relates to the field of bus technologies, and in particular, to a driving circuit for a two-bus system.

Background

In the field of fire alarm, the two-bus technology uses a bus for sharing signals and power supply, the downlink data of the host equipment can adopt voltage signals, and the uplink data of the slave equipment can adopt a current signal mode. The construction and cable cost is saved, and great convenience is brought to site construction and later maintenance.

At present, a driving circuit of a two-bus communication system in the related art is often controlled by control software of host equipment, and when the control software of the host equipment fails, a loop inevitably has an abnormal leakage condition, which results in low fault tolerance and poor abnormal resistance of the driving circuit of the two-bus system.

At present, no effective solution is provided for the problem of low fault tolerance of the driving circuit of the two-bus system in the related art.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a driving circuit of a two-bus system, so as to at least solve the problem of low fault tolerance of the driving circuit of the two-bus system in the related art.

In a first aspect, an embodiment of the present application provides a driving circuit for a two-bus system, including: the device comprises a code sending circuit, a stream leakage circuit and a code receiving circuit; the output end of the code sending circuit is used for outputting a high level or a low level; the leakage circuit is respectively connected with the output end of the code sending circuit and the signal bus, and is used for discharging the electric quantity on the signal bus when the output end of the code sending circuit outputs a high level; the bleeder circuit comprises: the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first MOS (metal oxide semiconductor) tube, a first diode and a second diode; the base electrode of the first triode is connected with the second end of the first resistor, the collector electrode of the first triode is connected with the base electrode of the second triode, the emitter electrode of the first triode is connected with the input end of the code receiving circuit, the emitter electrode of the second triode is connected with the drain electrode of the first MOS tube, and the collector electrode of the second triode is connected with the first end of the second resistor; the first end of the first resistor is connected with the output end of the code sending circuit, the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with a ground terminal, the first end of the fourth resistor is respectively connected with the first end of the second resistor and the first end of the sixth resistor, the second end of the fourth resistor is connected with the first end of the fifth resistor, the second end of the fifth resistor is connected with the ground terminal, and the second end of the sixth resistor is connected with the gate of the first MOS transistor; the source electrode of the first MOS tube is connected with the grounding end, and the drain electrode of the first MOS tube is connected with the signal bus; the negative electrode of the first diode is connected with the second end of the sixth resistor and the grid electrode of the first MOS tube, the positive electrode of the first diode is connected with the grounding end, the negative electrode of the second diode is connected with the drain electrode of the first MOS tube, and the positive electrode of the second diode is connected with the source electrode of the first MOS tube.

In some of these embodiments, the code sending circuit includes a code sending control circuit and a code sending current limiting circuit; the output end of the code sending control circuit is used for outputting a high level or a low level; the code sending current limiting circuit is respectively connected with the code sending control circuit and the signal bus, and is used for limiting the magnitude of current flowing between the code sending control circuit and the signal bus when the rear end load of the signal bus is overloaded.

In some embodiments, the code control circuit comprises: the first resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor and the third diode are connected in series; the first power supply is respectively connected with a first end of the seventh resistor, a first end of the eighth resistor, an emitter of the third triode and a cathode of the third diode; a collector of the third triode is connected with a first end of the ninth resistor, and a base of the third triode is respectively connected with a second end of the tenth resistor and a second end of the eighth resistor; a base electrode of the fourth triode is respectively connected with a collector electrode of the fifth triode and a second end of the seventh resistor, a collector electrode of the fourth triode is connected with a first end of the tenth resistor, and an emitting electrode of the fourth triode is connected with a first end of the eleventh resistor; a base electrode of the fifth triode is connected with a second end of the thirteenth resistor, and an emitting electrode of the fifth triode is connected with a grounding end; the second end of the eleventh resistor is connected with the ground terminal, the anode of the third diode is respectively connected with the second end of the ninth resistor and the first end of the twelfth resistor, the second end of the twelfth resistor is connected with the ground terminal, and the anode and the cathode of the third diode are both connected with the code-sending current-limiting circuit.

In some embodiments, the code-sending current-limiting circuit comprises: the first transistor, the second MOS transistor, the fourth diode, the fourteenth resistor, the fifteenth resistor, the first capacitor and the second capacitor are connected in series; an emitter of the sixth triode is connected with a cathode of the third diode and the first end of the fifteenth resistor respectively, a collector of the sixth triode is connected with an anode of the third diode and the gate of the second MOS transistor respectively, and a base of the sixth triode is connected with the first end of the fourteenth resistor; a source electrode of the second MOS transistor is connected to a second end of the fourteenth resistor and a second end of the fifteenth resistor, respectively, and a drain electrode of the second MOS transistor is connected to an emitter electrode of a second triode; the cathode of the fourth diode is connected with the source electrode of the second MOS tube, and the anode of the fourth diode is connected with the drain electrode of the second MOS tube; the first end of the first capacitor is connected with the first end of the fifteenth resistor and the first end of the second capacitor respectively, and the second end of the first capacitor and the second end of the second capacitor are both connected with a ground terminal.

In some embodiments, the code receiving circuit comprises a code receiving voltage modulation circuit and a code receiving current demodulation circuit; wherein, receive the code voltage modulation circuit and include: the first operational amplifier, the seventh triode, the eighth triode, the third capacitor, the fifth diode, the sixteenth resistor, the seventeenth resistor, the eighteenth resistor, the nineteenth resistor, the twentieth resistor, the twenty-first resistor and the twenty-second resistor; the inverting input end of the first operational amplifier is connected to the first end of the twenty-first resistor, the first end of the first operational amplifier is connected to the ground end, the second end of the first operational amplifier is connected to a first power supply, and the output end of the first operational amplifier is connected to the first end of the third capacitor and the first end of the nineteenth resistor respectively; an emitting electrode of the seventh triode is connected with a second end of the sixteenth resistor, a base electrode of the seventh triode is respectively connected with a second end of the nineteenth resistor and a negative electrode of the fifth diode, and a collector electrode of the seventh triode is respectively connected with a first end of the seventeenth resistor and a positive electrode of the fifth diode; an emitter of the eighth triode is connected with the second end of the seventeenth resistor, the first end of the twentieth resistor and the first end of the eighteenth resistor respectively, a base of the eighth triode is connected with the anode of the fifth diode, and a collector of the eighth triode is connected with the second end of the nineteenth resistor; a second end of the third capacitor is respectively connected with a first end of the twenty-first resistor and a first end of the twenty-second resistor; the first end of the sixteenth resistor is connected with the first power supply, the second end of the eighteenth resistor is connected with the emitting electrode of the first triode, the signal bus and the code receiving current demodulation circuit, the second end of the twentieth resistor is connected with the second end of the twenty-second resistor and the code receiving current demodulation circuit respectively, and the second end of the twenty-first resistor is connected with the grounding end.

In some embodiments, the receive current demodulation circuit includes: the third MOS tube, the second power supply, the fourth capacitor, the second operational amplifier, the sixth diode, the twenty-third resistor, the twenty-fourth resistor, the twenty-fifth resistor, the twenty-sixth resistor and the twenty-seventh resistor; a source electrode of the third MOS transistor is connected to the ground terminal, a drain electrode of the third MOS transistor is connected to the second end of the twenty-third resistor, and a gate electrode of the third MOS transistor is connected to a negative electrode of the sixth diode and the first end of the twenty-seventh resistor, respectively; the second power supply is connected with a first end of the twenty-third resistor; a first end of the fourth capacitor is connected with the non-inverting input end of the second operational amplifier, and a second end of the fourth capacitor is connected with the inverting input end of the second operational amplifier; the output end of the second operational amplifier is connected with the second end of the twenty-seventh resistor; the anode of the sixth diode is connected with the grounding end; the first end of twenty-fourth resistance respectively with the second end of twentieth resistance with the non inverting input end of second operational amplifier is connected, the second end of twenty-fourth resistance is connected with the earthing terminal, the first end of twenty-fifth resistance respectively with the second end of twentieth resistance with the second end of eighteenth resistance is connected, the second end of twenty-fifth resistance respectively with the inverting input end of second operational amplifier with the first end of twenty-sixth resistance is connected, the second end of twenty-sixth resistance is connected with the earthing terminal.

In some of these embodiments, the driver circuit of the two-bus system further comprises a current monitoring circuit; the current monitoring circuit is connected between the signal bus and the bleeder circuit, and is used for detecting the current of the two lines of the signal bus and the leakage current of the signal bus.

In some of these embodiments, the current monitoring circuit comprises: the third operational amplifier, the fifth capacitor, the sixth capacitor, the seventh diode, the eighth diode, the ninth diode, the twenty-eighth resistor, the twenty-ninth resistor, the thirty-seventh resistor, the thirty-second resistor and the thirty-third resistor; the non-inverting input end of the third operational amplifier is connected with the second end of the thirty-first resistor and the second end of the twenty-ninth resistor respectively, and the inverting input end of the third operational amplifier is connected with the first end of the thirty-second resistor and the second end of the thirty-second resistor respectively; a first end of the fifth capacitor is connected with a first end of the twenty-eighth resistor and a drain electrode of the first MOS transistor respectively, and a second end of the fifth capacitor is connected with the signal bus and a second end of the twenty-eighth resistor respectively; a first end of the sixth capacitor is connected with a second end of the twenty-ninth resistor and a non-inverting input end of the third operational amplifier respectively, and a second end of the sixth capacitor is connected with a second end of the thirty-third resistor and an inverting input end of the third operational amplifier respectively; the anode of the seventh diode is connected with the first end of the twenty-eighth resistor and the cathode of the eighth diode respectively, and the cathode of the seventh diode is connected with the second end of the twenty-eighth resistor and the anode of the eighth diode respectively; a cathode of the eighth diode is connected with a first end of the twenty-ninth resistor, and an anode of the eighth diode is connected with a first section of the thirty-third resistor; a negative electrode of the ninth diode is connected with a first end of the thirty-third resistor, and a positive electrode of the ninth diode is connected with the grounding end; a first end of the thirty-first resistor is connected to the ground terminal, and a second end of the thirty-second resistor is connected to an output end of the third operational amplifier and a second end of the thirty-third resistor, respectively.

In some embodiments, the driving circuit of the two-bus system further comprises a protection circuit; the protection circuit is connected between the current monitoring circuit and the signal bus, and the protection circuit is used for performing surge protection and filtering processing on the signal bus.

In some of these embodiments, the protection circuit includes: the common-mode inductor, the seventh capacitor, the eighth capacitor, the ninth capacitor, the tenth capacitor, the eleventh capacitor, the twelfth diode, the eleventh diode, the twelfth diode, the thirteenth diode, the first inductor, the second inductor, the first thermistor, the second thermistor, the first piezoresistor, the second piezoresistor, the thirty-fourth resistor and the discharge tube; a first end of the common mode inductor is connected with a second end of the seventh capacitor, a first end of the current monitoring circuit and a first end of the ninth capacitor, a second end of the common mode inductor is connected with a second end of the ninth capacitor, a second end of the thirty-fourth resistor and a first end of the eleventh capacitor, a third end of the common mode inductor is connected with a second end of the eighth capacitor, a first end of the tenth capacitor and a first end of the first thermistor, and a fourth end of the common mode inductor is connected with a second end of the tenth capacitor, a second end of the second thermistor and a first end of the twelfth capacitor; the first end of the seventh capacitor, the first end of the eighth capacitor, the second end of the eleventh capacitor, the second end of the twelfth capacitor and the first end of the thirty-fourth resistor are all connected with a ground terminal; the cathode of the twelfth diode is connected with the first end of the first thermistor, the anode of the twelfth diode is connected with the anode of the eleventh diode, and the cathode of the eleventh diode is connected with the first end of the second thermistor; the cathode of the twelfth diode is connected with the signal bus and the second end of the first inductor respectively, the anode of the twelfth diode is connected with the anode of the thirteenth diode, and the cathode of the thirteenth diode is connected with the signal bus and the second end of the second inductor respectively; the first end of the first inductor is connected with the second end of the first thermistor, and the first end of the second inductor is connected with the second end of the second thermistor; the first end of the first piezoresistor is connected with the second end of the first inductor, the second end of the first piezoresistor is connected with the discharge tube, the first end of the second piezoresistor is connected with the second end of the second inductor, the second end of the second piezoresistor is connected with the discharge tube, and the discharge tube is also connected with the grounding end.

Compared with the related art, the driving circuit of the two-bus system provided by the embodiment of the application comprises: the device comprises a code sending circuit, a stream leakage circuit and a code receiving circuit; the output end of the code sending circuit is used for outputting a high level or a low level; the leakage circuit is respectively connected with the output end of the code sending circuit and the signal bus, and is used for leaking the electric quantity on the signal bus when the output end of the code sending circuit outputs a high level; the bleeder circuit comprises: the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first MOS (metal oxide semiconductor) tube, a first diode and a second diode; the base electrode of the first triode is connected with the second end of the first resistor, the collector electrode of the first triode is connected with the base electrode of the second triode, the emitter electrode of the first triode is connected with the input end of the code receiving circuit, the emitter electrode of the second triode is connected with the drain electrode of the first MOS tube, and the collector electrode of the second triode is connected with the first end of the second resistor; the first end of the first resistor is connected with the output end of the code sending circuit, the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the grounding end, the first end of the fourth resistor is respectively connected with the first end of the second resistor and the first end of the sixth resistor, the second end of the fourth resistor is connected with the first end of the fifth resistor, the second end of the fifth resistor is connected with the grounding end, and the second end of the sixth resistor is connected with the grid electrode of the first MOS tube; the source electrode of the first MOS tube is connected with the grounding end, and the drain electrode of the first MOS tube is connected with the signal bus; the cathode of the first diode is connected with the second end of the sixth resistor and the grid of the first MOS tube respectively, the anode of the first diode is connected with the grounding end, the cathode of the second diode is connected with the drain electrode of the first MOS tube, and the anode of the second diode is connected with the source electrode of the first MOS tube. By the method and the device, the problem of low fault tolerance of the driving circuit of the two-bus system in the related technology is solved, and the technical effect of improving the fault tolerance of the driving circuit of the two-bus system is achieved.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a circuit diagram of a driver circuit for a two bus system according to an embodiment of the present application;

FIG. 2 is a circuit diagram of a code transmitting circuit according to an embodiment of the present application;

FIG. 3 is a circuit diagram of a code receiving circuit according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a current monitoring circuit and a protection circuit according to an embodiment of the present application;

fig. 5 is a circuit diagram of a driving circuit of a two-bus system according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any inventive step are within the scope of protection of the present application. Moreover, it should be appreciated that such a development effort might be complex and tedious, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure, given the benefit of this disclosure, without departing from the scope of this disclosure.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of ordinary skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments without conflict.

Unless defined otherwise, technical or scientific terms referred to herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar words throughout this application are not to be construed as limiting in number, and may refer to the singular or the plural. The use of the terms "including," "comprising," "having," and any variations thereof herein, is meant to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or elements, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in this application is not intended to be limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference herein to "a plurality" means greater than or equal to two. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. Reference herein to the terms "first," "second," "third," and the like, are merely to distinguish similar objects and do not denote a particular ordering for the objects.

The present embodiment provides a driving circuit of a two-bus system, and fig. 1 is a driving circuit diagram of a two-bus system according to an embodiment of the present application, and as shown in fig. 1, the driving circuit of the two-bus system includes: a code sending circuit 10, a bleeder circuit 20 and a code receiving circuit 30; wherein, the output end of the code sending circuit 10 is used for outputting high level or low level; the bleeder circuit 20 is respectively connected with the output end of the code sending circuit 10 and the signal bus 40, and the bleeder circuit 20 is used for bleeding the electric quantity on the signal bus 40 when the output end of the code sending circuit 10 outputs a high level; the bleeder circuit 20 comprises: the circuit comprises a first triode Q1, a second triode Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first MOS transistor M1, a first diode D1 and a second diode D2; the base electrode of the first triode Q1 is connected with the second end of the first resistor R1, the collector electrode of the first triode Q1 is connected with the base electrode of the second triode Q3, the emitter electrode of the first triode Q1 is connected with the input end of the code receiving circuit 30, the emitter electrode of the second triode Q3 is connected with the drain electrode of the first MOS transistor M1, and the collector electrode of the second triode Q3 is connected with the first end of the second resistor R2; a first end of the first resistor R1 is connected to an output end of the code sending circuit 10, a second end of the second resistor R2 is connected to a first end of the third resistor R3, a second end of the third resistor R3 is connected to a ground GND, a first end of the fourth resistor R4 is connected to a first end of the second resistor R2 and a first end of the sixth resistor R6, a second end of the fourth resistor R4 is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to the ground GND, and a second end of the sixth resistor R6 is connected to a gate of the first MOS transistor M1; the source of the first MOS transistor M1 is connected to the ground GND, and the drain of the first MOS transistor M1 is connected to the signal bus 40; the cathode of the first diode D1 is connected to the second end of the sixth resistor R6 and the gate of the first MOS transistor M1, the anode of the first diode D1 is connected to the ground GND, the cathode of the second diode D2 is connected to the drain of the first MOS transistor M1, and the anode of the second diode D2 is connected to the source of the first MOS transistor M1.

In this embodiment, the base voltage of the first transistor Q1 is a drain enable terminal, that is, the high-level control terminal controls the code-sending voltage and controls the enabling of the drain circuit 20, and when the code-sending circuit 10 outputs a high level, the drain function of the drain circuit 20 is turned off; when the output of the code sending circuit 10 is not high, the draining function of the draining circuit 20 is turned on.

In the present embodiment, the extent to which the voltage on the signal bus 40 is drained is determined by comparing the magnitude relationship between the actual voltage on the signal bus 40 and the voltage receiving point (two states of middle level/low level) of the first transistor Q1 and the second transistor Q2, wherein the draining process of the draining circuit 20 is divided into three states:

1. in the initial leakage, in actual operation, each triode has a response time, and does not reach a conducting state from a turn-off state instantaneously, but has a linear process, during the initial leakage, the second triode Q2 is changed from a turn-off state to a linear state, the voltage on R2-R5 gradually rises, and approaches the vgs (th) voltage of the first MOS transistor M1.

2. The voltage on R2-R5 gradually increases due to strong current leakage, so that the VGS voltage of the first MOS transistor M1 increases to the fully-on voltage of the first MOS transistor M1, and because the first diode D1 exists, the VGS voltage of the first MOS transistor M1 is always in a safe state, most of the electric quantity on the signal bus 40 is leaked by the first MOS transistor M1, and most of the electric quantity is leaked by the second transistor Q2, because the leaked instantaneous energy is, the problem of overload and overheating does not exist in the first MOS transistor M1, and meanwhile, a resistor with a proper size can be connected in series to the DS connection path of the first MOS transistor M1 according to the size of the load capacitance on the signal bus 40.

3. And finishing the current leakage, when the voltage on the signal bus 40 is close to a comparison point (voltage code collecting point), the voltages of the R2-R5 are reduced to the turn-off voltage of the first MOS transistor M1, the second triode Q2 is turned off from the conduction state, and the current leakage process is finished.

In the related art, the driving circuit of the two-bus communication system is often controlled by the control software of the host device, and when the control software of the host device fails, the loop inevitably has an abnormal leakage condition, which results in low fault tolerance and poor abnormality resistance of the driving circuit of the two-bus system.

In this embodiment, whether the current is discharged or not, the control of the current discharge time and the target voltage of the current discharge are completely determined by hardware logic, software does not participate completely, the fault tolerance and absolute safety of the device are ensured, and the abnormal current discharge condition does not occur in the loop under the abnormal condition of the software; and the drainage rate of the drainage circuit 20 is increased, the drainage capacity is further enhanced, the communication rate is increased, the communication channel is enhanced, and the number of the loads is increased. By the method and the device, the problem of low fault tolerance of the driving circuit of the two-bus system in the related technology is solved, and the technical effect of improving the fault tolerance of the driving circuit of the two-bus system is achieved.

Fig. 2 is a circuit diagram of a code sending circuit 10 according to an embodiment of the present application, and as shown in fig. 2, in some embodiments, the code sending circuit 10 includes a code sending control circuit 101 and a code sending current limiting circuit 102; wherein, the output end of the code sending control circuit 101 is used for outputting high level or low level; the code-sending current-limiting circuit 102 is respectively connected with the code-sending control circuit 101 and the signal bus 40, and the code-sending current-limiting circuit 102 is used for limiting the magnitude of the current flowing between the code-sending control circuit 101 and the signal bus 40 when the back end of the signal bus 40 is overloaded.

As shown in fig. 2, in the present embodiment, the code transmission control circuit 101 includes: a first power supply +28V, a third triode Q3, a fourth triode Q4, a fifth triode Q5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a third diode D3; the first power supply +28V is respectively connected with the first end of the seventh resistor R7, the first end of the eighth resistor R8, the emitter of the third triode Q3 and the cathode of the third diode D3; a collector of the third triode Q3 is connected with a first end of the ninth resistor R9, and a base of the third triode Q3 is connected with a second end of the tenth resistor R10 and a second end of the eighth resistor R8, respectively; a base electrode of the fourth triode Q4 is respectively connected with a collector electrode of the fifth triode Q5 and a second end of the seventh resistor R7, a collector electrode of the fourth triode Q4 is connected with a first end of the tenth resistor R10, and an emitter electrode of the fourth triode Q4 is connected with a first end of the eleventh resistor R11; the base electrode of the fifth triode Q5 is connected with the second end of the thirteenth resistor R13, and the emitter electrode of the fifth triode Q5 is connected with the ground end GND; the second end of the eleventh resistor R11 is connected to the ground GND, the anode of the third diode D3 is connected to the second end of the ninth resistor R9 and the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 is connected to the ground GND, and the anode and the cathode of the third diode D3 are both connected to the code-sending current-limiting circuit 102.

As shown in fig. 2, in the present embodiment, the code current limiting circuit 102 includes: a sixth triode Q6, a second MOS transistor M2, a fourth diode D4, a fourteenth resistor R14, a fifteenth resistor R15, a first capacitor C1, and a second capacitor C2; an emitter of the sixth triode Q6 is connected to a cathode of the third diode D3 and a first end of the fifteenth resistor R15, a collector of the sixth triode Q6 is connected to an anode of the third diode D3 and a gate of the second MOS transistor M2, and a base of the sixth triode Q6 is connected to a first end of the fourteenth resistor R14; a source of the second MOS transistor M2 is connected to the second end of the fourteenth resistor R14 and the second end of the fifteenth resistor R15, respectively, and a drain of the second MOS transistor M2 is connected to an emitter of the second transistor Q3; the cathode of the fourth diode D4 is connected to the source of the second MOS transistor M2, and the anode of the fourth diode D4 is connected to the drain of the second MOS transistor M2; a first end of the first capacitor C1 is connected to a first end of the fifteenth resistor R15 and a first end of the second capacitor C2, respectively, and a second end of the first capacitor C1 and a second end of the second capacitor C2 are both connected to the ground GND.

In this embodiment, the host device or the processor indirectly controls the state of the third transistor Q3 by controlling the state of the fifth transistor Q5, when the fifth transistor Q5 is turned on, there is no voltage difference between the third diode D3, and therefore, the VGS voltage of the second MOS transistor M2 is equal to 0, and no high level is output, i.e., no high level is output on the signal bus 40; when the fifth transistor Q5 is turned off, the voltage across the third diode D3 is the regulated voltage of the third diode D3, which is greater than the conducting VGS voltage of the second MOS transistor M2, and at this time, a high level is output, i.e., the signal bus 40 is at a high level.

In the embodiment, the code current limiting circuit 102 is a hardware current limiting circuit, which limits the source current of the back-end load (the load on the signal bus 40), and when the back-end load is a light load, the current flows from the first power supply +28V to the back-end load through the fifteenth resistor R15, the second MOS transistor M2; when the rear-end load is overloaded, the sixth triode Q6 is amplified or conducted, the VGS voltage changes, the second MOS transistor M2 is switched from the on state to the off state, and surge current generated by powering on the rear-end slave device at the same time can be prevented while limiting current, so as to protect the host device.

Through the embodiment, the code sending and current limiting of the host equipment are realized through hardware, the loop can still ensure the hardware current limiting protection under the abnormal condition of software, the fault tolerance of the driving circuit of the two-bus system is further improved, and meanwhile, the code receiving and sending of the host equipment are compatible with universal protocol data layers such as UART/RS485 and the like. Has easy development.

Fig. 3 is a circuit diagram of a code receiving circuit 30 according to an embodiment of the present application, as shown in fig. 3, in some embodiments, the code receiving circuit 30 includes a code receiving voltage modulation circuit 301 and a code receiving current demodulation circuit 302; wherein, receive code voltage modulation circuit 301 includes: a first operational amplifier U1A, a seventh triode Q7, an eighth triode Q8, a third capacitor C3, a fifth diode D5, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21 and a twenty-second resistor R22; the inverting input end of the first operational amplifier U1A is connected to the first end of the twenty-first resistor R21, the first end of the first operational amplifier U1A is connected to the ground GND, the second end of the first operational amplifier U1A is connected to the +28V of the first power supply, and the output end of the first operational amplifier U1A is connected to the first end of the third capacitor C3 and the first end of the nineteenth resistor R19, respectively; an emitter of the seventh triode Q7 is connected to the second end of the sixteenth resistor R16, a base of the seventh triode Q7 is connected to the second end of the nineteenth resistor R19 and the cathode of the fifth diode D5, respectively, and a collector of the seventh triode Q7 is connected to the first end of the seventeenth resistor R17 and the anode of the fifth diode D5, respectively; an emitter of the eighth triode Q8 is connected with the second end of the seventeenth resistor R17, the first end of the twentieth resistor R20 and the first end of the eighteenth resistor R18 respectively, a base of the eighth triode Q8 is connected with the anode of the fifth diode D5, and a collector of the eighth triode Q8 is connected with the second end of the nineteenth resistor R19; a second end of the third capacitor C3 is connected with a first end of the twenty-first resistor R21 and a first end of the twenty-second resistor R22, respectively; a first end of the sixteenth resistor R16 is connected to the +28V of the first power supply, a second end of the eighteenth resistor R18 is connected to the emitter of the first transistor Q1, the signal bus 40 and the code-receiving current demodulation circuit 302, a second end of the twentieth resistor R20 is connected to the second end of the twenty-second resistor R22 and the code-receiving current demodulation circuit 302, and a second end of the twenty-first resistor R21 is connected to the ground GND.

As shown in fig. 3, in the present embodiment, the receive current demodulation circuit 302 includes: a third MOS transistor M3, a second power supply +3.3V, a fourth capacitor C4, a second operational amplifier U2A, a sixth diode D6, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, and a twenty-seventh resistor R27; a source of the third MOS transistor M3 is connected to a ground GND, a drain of the third MOS transistor M3 is connected to a second end of the twenty-third resistor R23, and a gate of the third MOS transistor M3 is connected to a cathode of the sixth diode D6 and a first end of the twenty-seventh resistor R27, respectively; the second power supply +3.3V is connected with the first end of a twenty-third resistor R23; a first end of the fourth capacitor C4 is connected to the non-inverting input terminal of the second operational amplifier U2A, and a second end of the fourth capacitor C4 is connected to the inverting input terminal of the second operational amplifier U2A; the output end of the second operational amplifier U2A is connected with the second end of the twenty-seventh resistor R27; the anode of the sixth diode D6 is connected to the ground GND; a first end of a twenty-fourth resistor R24 is connected to a second end of the twentieth resistor R20 and a non-inverting input terminal of the second operational amplifier U2A, a second end of the twenty-fourth resistor R24 is connected to a ground terminal GND, a first end of a twenty-fifth resistor R25 is connected to a second end of the twentieth resistor R20 and a second end of the eighteenth resistor R18, a second end of the twenty-fifth resistor R25 is connected to an inverting input terminal of the second operational amplifier U2A and a first end of a twenty-sixth resistor R26, and a second end of the twenty-sixth resistor R26 is connected to the ground terminal GND.

In this embodiment, the first operational amplifier U1A, its feedback loop, and the seventh transistor Q7 form a series linear voltage regulator circuit with negative feedback, and the output voltage of the first operational amplifier U1A is adjusted through the feedback point behind the eighteenth resistor R18, so as to adjust the linear amplification operating state of the seventh transistor Q7, so as to ensure that the potential behind the eighteenth resistor R18 is (VIN +) (1+ R22/R21), and even if the voltage drop of the seventeenth resistor R17 and the eighteenth resistor R18 changes due to the current change on the signal bus 40, the stability of the level of the code receiving current can be ensured.

In this embodiment, the first power supply +28V, the sixteenth resistor R16, the seventh transistor Q7, the seventeenth resistor 17, the fifth diode D5, and the eighth transistor Q8 further form a code-receiving voltage current-limiting circuit 303, and the voltage drop of the seventeenth resistor R17 competes with the Vbe of the eighth transistor Q8, so that the current limit I is Vbe/R17, and when an overcurrent occurs, the voltage is pulled down.

In this embodiment, the received code current demodulation circuit 302 detects the received code current by using a differential amplification circuit for common mode interference resistance, and converts the current signal into a digital voltage signal, and the digital signal is commonly used with data layers such as a universal protocol UART/RS458, which is convenient for development. The threshold value of the current is VGSth (third MOS transistor M3)/(R24/R25)/R18.

Through the embodiment, the medium level of the voltage receiving code can not cause the output voltage change of the medium level according to the change of the load or the return code current, the code receiving current limiting of the host equipment is realized through hardware, the loop can still ensure the hardware current limiting protection under the condition of software exception, the fault tolerance of the driving circuit of the two-bus system is further improved, and meanwhile, the receiving and sending codes of the host equipment are compatible with universal protocol data layers such as UART/RS485 and the like. Has easy development.

Fig. 4 is a circuit diagram of a current monitoring circuit 50 and a protection circuit 60 according to an embodiment of the present application, and as shown in fig. 4, in some embodiments, the driving circuit of the two-bus system further includes a current monitoring circuit 50, the current monitoring circuit 50 is connected between the signal bus 40 and the bleeder circuit 20, and the current monitoring circuit 50 is configured to detect a two-wire current magnitude of the signal bus 40 and a leakage current magnitude of the signal bus 40.

As shown in fig. 4, in the present embodiment, the current monitoring circuit 50 includes: a third operational amplifier U3A, a fifth capacitor C5, a sixth capacitor C6, a seventh diode D7, an eighth diode D8, a ninth diode D9, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirty-third resistor R30, a thirty-eleventh resistor R31, a thirty-second resistor R32, and a thirty-third resistor R33; the non-inverting input end of the third operational amplifier U3A is connected to the second end of the thirty-first resistor R31 and the second end of the twenty-ninth resistor R29, respectively, and the inverting input end of the third operational amplifier U3A is connected to the first end of the thirty-second resistor R32 and the second end of the thirty-second resistor R30, respectively; a first end of a fifth capacitor C5 is connected with a first end of a twenty-eighth resistor R28 and the drain of the first MOS transistor M1, respectively, and a second end of the fifth capacitor C5 is connected with the signal bus 40 and a second end of the twenty-eighth resistor R28, respectively; a first end of a sixth capacitor C6 is connected to a second end of the twenty-ninth resistor R29 and a non-inverting input terminal of the third operational amplifier U3A, respectively, and a second end of the sixth capacitor C6 is connected to a second end of the thirty-second resistor R30 and an inverting input terminal of the third operational amplifier U3A, respectively; the anode of the seventh diode D7 is connected to the first end of the twenty-eighth resistor R28 and the cathode of the eighth diode D8, respectively, and the cathode of the seventh diode D7 is connected to the second end of the twenty-eighth resistor R28 and the anode of the eighth diode D8, respectively; the cathode of the eighth diode D8 is connected to the first end of the twenty-ninth resistor R29, and the anode of the eighth diode D8 is connected to the first segment of the thirty-first resistor R30; the negative electrode of the ninth diode D9 is connected to the first end of the thirty-third resistor R33, and the positive electrode of the ninth diode D9 is connected to the ground GND; a first end of the thirty-first resistor R31 is connected to the ground GND, and a second end of the thirty-second resistor R32 is connected to an output terminal of the third operational amplifier U3A and a second end of the thirty-third resistor R33, respectively.

As shown in fig. 4, in some embodiments, the driving circuit of the two-bus system further includes a protection circuit 60; the protection circuit 60 is connected between the current monitoring circuit 50 and the signal bus 40, and the protection circuit 60 is used for performing surge protection and filtering processing on the signal bus 40.

As shown in fig. 4, in the present embodiment, the protection circuit 60 includes: a common-mode inductor FIL, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a twelfth diode D10, an eleventh diode D11, a twelfth diode D12, a thirteenth diode D13, a first inductor L1, a second inductor L2, a first thermistor RT1, a second thermistor RT2, a first piezoresistor RV1, a second piezoresistor RV2, a thirty-fourth resistor R34 and a discharge tube GDT; the first end of the common-mode inductor FIL is connected to the second end of the seventh capacitor C7, the first end of the current monitoring circuit 50 and the first end of the ninth capacitor C9, the second end of the common-mode inductor FIL is connected to the second end of the ninth capacitor C9, the second end of the thirty-fourth resistor R34 and the first end of the eleventh capacitor C11, the third end of the common-mode inductor FIL is connected to the second end of the eighth capacitor C8, the first end of the tenth capacitor C10 and the first end of the first thermistor RT1, and the fourth end of the common-mode inductor FIL is connected to the second end of the tenth capacitor C10, the second end of the second thermistor RT2 and the first end of the twelfth capacitor C12; the first end of the seventh capacitor C7, the first end of the eighth capacitor C8, the second end of the eleventh capacitor C11, the second end of the twelfth capacitor C12 and the first end of the thirty-fourth resistor R34 are all connected to the ground GND; the negative electrode of the twelfth diode D10 is connected with the first end of the first thermistor RT1, the positive electrode of the twelfth diode D10 is connected with the positive electrode of the eleventh diode D11, and the negative electrode of the eleventh diode D11 is connected with the first end of the second thermistor RT 2; the cathode of the twelfth diode D12 is connected to the signal bus 40 and the second end of the first inductor L1, respectively, the anode of the twelfth diode D12 is connected to the anode of the thirteenth diode D13, and the cathode of the thirteenth diode D13 is connected to the signal bus 40 and the second end of the second inductor L2, respectively; a first end of the first inductor L1 is connected with a second end of the first thermistor RT1, and a first end of the second inductor L2 is connected with a second end of the second thermistor RT 2; the first end of the first piezoresistor RV1 is connected with the second end of the first inductor L1, the second end of the first piezoresistor RV1 is connected with the discharge tube GDT, the first end of the second piezoresistor RV2 is connected with the second end of the second inductor L2, the second end of the second piezoresistor RV2 is connected with the discharge tube GDT, and the discharge tube GDT is further connected with the ground terminal GND.

In this embodiment, the first varistor RV1, the second varistor RV2 and the discharge tube GDT form a first-stage protection circuit, the first inductor L1 and the second inductor L2 form a common-mode delay circuit, the twelfth diode D10, the eleventh diode D11, the twelfth diode D12 and the thirteenth diode D13 form a second-stage protection circuit, and the common-mode inductor FIL, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11 and the twelfth capacitor C12 form a decoupling filter circuit.

Fig. 5 is a circuit diagram of a driving circuit of a two-bus system according to another embodiment of the present application, and in some embodiments, the driving circuit of the two-bus system includes a code sending circuit 10, a bleeder circuit 20, a code receiving circuit 30, a current monitoring circuit 50, and a protection circuit 60 as described in the above embodiments, as shown in fig. 5.

It should be noted that, for specific examples in this embodiment, reference may be made to examples described in the foregoing embodiments and optional implementations, and details of this embodiment are not described herein again.

It should be understood by those skilled in the art that various technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present description should be considered as being described in the present specification.

The above examples are merely illustrative of several embodiments of the present application, and the description is more specific and detailed, but not to be construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A driving circuit for a two-bus system, comprising: the device comprises a code sending circuit, a stream leakage circuit and a code receiving circuit;

the output end of the code sending circuit is used for outputting a high level or a low level;

the leakage circuit is respectively connected with the output end of the code sending circuit and a signal bus, and is used for releasing the electric quantity on the signal bus when the output end of the code sending circuit outputs a high level; the bleeder circuit comprises: the circuit comprises a first triode, a second triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first MOS (metal oxide semiconductor) tube, a first diode and a second diode;

the base electrode of the first triode is connected with the second end of the first resistor, the collector electrode of the first triode is connected with the base electrode of the second triode, the emitter electrode of the first triode is connected with the input end of the code receiving circuit, the emitter electrode of the second triode is connected with the drain electrode of the first MOS tube, and the collector electrode of the second triode is connected with the first end of the second resistor;

the first end of the first resistor is connected with the output end of the code sending circuit, the second end of the second resistor is connected with the first end of the third resistor, the second end of the third resistor is connected with a ground terminal, the first end of the fourth resistor is respectively connected with the first end of the second resistor and the first end of the sixth resistor, the second end of the fourth resistor is connected with the first end of the fifth resistor, the second end of the fifth resistor is connected with the ground terminal, and the second end of the sixth resistor is connected with the gate of the first MOS transistor;

the source electrode of the first MOS tube is connected with the grounding end, and the drain electrode of the first MOS tube is connected with the signal bus;

the cathode of the first diode is connected with the second end of the sixth resistor and the grid electrode of the first MOS tube, the anode of the first diode is connected with the grounding end, the cathode of the second diode is connected with the drain electrode of the first MOS tube, and the anode of the second diode is connected with the source electrode of the first MOS tube.

2. The driving circuit of two-bus system according to claim 1, wherein the code-sending circuit comprises a code-sending control circuit and a code-sending current-limiting circuit;

the output end of the code sending control circuit is used for outputting a high level or a low level;

the code sending current limiting circuit is respectively connected with the code sending control circuit and the signal bus, and is used for limiting the magnitude of current flowing between the code sending control circuit and the signal bus when the rear end load of the signal bus is overloaded.

3. The driving circuit of two-bus system according to claim 2, wherein the code control circuit comprises: the first resistor is connected with the first power supply, the third triode, the fourth triode, the fifth triode, the seventh resistor, the eighth resistor, the ninth resistor, the tenth resistor, the eleventh resistor, the twelfth resistor, the thirteenth resistor and the third diode;

the first power supply is respectively connected with a first end of the seventh resistor, a first end of the eighth resistor, an emitter of the third triode and a cathode of the third diode;

a collector of the third triode is connected with a first end of the ninth resistor, and a base of the third triode is respectively connected with a second end of the tenth resistor and a second end of the eighth resistor;

a base electrode of the fourth triode is respectively connected with a collector electrode of the fifth triode and a second end of the seventh resistor, a collector electrode of the fourth triode is connected with a first end of the tenth resistor, and an emitting electrode of the fourth triode is connected with a first end of the eleventh resistor;

a base electrode of the fifth triode is connected with a second end of the thirteenth resistor, and an emitting electrode of the fifth triode is connected with a grounding end;

the second end of the eleventh resistor is connected with the ground terminal, the anode of the third diode is respectively connected with the second end of the ninth resistor and the first end of the twelfth resistor, the second end of the twelfth resistor is connected with the ground terminal, and the anode and the cathode of the third diode are both connected with the code-sending current-limiting circuit.

4. The driving circuit of a two-bus system according to claim 3, wherein the code-transmitting current-limiting circuit comprises: the fourth transistor, the third MOS transistor, the fourth diode, the fourteenth resistor, the fifteenth resistor, the first capacitor and the second capacitor are connected in series;

an emitter of the sixth triode is connected with a cathode of the third diode and the first end of the fifteenth resistor respectively, a collector of the sixth triode is connected with an anode of the third diode and the gate of the second MOS transistor respectively, and a base of the sixth triode is connected with the first end of the fourteenth resistor;

a source electrode of the second MOS transistor is connected to a second end of the fourteenth resistor and a second end of the fifteenth resistor, respectively, and a drain electrode of the second MOS transistor is connected to an emitter electrode of the second triode;

the cathode of the fourth diode is connected with the source electrode of the second MOS tube, and the anode of the fourth diode is connected with the drain electrode of the second MOS tube;

the first end of the first capacitor is connected with the first end of the fifteenth resistor and the first end of the second capacitor respectively, and the second end of the first capacitor and the second end of the second capacitor are both connected with a ground terminal.

5. The driving circuit of two-bus system according to claim 1, wherein the code receiving circuit comprises a code receiving voltage modulation circuit and a code receiving current demodulation circuit;

wherein, receive the code voltage modulation circuit and include: the first operational amplifier, the seventh triode, the eighth triode, the third capacitor, the fifth diode, the sixteenth resistor, the seventeenth resistor, the eighteenth resistor, the nineteenth resistor, the twentieth resistor, the twenty-first resistor and the twenty-second resistor;

the inverting input end of the first operational amplifier is connected with the first end of the twenty-first resistor, the first end of the first operational amplifier is connected with the grounding end, the second end of the first operational amplifier is connected with a first power supply, and the output end of the first operational amplifier is respectively connected with the first end of the third capacitor and the first end of the nineteenth resistor;

an emitting electrode of the seventh triode is connected with a second end of the sixteenth resistor, a base electrode of the seventh triode is respectively connected with a second end of the nineteenth resistor and a negative electrode of the fifth diode, and a collector electrode of the seventh triode is respectively connected with a first end of the seventeenth resistor and a positive electrode of the fifth diode;

an emitter of the eighth triode is connected with the second end of the seventeenth resistor, the first end of the twentieth resistor and the first end of the eighteenth resistor respectively, a base of the eighth triode is connected with the anode of the fifth diode, and a collector of the eighth triode is connected with the second end of the nineteenth resistor;

a second end of the third capacitor is respectively connected with a first end of the twenty-first resistor and a first end of the twenty-second resistor;

the first end of the sixteenth resistor is connected with the first power supply, the second end of the eighteenth resistor is connected with the emitting electrode of the first triode, the signal bus and the code receiving current demodulation circuit, the second end of the twentieth resistor is connected with the second end of the twenty-second resistor and the code receiving current demodulation circuit respectively, and the second end of the twenty-first resistor is connected with the grounding end.

6. The driving circuit of two-bus system according to claim 5, wherein the receiving current demodulation circuit comprises: the third MOS tube, the second power supply, the fourth capacitor, the second operational amplifier, the sixth diode, the twenty-third resistor, the twenty-fourth resistor, the twenty-fifth resistor, the twenty-sixth resistor and the twenty-seventh resistor;

a source electrode of the third MOS transistor is connected to the ground terminal, a drain electrode of the third MOS transistor is connected to the second end of the twenty-third resistor, and a gate electrode of the third MOS transistor is connected to a negative electrode of the sixth diode and the first end of the twenty-seventh resistor, respectively;

the second power supply is connected with a first end of the twenty-third resistor;

a first end of the fourth capacitor is connected with a non-inverting input end of the second operational amplifier, and a second end of the fourth capacitor is connected with an inverting input end of the second operational amplifier;

the output end of the second operational amplifier is connected with the second end of the twenty-seventh resistor;

the anode of the sixth diode is connected with the grounding end;

the first end of twenty-fourth resistance respectively with the second end of twentieth resistance with the non inverting input end of second operational amplifier is connected, the second end of twenty-fourth resistance is connected with the earthing terminal, the first end of twenty-fifth resistance respectively with the second end of twentieth resistance with the second end of eighteenth resistance is connected, the second end of twenty-fifth resistance respectively with the inverting input end of second operational amplifier with the first end of twenty-sixth resistance is connected, the second end of twenty-sixth resistance is connected with the earthing terminal.

7. The driving circuit of a two-bus system according to claim 1, further comprising a current monitoring circuit;

the current monitoring circuit is connected between the signal bus and the current leakage circuit and is used for detecting the current of two lines of the signal bus and the current leakage of the signal bus.

8. The driving circuit of a two-bus system according to claim 7, wherein the current monitoring circuit comprises: the third operational amplifier, the fifth capacitor, the sixth capacitor, the seventh diode, the eighth diode, the ninth diode, the twenty-eighth resistor, the twenty-ninth resistor, the thirtieth resistor, the thirty-eleventh resistor, the thirty-second resistor and the thirty-third resistor;

the non-inverting input end of the third operational amplifier is connected with the second end of the thirty-first resistor and the second end of the twenty-ninth resistor respectively, and the inverting input end of the third operational amplifier is connected with the first end of the thirty-second resistor and the second end of the thirty-second resistor respectively;

a first end of the fifth capacitor is connected with a first end of the twenty-eighth resistor and a drain electrode of the first MOS transistor respectively, and a second end of the fifth capacitor is connected with the signal bus and a second end of the twenty-eighth resistor respectively;

a first end of the sixth capacitor is connected with a second end of the twenty-ninth resistor and a non-inverting input end of the third operational amplifier respectively, and a second end of the sixth capacitor is connected with a second end of the thirty-third resistor and an inverting input end of the third operational amplifier respectively;

the anode of the seventh diode is connected with the first end of the twenty-eighth resistor and the cathode of the eighth diode respectively, and the cathode of the seventh diode is connected with the second end of the twenty-eighth resistor and the anode of the eighth diode respectively;

a cathode of the eighth diode is connected with a first end of the twenty-ninth resistor, and an anode of the eighth diode is connected with a first section of the thirty-third resistor;

the negative electrode of the ninth diode is connected with the first end of the thirty-third resistor, and the positive electrode of the ninth diode is connected with the grounding end;

a first end of the thirty-first resistor is connected to the ground terminal, and a second end of the thirty-second resistor is connected to an output end of the third operational amplifier and a second end of the thirty-third resistor, respectively.

9. The driver circuit for a two-bus system according to claim 7, further comprising a protection circuit;

the protection circuit is connected between the current monitoring circuit and the signal bus, and the protection circuit is used for performing surge protection and filtering processing on the signal bus.

10. The drive circuit of a two-bus system according to claim 9, wherein the protection circuit comprises: the common-mode inductor, the seventh capacitor, the eighth capacitor, the ninth capacitor, the tenth capacitor, the eleventh capacitor, the twelfth diode, the eleventh diode, the twelfth diode, the thirteenth diode, the first inductor, the second inductor, the first thermistor, the second thermistor, the first piezoresistor, the second piezoresistor, the thirty-fourth resistor and the discharge tube;

a first end of the common mode inductor is connected with a second end of the seventh capacitor, a first end of the current monitoring circuit and a first end of the ninth capacitor, a second end of the common mode inductor is connected with a second end of the ninth capacitor, a second end of the thirty-fourth resistor and a first end of the eleventh capacitor, a third end of the common mode inductor is connected with a second end of the eighth capacitor, a first end of the tenth capacitor and a first end of the first thermistor, and a fourth end of the common mode inductor is connected with a second end of the tenth capacitor, a second end of the second thermistor and a first end of the twelfth capacitor;

the first end of the seventh capacitor, the first end of the eighth capacitor, the second end of the eleventh capacitor, the second end of the twelfth capacitor and the first end of the thirty-fourth resistor are all connected with a ground terminal;

the negative electrode of the twelfth diode is connected with the first end of the first thermistor, the positive electrode of the twelfth diode is connected with the positive electrode of the eleventh diode, and the negative electrode of the eleventh diode is connected with the first end of the second thermistor;

the cathode of the twelfth diode is connected with the signal bus and the second end of the first inductor respectively, the anode of the twelfth diode is connected with the anode of the thirteenth diode, and the cathode of the thirteenth diode is connected with the signal bus and the second end of the second inductor respectively;

the first end of the first inductor is connected with the second end of the first thermistor, and the first end of the second inductor is connected with the second end of the second thermistor;

the first end of the first piezoresistor is connected with the second end of the first inductor, the second end of the first piezoresistor is connected with the discharge tube, the first end of the second piezoresistor is connected with the second end of the second inductor, the second end of the second piezoresistor is connected with the discharge tube, and the discharge tube is also connected with the grounding end.