CN217240680U - Low operating voltage ring oscillator with self-starting bias circuit - Google Patents

Abstract

The utility model provides a take low operating voltage ring oscillator of self-starting biasing circuit, include: current source, bias circuit, oscillator circuit, the current source adopts self-starting power supply circuit, includes: the starting circuit inputs an enable signal ENB, the output end of the starting circuit is connected with the low-voltage PTAT current source and used for starting the low-voltage PTAT current source, the output end of the low-voltage PTAT current source is connected with the bias circuit, the output end of the current source is connected with the bias circuit, and the bias circuit is connected with the oscillator circuit; the PATA current source is driven by a self-starting power circuit to establish loop current; the PATA current source passes through the bias circuit and the charging and discharging circuit, so that the oscillator circuit obtains relatively stable current under different working voltages, and stable oscillation period and duty ratio are obtained.

Description

Low operating voltage ring oscillator with self-starting bias circuit

Technical Field

The utility model relates to a ring oscillator field, concretely relates to take low operating voltage ring oscillator of self-starting biasing circuit.

Background

The ring oscillator is formed by connecting odd inverters end to end by utilizing the inherent transmission delay time of a gate circuit, has simple circuit, easy oscillation starting and convenient integration, is commonly used for a clock generator, a timer and the like in an integrated circuit chip, but the oscillator cannot oscillate at certain moments and can cause partial or all functions of the chip to fail, so that the ring oscillator needs to be restarted or awakened to oscillate.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problem, the utility model provides a take low operating voltage ring oscillator of self-starting biasing circuit, concrete technical scheme is: the method comprises the following steps: the current source, the bias circuit and the oscillator circuit, wherein the output end of the current source is connected with the bias circuit, and the bias circuit is connected with the oscillator circuit; the current source adopts the self-starting power supply circuit, includes: the starting circuit inputs an enable signal ENB, the output end of the starting circuit is connected with the low-voltage PTAT current source and used for starting the low-voltage PTAT current source, and the output end of the low-voltage PTAT current source is connected with the bias circuit.

Further, the start-up circuit includes: the low-voltage PTAT current source comprises a first switch, a second switch and a third switch, wherein the first switch inputs an enable signal ENB, the output end of the first switch is connected with the signal input end of the second switch, and the second switch is started to enable the low-voltage PTAT current source to establish loop current; the third switch inputs loop current and is used for controlling the closing of the second switch, and the PTAT current source is realized from no loop current to loop current establishment and enters a normal oscillation state by using the switch structure.

Further, the start-up circuit includes: a first switch PMOS transistor M20, a second switch NMOS transistor M21, a third switch NMOS transistor, wherein the PMOS transistor M20: the grid inputs the enabling signal ENB, the source is connected with the voltage VDD, the drain is connected with the drain of the NMOS tube M19 and the grid of the NMOS tube M21; the source electrode of the NMOS tube M19 is connected with VSS; the drain of the NMOS transistor M21 is grounded, and the combined action of the enable signal and VDD turns on the first switch and turns on the second switch, so that the PATA current source establishes a loop current, and the third switch inputs the loop current and gradually turns off the second switch, so that the PATA current source is stabilized.

Further, the low voltage PTAT current source includes: PMOS pipe M15, PMOS pipe M16, NMOS pipe M17, NMOS pipe M18, resistance R1, PMOS pipe M15: the source electrode is connected with a voltage VDD, the grid electrode is connected with the drain electrode of the NMOS tube M21, and the drain electrode is connected with the drain electrode of the NMOS tube M18; the NMOS tube M18: the drain electrode is connected with the grid electrode and is connected with the grid electrode of the NMOS tube M19, and the source electrode is connected with VSS; the PMOS tube M16: the source electrode is connected with a voltage VDD, the grid electrode is connected with the drain electrode of the NMOS tube M21, the drain electrode is connected with the grid electrode and is also connected with the drain electrode of the NMOS tube M17; the NMOS tube M17: the grid electrode of the NMOS tube M19 is connected with the grid electrode of the NMOS tube, the drain electrode of the NMOS tube M19 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with VSS, the PMOS tube M15 and the PMOS tube M16 are of mirror image structures, when the second switch is turned on, the grid electrode of the mirror image structure is pulled down, therefore loop current is established, the second switch is turned off after the third switch is turned on, and the PATA current source normally works.

Further, the bias circuit comprises a PMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, and a PMOS transistor M10, wherein the PMOS transistor M10: the source electrode is connected with a voltage VDD, the grid electrode is connected with the grid electrode of the PMOS tube M16, and the drain electrode is connected with the drain electrode of the NMOS tube M9; the NMOS tube M9: the grid electrode is connected with the drain electrode, and the source electrode is connected with VSS; the PMOS tube M7: the source electrode is connected with a voltage VDD, the grid electrode is connected with the source electrode, and the source electrode is connected with the drain electrode of the NMOS tube M8; the NMOS tube M8: the grid electrode of the grid electrode is connected with the grid electrode of the NMOS tube M9, the source electrode of the NMOS tube M9 is connected with VSS, the grid electrodes of the PMOS tube M15 and the PMOS tube M16 are pulled down to be conducted, and the current of the bias circuit is obtained by copying the proportion of the PATA current source.

Further, the bias circuit is also connected with a charge-discharge branch, the charge-discharge branch comprises: PMOS transistor M5, NMOS transistor M6 and charge-discharge capacitor C1, PMOS transistor M5: the source electrode is connected with VDD, and the grid electrode is connected with the grid electrode of the PMOS transistor M7; the NMOS tube M6: the grid is connected with the grid of the NMOS tube M8, and the source is connected with VSS; the charging and discharging capacitor C1: and receiving the output current of the drain electrode of the PMOS transistor M5 or the drain electrode of the NMOS transistor M6, and connecting the grid electrodes of the PMOS transistor M5 and the NMOS transistor M6 with a bias circuit to obtain bias current and charge or discharge the charge-discharge capacitor C1.

Further, the oscillator circuit includes: the output end OSC of the odd number of series-connected inverters is connected with the feedback branch III, the output end of the odd number of series-connected inverters is connected with the VI of the feedback branch II and the feedback branch I after being connected with the inverter INV4 in series, the feedback branch I is further connected with a charge-discharge capacitor C1, the common output end of the feedback branch I and the feedback branch III is connected with the input end of the odd number of series-connected inverters, the oscillator circuit is matched with a charge-discharge circuit, and relatively stable current is obtained under different working voltages through the charge-discharge circuit, so that a stable oscillation period and a duty ratio are obtained.

Further, the feedback branch i includes: PMOS pipe M11, PMOS pipe M13, NMOS pipe M14, NMOS pipe M12, PMOS pipe M11: the source electrode is connected with VDD, the grid electrode is connected with the grid electrode of the NMOS tube M12 and is connected with the charge-discharge capacitor C1, and the drain electrode is connected with the source electrode of the PMOS tube M13; the PMOS tube M13: the grid electrode of the NMOS tube M14 is connected with the grid electrode of the inverter INV4, the drain electrode of the NMOS tube M14 is connected with the drain electrode of the NMOS tube M14, and the output end of the feedback branch circuit III is connected with the drain electrode of the NMOS tube M14; the NMOS tube M14: the source electrode is connected with the drain electrode of the NMOS tube M12; the NMOS tube M12: the source is connected to VSS.

Further, the feedback branch ii includes: PMOS pipe M1, NMOS pipe M2, PMOS pipe M1: the source electrode is connected with the drain electrode of the PMOS tube M5, the grid electrode is connected with the grid electrode of the NMOS tube M2 and is connected with the output end of the inverter INV4, and the drain electrode is connected with the drain electrode of the NMOS tube M2 and is connected with the charge-discharge capacitor C1; the NMOS tube M2: the source is connected with the drain of the NMOS transistor M6.

Further, the feedback branch iii includes: PMOS pipe M3, NMOS pipe M4, the PMOS pipe M3: the source electrode is connected with the drain electrode of the PMOS tube M5, the grid electrode is connected with the grid electrode of the NMOS tube M4, the drain electrode is connected with the drain electrode of the NMOS tube M4, the drain electrode is also connected with the input ends of odd number of inverters connected in series, and the drain electrode is also connected with the drain electrode of the PMOS tube M13 and the drain electrode of the NMOS tube M14; the NMOS tube M4: the grid electrode is connected with the output end OSC of the odd number of inverters in series, and the source electrode is connected with the drain electrode of the NMOS tube M6.

Compared with the prior art the utility model discloses following beneficial effect has: the PATA current source is driven by a self-starting power circuit to establish loop current; the PATA current source passes through the bias circuit and the charging and discharging circuit, so that the oscillator circuit obtains relatively stable current under different working voltages, and stable oscillation period and duty ratio are obtained.

Drawings

FIG. 1 is a schematic circuit diagram of the present patent;

fig. 2 is a waveform diagram of a ring oscillator circuit of the present patent.

Detailed Description

The present invention will now be further described with reference to the accompanying drawings.

As shown in fig. 1, the patent includes: the current source, bias circuit, charge-discharge branch road, oscillator circuit, current source output termination bias circuit, bias circuit connects charge-discharge branch road, and charge-discharge branch road acquires bias circuit's bias current, makes the oscillator circuit under the different operating voltage can obtain relatively stable electric current through charge-discharge branch road, obtains stable oscillation cycle and duty cycle, and this patent application is based on 0.5um COMS technology, and the power is low to 0.9V can work.

Wherein, the electric current source adopts self-starting power supply circuit, and self-starting power supply circuit includes: the circuit comprises a starting circuit and a low-voltage PTAT current source, wherein the starting circuit inputs an enabling signal ENB, the output end of the starting circuit is connected with the low-voltage PTAT current source and used for starting the low-voltage PTAT current source to establish loop current, and the output end of the low-voltage PTAT current source is connected with a bias circuit.

Further, the start-up circuit includes: the first switch inputs an enable signal ENB, the output end of the first switch is connected with the signal input end of the second switch, the second switch is controlled to be started, and the second switch is started to enable the low-voltage PTAT current source to establish loop current; after the loop current is established, the third switch inputs the loop current and controls the second switch to be closed, the starting circuit enables the PATA current source to enter a normal working state, and the starting circuit is closed after the PATA current source works, so that the normal working state of the starting circuit is not influenced.

Further, the start-up circuit includes: a first switch PMOS transistor M20, a second switch NMOS transistor M21, a third switch NMOS transistor, a PMOS transistor M20: the grid inputs the enabling signal ENB, the source is connected with the voltage VDD, the drain is connected with the drain of the NMOS tube M19 and the grid of the NMOS tube M21; the source electrode of the NMOS tube M19 is connected with VSS; the drain electrode of the NMOS tube M21 is grounded, when the loop current of the PTAT current source is not established, the grid voltage of the NMOS tube M19 is low, the PMOS tube M20 is conducted after an ENB signal is input, the grid electrode of the NMOS tube M21 is pulled up by the PMOS tube M20, the NMOS tube M21 is conducted, the loop current of the PTAT current source is established, after the loop current is established, the NMOS tube M19 is started, and the NMOS tube M19 has stronger capacity than the PMOS tube M20, so that the NMOS tube M21 is closed, and the normal work of the PTAT current source is not influenced by the starting circuit.

Further, a low voltage PTAT current source, comprising: PMOS pipe M15, PMOS pipe M16, NMOS pipe M17, NMOS pipe M18, resistance R1, PMOS pipe M15: the source electrode is connected with a voltage VDD, the grid electrode is connected with the drain electrode of the NMOS tube M21, and the drain electrode is connected with the drain electrode of the NMOS tube M18; NMOS transistor M18: the drain electrode is connected with the grid electrode and is connected with the grid electrode of the NMOS tube M19, and the source electrode is connected with VSS; PMOS tube M16: the source electrode is connected with a voltage VDD, the grid electrode is connected with the drain electrode of the NMOS tube M21, the drain electrode is connected with the grid electrode and is also connected with the drain electrode of the NMOS tube M17; NMOS transistor M17: the grid electrode is connected with the grid electrode of the NMOS tube M19, the drain electrode is connected with one end of the resistor R1, the other end of the resistor R1 is connected with VSS, the PMOS tube M15 and the PMOS tube M16 form a current mirror, when the PMOS tube M20 pulls up the grid electrode of the NMOS tube M21, the NMOS tube M21 is conducted, the grid electrode of the current mirror is pulled down, and therefore the PMOS tube M15 and the PMOS tube M16 are conducted, and loop current of the PATA current source is established.

Further, the bias circuit comprises a PMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, a PMOS transistor M10, a PMOS transistor M10: the source electrode is connected with a voltage VDD, the grid electrode is connected with the grid electrode of the PMOS tube M16, and the drain electrode is connected with the drain electrode of the NMOS tube M9; NMOS transistor M9: the grid electrode is connected with the drain electrode, and the source electrode is connected with VSS; PMOS tube M7: the source electrode is connected with a voltage VDD, the grid electrode is connected with the source electrode, and the source electrode is connected with the drain electrode of the NMOS tube M8; NMOS transistor M8: the gate of the NMOS transistor M9 is connected to the gate and the source is connected to VSS, and the bias current is obtained by proportional replication from a PTAT current source.

Further, the bias circuit is still connected with the charge-discharge branch road, and the charge-discharge branch road contains: PMOS pipe M5, NMOS pipe M6 and charge-discharge capacitor C1, PMOS pipe M5: the source electrode is connected with VDD, and the grid electrode is connected with the grid electrode of the PMOS transistor M7; NMOS tube M6: the grid is connected with the grid of the NMOS tube M8, and the source is connected with VSS; charging and discharging capacitor C1: and the output current of the drain electrode of the PMOS tube M5 or the drain electrode of the NMOS tube M6 is received, the PMOS tube M5 and the NMOS tube M6 obtain bias current from a bias circuit, and the current flows through the charge and discharge capacitor C1 after being conducted, so that the charge or discharge of the charge and discharge capacitor C1 is realized.

Further, the oscillator circuit includes: odd number of phase inverters of establishing ties, feedback branch circuit I, feedback branch circuit II and feedback branch circuit III, feedback branch circuit III is connected to output OSC of odd number of phase inverters of establishing ties, the output of odd number of phase inverters of establishing ties connects the VI of feedback branch circuit II and feedback branch circuit I behind the phase inverter INV4 in series, feedback branch circuit I still is connected with charge-discharge capacitor C1, feedback branch circuit I, the common output of feedback branch circuit III connects at the input of odd number of phase inverters of establishing ties, charge-discharge circuit cooperation biasing circuit, can guarantee that the oscillator circuit under different operating voltage obtains relatively stable current, thereby obtain stable oscillation period and duty cycle.

Further, in the oscillator circuit, the feedback branch i includes: PMOS pipe M11, PMOS pipe M13, NMOS pipe M14, NMOS pipe M12, PMOS pipe M11: the source electrode is connected with VDD, the grid electrode is connected with the grid electrode of the NMOS transistor M12 and is connected with the charge-discharge capacitor C1, and the drain electrode is connected with the source electrode of the PMOS transistor M13; PMOS tube M13: the grid electrode of the NMOS tube M14 is connected with the grid electrode of the inverter INV4, the drain electrode of the NMOS tube M14 is connected with the drain electrode of the NMOS tube M14, and the output end of the feedback branch circuit III is connected with the drain electrode of the NMOS tube M14; NMOS transistor M14: the source electrode is connected with the drain electrode of the NMOS tube M12; NMOS transistor M12: the source is connected to VSS.

Further, the feedback branch ii includes: PMOS transistor M1, NMOS transistor M2, PMOS transistor M1: the source electrode is connected with the drain electrode of the PMOS tube M5, the grid electrode is connected with the grid electrode of the NMOS tube M2 and is connected with the output end of the inverter INV4, and the drain electrode is connected with the drain electrode of the NMOS tube M2 and is connected with the charge-discharge capacitor C1; NMOS transistor M2: the source is connected with the drain of the NMOS transistor M6.

Further, the feedback branch iii comprises: PMOS transistor M3, NMOS transistor M4, PMOS transistor M3: the source electrode is connected with the drain electrode of the PMOS tube M5, the grid electrode is connected with the grid electrode of the NMOS tube M4, the drain electrode is connected with the drain electrode of the NMOS tube M4, the drain electrode is also connected with the input ends of odd number of inverters connected in series, and the drain electrode is also connected with the drain electrode of the PMOS tube M13 and the drain electrode of the NMOS tube M14; NMOS tube M4: the grid electrode is connected with the output end OSC of the odd number of inverters in series, and the source electrode is connected with the drain electrode of the NMOS tube M6.

Further, an odd number of the inverters connected in series includes: the inverter comprises an inverter INV1, an inverter INV2 and an inverter INV3, wherein the input end of the inverter INV1 is connected with the drain of the NMOS tube M4, the output end of the inverter INV1 is connected with the Schmidt SMT1, the output end of the Schmidt SMT1 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end OSC of the inverter INV3 is connected with the gate of the NMOS tube M4 and the input end of the inverter INV 4.

Referring to FIG. 2, in the period T1, assuming that the signal line VI is initially 0 and the OSC is initially 1, the common output terminal of the PMOS transistor M3 and the NMOS transistor M4 is weaker than the transistors M13 and M14VOStill following the control of VI, which can be regarded as 1, at this time, the PMOS transistor M1 is turned on, the NMOS transistor M2 and the PMOS transistor M3 are turned off, the capacitor C1 is charged by the current provided by the PMOS transistor M5, so that the VCHG level gradually increases, with the increase of VCHG, the effects of the PMOS transistor M3 and the NMOS transistor M4 are gradually weakened, when VCHG increases to a certain point, VO is controlled by OSC, and is equivalent to 0, and thereafter, the signal line VO is shaped by schmidt SMT1, the inverter INV1, the inverter INV2, and the inverter INV3, and the output OSC changes to 0, VI is 1, and enters the T2 time period.

In the period T2, OSC is 0, VI is 1, at this time, PMOS transistor M1 and NMOS transistor M4 are turned off, PMOS transistor M2 is turned on, capacitor C1 discharges through the current path provided by NMOS transistor M6, and VCHG voltage gradually decreases, and similarly, as VCHG level gradually decreases, the effects of PMOS transistor M13 and NMOS transistor M14 are still gradually weakened (since VI has become reverse level with respect to the period T1 at this time), VO signal gradually changes to be controlled by OSC, and when VCHG decreases to the original low level, VO is equivalent to 1 instead, and pulls OSC back to high level, thereby entering the next oscillation cycle.

The technical principle of the present invention is described above with reference to specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without any inventive effort, which would fall within the scope of the claims of the present invention.

Claims (10)

1. A low operating voltage ring oscillator with a self-starting bias circuit, comprising: the current source, the bias circuit and the oscillator circuit, wherein the output end of the current source is connected with the bias circuit, and the bias circuit is connected with the oscillator circuit; it is characterized in that the current source adopts a self-starting power supply circuit, comprising: the starting circuit inputs an enable signal ENB, the output end of the starting circuit is connected with the low-voltage PTAT current source and used for starting the low-voltage PTAT current source, and the output end of the low-voltage PTAT current source is connected with the bias circuit.

2. The low operating voltage ring oscillator with self-starting bias circuit of claim 1, wherein: the start-up circuit includes: the low-voltage PTAT current source comprises a first switch, a second switch and a third switch, wherein the first switch inputs an enable signal ENB, the output end of the first switch is connected with the signal input end of the second switch, and the second switch is turned on to enable the low-voltage PTAT current source to establish loop current; the third switch inputs the loop current, and the third switch is used for controlling the closing of the second switch.

3. The low operating voltage ring oscillator with self-starting bias circuit of claim 2, wherein: the start-up circuit includes: a first switch PMOS transistor M20, a second switch NMOS transistor M21, a third switch NMOS transistor, wherein the PMOS transistor M20: the grid inputs the enabling signal ENB, the source is connected with the voltage VDD, the drain is connected with the drain of the NMOS tube M19 and the grid of the NMOS tube M21; the source electrode of the NMOS tube M19 is connected with VSS; the drain of the NMOS transistor M21 is grounded.

4. The low operating voltage ring oscillator with self-starting bias circuit of claim 3, wherein: the low voltage PTAT current source includes: PMOS pipe M15, PMOS pipe M16, NMOS pipe M17, NMOS pipe M18, resistance R1, PMOS pipe M15: the source electrode is connected with a voltage VDD, the grid electrode is connected with the drain electrode of the NMOS tube M21, and the drain electrode is connected with the drain electrode of the NMOS tube M18; the NMOS tube M18: the drain electrode is connected with the grid electrode and is connected with the grid electrode of the NMOS tube M19, and the source electrode is connected with VSS; the PMOS tube M16: the source electrode is connected with a voltage VDD, the grid electrode is connected with the drain electrode of the NMOS tube M21, the drain electrode is connected with the grid electrode and is also connected with the drain electrode of the NMOS tube M17; the NMOS tube M17: the grid electrode of the NMOS tube M19 is connected with the grid electrode and the drain electrode of the NMOS tube M19 is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with VSS.

5. The low operating voltage ring oscillator with self-starting bias circuit of claim 4, wherein: the bias circuit comprises a PMOS tube M7, an NMOS tube M8, an NMOS tube M9 and a PMOS tube M10, wherein the PMOS tube M10: the source electrode is connected with a voltage VDD, the grid electrode is connected with the grid electrode of the PMOS tube M16, and the drain electrode is connected with the drain electrode of the NMOS tube M9; the NMOS tube M9: the grid electrode is connected with the drain electrode, and the source electrode is connected with VSS;

the PMOS tube M7: the source electrode is connected with a voltage VDD, the grid electrode is connected with the source electrode, and the source electrode is connected with the drain electrode of the NMOS tube M8; the NMOS tube M8: the grid is connected with the grid of the NMOS tube M9, and the source is connected with VSS.

6. The low operating voltage ring oscillator with self-starting bias circuit of claim 5, wherein: the bias circuit is still connected with the charge-discharge branch road, the charge-discharge branch road contains: PMOS transistor M5, NMOS transistor M6 and charge-discharge capacitor C1, PMOS transistor M5: the source electrode is connected with VDD, and the grid electrode is connected with the grid electrode of the PMOS transistor M7; the NMOS tube M6: the grid is connected with the grid of the NMOS tube M8, and the source is connected with VSS; the charging and discharging capacitor C1: and receiving the output current of the drain electrode of the PMOS tube M5 or the drain electrode of the NMOS tube M6.

7. The low operating voltage ring oscillator with self-starting bias circuit of claim 6, wherein: the oscillator circuit includes: the output end OSC of the odd number of series-connected inverters is connected with the feedback branch circuit III, the output end of the odd number of series-connected inverters is connected with the VI of the feedback branch circuit II and the VI of the feedback branch circuit I after being connected with the inverter INV4 in series, the feedback branch circuit I is further connected with the charge-discharge capacitor C1, and the common output end of the feedback branch circuit I and the feedback branch circuit III is connected with the input end of the odd number of series-connected inverters.

8. The low operating voltage ring oscillator with self-starting bias circuit of claim 7, wherein: the feedback branch I comprises: PMOS pipe M11, PMOS pipe M13, NMOS pipe M14, NMOS pipe M12, PMOS pipe M11: the source electrode is connected with VDD, the grid electrode is connected with the grid electrode of the NMOS tube M12 and is connected with the charge-discharge capacitor C1, and the drain electrode is connected with the source electrode of the PMOS tube M13; the PMOS tube M13: the grid electrode of the NMOS tube M14 is connected with the grid electrode of the NMOS tube M4 and is connected with the output end of the inverter INV4, and the drain electrode of the NMOS tube M14 is connected with the drain electrode of the NMOS tube M14 and is connected with the output end of the feedback branch III; the NMOS tube M14: the source electrode is connected with the drain electrode of the NMOS tube M12; the NMOS tube M12: the source is connected to VSS.

9. The low operating voltage ring oscillator with self-starting bias circuit of claim 8, wherein: the feedback branch circuit II comprises: PMOS pipe M1, NMOS pipe M2, PMOS pipe M1: the source electrode is connected with the drain electrode of the PMOS tube M5, the grid electrode is connected with the grid electrode of the NMOS tube M2 and is connected with the output end of the inverter INV4, and the drain electrode is connected with the drain electrode of the NMOS tube M2 and is connected with the charge-discharge capacitor C1; the NMOS tube M2: the source is connected with the drain of the NMOS transistor M6.

10. The low operating voltage ring oscillator with self-starting bias circuit of claim 9, wherein: the feedback branch III comprises: PMOS pipe M3, NMOS pipe M4, PMOS pipe M3: the source electrode is connected with the drain electrode of the PMOS tube M5, the grid electrode is connected with the grid electrode of the NMOS tube M4, the drain electrode is connected with the drain electrode of the NMOS tube M4, the drain electrode is also connected with the input ends of odd number of inverters which are connected in series, and the drain electrode is also connected with the drain electrode of the PMOS tube M13 and the drain electrode of the NMOS tube M14; the NMOS tube M4: the grid electrode is connected with the output end OSC of the odd number of inverters in series, and the source electrode is connected with the drain electrode of the NMOS tube M6.

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