CN210780703U

CN210780703U - Sawtooth wave generating circuit and buck-boost converter

Info

Publication number: CN210780703U
Application number: CN201921846738.4U
Authority: CN
Inventors: 张亮; 江力
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2019-10-30
Filing date: 2019-10-30
Publication date: 2020-06-16
Anticipated expiration: 2029-10-30

Abstract

The utility model discloses a sawtooth wave generating circuit, which comprises a current mirror module, a clock generating module, a voltage-reducing sawtooth wave module and a voltage-boosting sawtooth wave module, wherein the clock generating module comprises a first charging and discharging unit and a comparator unit, the voltage-reducing sawtooth wave module comprises a second charging and discharging unit, and the voltage-boosting sawtooth wave module comprises a third charging and discharging unit, a fourth charging and discharging unit and a control unit; the comparator unit is respectively connected with the control unit and the first to second charging and discharging units; the control unit is respectively connected with the third to fourth charging and discharging units. Correspondingly, the utility model also discloses a buck-boost converter. The embodiment of the utility model provides a sawtooth wave amplitude is nimble to be set up to improve the interference killing feature of buck-boost converter, can realize that the peak value of buck sawtooth wave equals with the valley value of boost sawtooth wave, thereby guarantee the smooth switch-over of buck-boost converter mode of operation, thereby improve the efficiency of buck-boost converter and output voltage's stability.

Description

Sawtooth wave generating circuit and buck-boost converter

Technical Field

The utility model relates to the field of electronic technology, especially, relate to a sawtooth wave produces circuit and step-up and step-down converter.

Background

The BUCK-BOOST converter, also known as a BUCK-BOOST transformer, is a dc converter whose output voltage may be higher, lower or equal to the input voltage. Because the dual-mode control mode of the BUCK-BOOST converter works in the BUCK mode or the BOOST mode in one clock cycle, the situation that the BUCK mode and the BOOST mode work simultaneously does not occur, namely, the situation that a BUCK switching tube and a BOOST switching tube are switched simultaneously does not exist, and the efficiency is higher than that of other control modes, the current BUCK-BOOST converter generally adopts dual-mode control.

The dual-mode control mode of the BUCK-BOOST converter generally has the following two control strategies: firstly, a double modulation signal-single sawtooth wave control strategy is adopted; second, a single modulation signal-dual sawtooth control strategy is employed. The BUCK switching tube and the BOOST switching tube of the BUCK-BOOST converter adopting the single modulation signal-double sawtooth wave control strategy have the same modulation signal and are both from the output of the same error amplifier, and the sawtooth wave signal of the BOOST switching tube is obtained by superposing the sawtooth wave signal of the BUCK switching tube with a direct current bias voltage, so that only one sawtooth wave is in alternating load with the modulation signal at any time, namely only one switching tube is controlled.

Fig. 1 shows a buck sawtooth wave generating circuit provided in the prior art, a current source 7202 provides a charging current I1 to charge a capacitor C11 according to an input voltage Vin, a control circuit 7204 includes a switch SW1 connected in parallel with the capacitor C11, a frequency Clk switches over the switch SW1 to control charging and discharging of the capacitor C11, when a clock Clk is at a low level, the capacitor C11 is charged through the current I1, the voltage of the SAWbuck gradually rises until the level of the Clk is at a high level, the capacitor is rapidly discharged, the voltage of the SAWbuck recovers to Vbe, and then the capacitor is charged again when the level of the Clk is at a low level, the previous process is repeated to generate a buck sawtooth wave signal SAWbuck, and a limiting circuit 7206 is used to fix a valley value of the buck sawtooth wave signal SAWbuck at Vbe. Fig. 2 shows a boost sawtooth wave generating circuit provided by the prior art, a current source 7210 provides a charging current I2 to charge a capacitor C22 according to an input voltage Vin, a control circuit 7212 includes a switch SW2 connected in parallel with the capacitor C22, a frequency Clk switches over the switch SW2 to control charging and discharging of the capacitor C22, when a clock Clk is at a low level, the capacitor C22 is charged through the current I2, the SAWboost voltage gradually rises until the Clk level is at a high level, the capacitor C22 is rapidly discharged, the SAWboost voltage returns to 2Vbe, and then the charging is performed again when the Clk is at a low level, the previous process is repeated to generate a boost sawtooth wave signal SAWboost, and a limiting circuit 7214 is used to fix the valley value of the charging voltage V1 at 2 Vbe. On one hand, the amplitude of the generated voltage reduction sawtooth wave and the amplitude of the generated voltage boosting sawtooth wave are Vbe, so that the noise resistance is poor; on the other hand, to make the amplitudes of the two sawtooth waves the same and equal to Vbe, and ensure that the peak value of the SAWbuck is equal to the valley value of the SAWboost, to implement smooth switching, the sawtooth waves need an accurate rising Vbe voltage within the low level time of the clock Clk, which is difficult to implement in practice. When the two sawtooth waves are intersected, the situation that two modes work simultaneously appears in one clock period, and two switching tubes are switched once, so that the switching loss is large, and the efficiency is low; when the double-sawtooth phase is separated, the switching time of the BUCK mode and the BOOST mode is longer, the output voltage greatly oscillates, and the output voltage is unstable.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a sawtooth wave generating circuit and step-up and step-down voltage converter are provided, can realize that sawtooth wave range sets up in a flexible way to improve the interference killing feature of step-up and step-down voltage converter, can ensure that the peak value of step-down sawtooth wave equals with the valley value of the sawtooth wave that steps up, realize the level and smooth switching of step-up and step-down voltage converter mode of operation, thereby improve the efficiency of step-up and step-down voltage converter and output voltage's stability.

In order to solve the technical problem, the utility model provides a sawtooth wave generating circuit, including current mirror module, clock generation module, step-down sawtooth wave module and step-up sawtooth wave module, the clock generation module includes first charge-discharge unit and comparator unit, step-down sawtooth wave module includes second charge-discharge unit, step-up sawtooth wave module includes third charge-discharge unit, fourth charge-discharge unit and the control unit; the first to fourth charge and discharge units have the same circuit structure;

the current mirror module is respectively connected with the first to fourth charging and discharging units and is used for providing charging current for the first to fourth charging and discharging units so as to charge the first to fourth charging and discharging units;

the first charging and discharging unit is used for generating a sawtooth wave with a target amplitude value according to the charging current; the comparator unit is respectively connected with the first charging and discharging unit, the control unit and the second charging and discharging unit, and is used for generating a clock signal according to the sawtooth wave with the target amplitude value and sending the clock signal to the control unit and the second charging and discharging unit;

the second charging and discharging unit is used for charging and discharging according to the clock signal and outputting charging voltage;

the control unit is respectively connected with the third charge-discharge unit and the fourth charge-discharge unit and used for generating a control signal according to the clock signal so as to control the third charge-discharge unit and the fourth charge-discharge unit to discharge for one clock cycle every time the third charge-discharge unit and the fourth charge-discharge unit are charged, so as to control the third charge-discharge unit and the fourth charge-discharge unit to discharge when the third charge-discharge unit and the fourth charge-discharge unit are charged, and to control the third charge-discharge unit and the fourth charge-discharge unit to output charging voltage when the third charge-discharge unit and the fourth charge-discharge.

Furthermore, the first to fourth charging and discharging units each include a control signal input terminal, a ground terminal, a charging terminal, and a charging voltage output terminal, and the comparator unit includes a voltage signal input terminal, a reference signal input terminal, and a clock signal output terminal;

the charging end of the first charging and discharging unit is connected with the current mirror module, the charging voltage output end of the first charging and discharging unit is connected with the voltage signal input end of the comparator unit, the reference signal input end of the comparator unit is connected to a reference voltage source, and the clock signal output end of the comparator unit is connected with the control signal input end of the first charging and discharging unit.

Further, the comparator unit includes a comparator and an inverter;

the non-inverting input end of the comparator is connected with the reference signal input end, the inverting input end of the comparator is connected with the voltage signal input end, the output end of the comparator is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the clock signal output end.

Furthermore, the step-down sawtooth wave module further comprises a step-down sawtooth wave output end, the charging end of the second charging and discharging unit is connected with the current mirror module, the control signal input end of the second charging and discharging unit is connected with the clock signal output end of the comparator unit, and the charging voltage output end of the second charging and discharging unit is connected with the step-down sawtooth wave output end.

Furthermore, the boost sawtooth wave module further comprises a boost sawtooth wave output end, the control unit comprises a logic control subunit, a charge-discharge switching subunit, a first switch tube and a second switch tube, the logic control subunit comprises a clock signal input end, a first charge-discharge control output end, a second charge-discharge control output end, a first switch control output end and a second switch control output end, and the charge-discharge switching subunit comprises a current end, a first current output end, a second current output end, a first switching control input end, a second switching control input end and a discharge end;

the current end is connected with the current mirror module, the charging end of the third charging and discharging unit is connected with the first current output end, the charging end of the fourth charging and discharging unit is connected with the second current output end, the first charging and discharging control output end is connected with the control signal input end of the third charging and discharging unit, the second charging and discharging control output end is connected with the control signal input end of the fourth charging and discharging unit, the charging voltage output end of the third charging and discharging unit is connected with the first end of the first switch tube, the control end of the first switch tube is respectively connected with the first switch control output end and the first switching control input end, the charging voltage output end of the fourth charging and discharging unit is connected with the first end of the second switch tube, and the control end of the second switch tube is respectively connected with the second switch control output end and the second switching control input end, the second end of the first switch tube and the second end of the second switch tube are connected with the boost sawtooth wave output end, and the clock signal input end is connected with the clock signal output end of the comparator.

Further, the charge-discharge switching subunit further comprises a third switching tube, a fourth switching tube, a fifth switching tube and a sixth switching tube;

the first end of third switch tube with the first end of fourth switch tube with the electric current end is connected, the control end of third switch tube with the control end of fifth switch tube with first switching control input end is connected, the second end of third switch tube with the first end of fifth switch tube with first current output end is connected, the control end of fourth switch tube with the control end of sixth switch tube with second switching control input end is connected, the second end of fourth switch tube with the first end of sixth switch tube with second current output end is connected, the second end of fifth switch tube with the second end of sixth switch tube with discharge end is connected.

Furthermore, the logic control subunit further comprises a D flip-flop, a first delayer, a second delayer, a first inverter, a second inverter, a first and gate and a second and gate;

the clock input end of the D trigger is connected with the clock signal input end, the data input end of the D trigger is connected with the second output end of the D trigger, the first output end of the D trigger is respectively connected with the first switch control output end, the input end of the first delayer and the second input end of the first AND gate, the output end of the first delayer is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the first input end of the first AND gate, the output end of the first AND gate is connected with the first charge-discharge control output end, the second output end of the D trigger is respectively connected with the second switch control output end, the input end of the second delayer and the first input end of the second AND gate, and the output end of the second delayer is connected with the input end of the second phase inverter, the output end of the second inverter is connected with the second input end of the second AND gate, and the output end of the second AND gate is connected with the second charge-discharge control output end.

Furthermore, the first to fourth charge and discharge units also comprise discharge switch tubes and capacitors;

the first end of the discharge switch tube is connected with the charging end and the first end of the capacitor respectively, the first end of the capacitor is connected with the charging voltage output end, the control end of the discharge switch tube is connected with the control signal input end, and the second end of the discharge switch tube and the second end of the capacitor are connected with the grounding end.

Further, the current mirror module comprises a current input end, a seventh switching tube, an eighth switching tube, a ninth switching tube, a tenth switching tube, an eleventh switching tube, a twelfth switching tube and a thirteenth switching tube;

the current input end is connected to a current source, the second end of the seventh switching tube is connected to the current input end, the control ends of the seventh to eleventh switching tubes are all connected to the second end of the seventh switching tube, the first ends of the seventh to eleventh switching tubes are all connected to a power supply, the second end of the eighth switching tube is connected to the charging end of the first charging and discharging unit, the second end of the ninth switching tube is respectively connected to the first end and the control end of the twelfth switching tube, the second end of the twelfth switching tube is grounded, the control end of the twelfth switching tube is connected to the control end of the thirteenth switching tube, the second end of the thirteenth switching tube is grounded, the first end of the thirteenth switching tube is connected to the discharging end of the charging and discharging switching sub-unit, and the second end of the tenth switching tube is connected to the charging end of the second charging and discharging unit, and the second end of the eleventh switching tube is connected with the current end of the charge-discharge switching subunit.

Correspondingly, the utility model also provides a step-up and step-down converter, step-up and step-down converter includes as before sawtooth wave produces the circuit.

The utility model provides a sawtooth wave generating circuit and step-up and step-down converter, current mirror module provide charging current to first to fourth charge-discharge unit, first charge-discharge unit according to charging current produces the sawtooth wave that has the target amplitude value, comparator unit according to the sawtooth wave that has the target amplitude value produces clock signal, second charge-discharge unit according to clock signal charges and discharges, and output charging voltage; the control unit generates a control signal according to the clock signal to control the third charge-discharge unit and the fourth charge-discharge unit to discharge for one clock cycle every time the third charge-discharge unit and the fourth charge-discharge unit are charged for one clock cycle, so as to control the third charge-discharge unit and the fourth charge-discharge unit to discharge when the third charge-discharge unit and the fourth charge-discharge unit are charged for one clock cycle, and to control the third charge-discharge unit and the fourth charge-discharge unit to output charging voltage when the third charge-discharge unit and the fourth. The first to fourth charging and discharging units have the same circuit structure and are controlled by the same clock signal, and the charging voltage output by the second charging and discharging unit is also a buck sawtooth wave with a target amplitude value; the third charge-discharge unit and the fourth charge-discharge unit discharge when the other charge, that is, the third charge-discharge unit and the fourth charge-discharge unit alternately charge and discharge, and the third charge-discharge unit and the fourth charge-discharge unit output charging voltages when discharging, and when the third charge-discharge unit and the fourth charge-discharge unit are charged for one clock cycle with a current 2 times as much as the charging current of the second charge-discharge unit, and then are rapidly discharged for one clock cycle with the same current as the charging current of the second charge-discharge unit, a boost sawtooth wave with a valley value equal to the peak value of the buck sawtooth wave and a target amplitude value can be generated. The target amplitude value can be flexibly set by changing a reference voltage source of the comparator unit, so that the anti-interference capability of the buck-boost converter is improved; the peak value of the buck sawtooth wave can be equal to the valley value of the boost sawtooth wave, smooth switching of the working mode of the buck-boost converter is guaranteed, and therefore efficiency of the buck-boost converter and stability of output voltage are improved.

Drawings

FIG. 1 is a schematic circuit diagram of a buck sawtooth generation circuit provided in the prior art;

FIG. 2 is a schematic circuit diagram of a boost sawtooth generation circuit provided in the prior art;

FIG. 3 is a block diagram of a sawtooth generation circuit provided by the present invention;

fig. 4 is a schematic circuit diagram of an embodiment of a sawtooth wave generating circuit provided by the present invention;

FIG. 5 is a schematic circuit diagram of an embodiment of a logic control subunit of a sawtooth generation circuit;

fig. 6 is a timing diagram of logic control and a waveform diagram of a sawtooth waveform of the logic control subunit of the sawtooth wave generating circuit according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. According to the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without any creative work belong to the protection scope of the present invention.

Referring to fig. 3, it is a block diagram of the sawtooth wave generating circuit provided by the present invention.

The embodiment of the utility model provides a sawtooth wave produces circuit, including current mirror module 1, clock generation module 2, step-down sawtooth wave module 3 and boost sawtooth wave module 4, clock generation module 2 includes first charge-discharge unit 21 and comparator unit 22, and step-down sawtooth wave module 3 includes second charge-discharge unit 31, and boost sawtooth wave module 4 includes third charge-discharge unit 41, fourth charge-discharge unit 42 and the control unit; wherein the first to fourth charge and discharge units (21,31,41,42) have the same circuit structure;

the current mirror module 1 is respectively connected with the first to fourth charge and discharge units (21,31,41,42) and is used for providing charging current to the first to fourth charge and discharge units (21,31,41,42) so as to charge the first to fourth charge and discharge units (21,31,41, 42);

a first charge and discharge unit 21 for generating a sawtooth wave having a target amplitude value according to the charging current; the comparator unit 22 is connected to the first charge and discharge unit 21, the second charge and discharge unit 31, and the control unit, respectively, and is configured to generate a clock signal according to a sawtooth wave having a target amplitude value, and send the clock signal to the control unit and the second charge and discharge unit 31;

the second charge and discharge unit 31 performs charge and discharge according to the clock signal and outputs a charge voltage;

the control unit is respectively connected to the third charge and discharge unit 41 and the fourth charge and discharge unit 42, and configured to generate a control signal according to the clock signal, so as to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge for one clock cycle every time the third charge and discharge unit 41 and the fourth charge and discharge unit 42 are charged, so as to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge when the third charge and discharge unit 41 and the fourth charge and discharge unit 42 output a charging voltage when the third charge and discharge unit 41 and the fourth charge and discharge unit 42 are charged.

In specific implementation, the current mirror module 1 supplies a charging current to the first to fourth charging and discharging units (21,31,41,42), the first charging and discharging unit 21 generates a sawtooth wave having a target amplitude value according to the charging current Ic0, the comparator unit 22 generates a clock signal according to the sawtooth wave having the target amplitude value and transmits the clock signal to the control unit and the second charging and discharging unit 31, and the second charging and discharging unit 31 performs charging and discharging according to the clock signal and outputs a charging voltage; the control unit generates a control signal according to the clock signal to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge for one clock cycle every time the third charge and discharge unit 41 and the fourth charge and discharge unit 42 are charged, so as to control the third charge and discharge unit 41 and the fourth charge and discharge unit 42 to discharge when the third charge and discharge unit 41 and the fourth charge and discharge unit 42 output the charging voltage when the third charge and discharge unit 41 and the fourth charge and discharge unit 42 are charged. Since the first to fourth charging and discharging units (21,31,41,42) have the same circuit configuration and are controlled by the same clock signal, when the charging current 2Ic0 is 2Ic1 is Ic2 is 2Ic3, the charging voltage output by the second charging and discharging unit 31 is also a buck sawtooth wave having a target amplitude value. The third charge and discharge unit 41 and the fourth charge and discharge unit 42 are discharged when the other charge, that is, the third charge and discharge unit 41 and the fourth charge and discharge unit 42 are alternately charged and discharged, that is, when the third charge and discharge unit 41 is charged with the charge current Ic2, the fourth charge and discharge unit 42 is discharged with the charge current Ic3 and outputs the charge voltage, and when the third charge and discharge unit 41 is charged for one clock cycle, the third charge and discharge unit 41 and the fourth charge and discharge unit 42 are rapidly discharged to 0 and then start to be charged with the charge current Ic 2. Thereby, a step-up sawtooth wave having a valley value equal to the peak value of the step-down sawtooth wave and having a target amplitude value can be generated. Because the boost sawtooth wave and the buck sawtooth wave are generated under the control of the same clock signal, the phase shift of the two sawtooth wave signals can be ensured to be the same. The target amplitude value can be flexibly set by changing the reference voltage source of the comparator unit 22, so that the anti-interference capability of the buck-boost converter is improved; the peak value of the buck sawtooth wave can be equal to the valley value of the boost sawtooth wave, smooth switching of the working mode of the buck-boost converter is guaranteed, and therefore efficiency of the buck-boost converter and stability of output voltage are improved.

Further, the first to fourth charge and discharge units (21,31,41,42) each include a control signal input terminal (c1, c2, c3, c4), a ground terminal (b1, b2, b3, b4), a charge terminal (a1, a2, a3, a4), and a charge voltage output terminal (d1, d2, d3, d4), and the comparator unit 22 includes a voltage signal input terminal VI, a reference signal input terminal VR, and a clock signal output terminal CLK;

the charging terminal a1 of the first charge and discharge unit 21 is connected to the current mirror module 1, the charging voltage output terminal d1 of the first charge and discharge unit 21 is connected to the voltage signal input terminal VI of the comparator unit 22, the reference signal input terminal VR of the comparator unit 22 is connected to the reference voltage source Vsaw, and the clock signal output terminal CLK of the comparator unit 22 is connected to the control signal input terminal c1 of the first charge and discharge unit 21.

In practical implementation, the current mirror module 1 provides the charging current Ic0 to the charging terminal a1 of the first charging/discharging unit 21, the first charging/discharging unit 21 is charged, when the voltage output from the charging voltage output terminal d1 of the first charging and discharging unit 21 is greater than the reference voltage Vsaw input from the reference signal input terminal VR of the comparator unit 22, the comparator unit 22 turns over, outputs a clock signal to control the first charging and discharging unit 21 to discharge rapidly, when the voltage output by the charging voltage output terminal d1 of the first charging and discharging unit 21 is less than the reference voltage Vsaw input by the reference signal input terminal VR of the comparator unit 22, the comparator unit 22 flips again, and outputs a clock signal to control the first charging and discharging unit 21 to charge, and repeats the above processes, the first charging and discharging unit 21 outputs a sawtooth wave with an amplitude value equal to Vsaw, and the comparator unit 22 outputs a clock signal through the clock signal output terminal CLK.

It should be noted that the sawtooth wave signal generated by the charging and discharging process of the first charging and discharging unit 21 is compared with a reference voltage Vsaw to generate a clock signal, so that the voltage boosting sawtooth wave and the voltage reducing sawtooth wave amplitude value of the embodiment of the present invention are the reference voltage Vsaw of the comparator unit, and therefore the voltage boosting sawtooth wave and the voltage reducing sawtooth wave amplitude can be flexibly set.

Referring to fig. 4, a schematic circuit diagram of an embodiment of a sawtooth wave generating circuit according to the present invention is shown. As shown in fig. 3 and 4, the comparator unit 22 includes a comparator U1 and an inverter U2;

the non-inverting input terminal of the comparator U1 is connected to the reference signal input terminal VR, the inverting input terminal of the comparator U1 is connected to the voltage signal input terminal VI, the output terminal of the comparator U1 is connected to the input terminal of the inverter U2, and the output terminal of the inverter U2 is connected to the clock signal output terminal CLK.

Further, each of the first to fourth charge and discharge units (21,31,41,42) further comprises a discharge switching tube (MN1, MN3, MN7, MN8) and a capacitor (CO, C1, C2, C3);

taking the first charge/discharge unit 21 as an example, the first terminal of the discharge switch MN1 is connected to the charging terminal a1 and the first terminal of the capacitor CO, the first terminal of the capacitor CO is connected to the charging voltage output terminal d1, the control terminal of the discharge switch MN1 is connected to the control signal input terminal C1, and the second terminal of the discharge switch MN1 and the second terminal of the capacitor C0 are connected to the ground terminal b 1.

It should be noted that, the clock generation module 2 composed of the first charging and discharging unit 21 and the comparator unit 22 uses the relaxation oscillator principle, when the clock signal output by the output end of the inverter U2 is at a low level, the capacitor C0 is charged through the current Ic0, the voltage at both ends of the capacitor CO starts to rise, when the voltage rises to be equal to Vsaw, the voltage at the output end of the inverter U2 is inverted to a high level, then the switching tube MN1 is turned on to rapidly discharge the capacitor CO, when the voltage of the capacitor CO drops to be lower than Vsaw, the voltage at the output end of the inverter U2 is inverted to a low level again, the foregoing processes are repeated, so as to form the clock signal, and the high level time of the voltage at the output end of the inverter U2 is determined by the delay of the comparator U1 and the time when the voltage on the capacitor C0 drops to be lower than vs. The capacitances of the second charge and discharge unit 31 and the first charge and discharge unit 21 are matched, and the currents are also matched, that is, C0 is C1, Ic0 is Ic1, and the clock signals are also matched, so that the voltage output by the second charge and discharge unit 31 is a sawtooth wave with an amplitude value equal to Vsaw.

Preferably, the discharge switch tubes (MN1, MN3, MN7, MN8) are N-channel MOS tubes, drains of the N-channel MOS tubes are first ends of the discharge switch tubes (MN1, MN3, MN7, MN8), sources of the N-channel MOS tubes are second ends of the discharge switch tubes (MN1, MN3, MN7, MN8), and gates of the N-channel MOS tubes are control ends of the discharge switch tubes (MN1, MN3, MN7, MN 8).

Further, the buck sawtooth wave module 3 further includes a buck sawtooth wave output terminal Vsaw-buck, the charging terminal a2 of the second charge and discharge unit 3 is connected with the current mirror module 1, the control signal input terminal c2 of the second charge and discharge unit 31 is connected with the clock signal output terminal CLK of the comparator unit 22, and the charging voltage output terminal d2 of the second charge and discharge unit 31 is connected with the buck sawtooth wave output terminal Vsaw-buck.

It should be noted that, the current mirror module 1 provides a charging current Ic1 to the charging terminal a2 of the second charging and discharging unit 31, the second charging and discharging unit 31 charges, the comparator unit 22 outputs a clock signal to the second charging and discharging unit 31 through the clock signal output terminal CLK to control the charging and discharging of the second charging and discharging unit 31, and since the clock signals for controlling the charging and discharging of the second charging and discharging unit 31 and the first charging and discharging unit 31 are the same and the circuit structures of the two are the same, when the current Ic0 is Ic1, the second charging and discharging unit 31 generates a sawtooth wave with the same amplitude value as the first charging and discharging unit 21.

Further, the boost sawtooth wave module 4 further includes a boost sawtooth wave output terminal Vsaw _ boost, the control unit includes a logic control subunit 432, a charge-discharge switching subunit 431, a first switch tube MN5 and a second switch tube MN6, the logic control subunit 432 includes a clock signal input terminal CLK1, a first charge-discharge control output terminal CLK2, a second charge-discharge control output terminal CLK3, a first switch control output terminal CLKC and a second switch control output terminal CLKD, the charge-discharge switching subunit 431 includes a current terminal g, a first current output terminal f1, a second current output terminal f2, a first switch control input terminal 1, a second switch control input terminal ct2 and a discharge terminal e;

the current end g is connected with the current mirror module 1, the charging end a3 of the third charging and discharging unit 41 is connected with the first current output end f1, the charging end a4 of the fourth charging and discharging unit 42 is connected with the second current output end f2, the first charging and discharging control output end CLK2 is connected with the control signal input end c3 of the third charging and discharging unit 41, the second charging and discharging control output end CLK3 is connected with the control signal input end c4 of the fourth charging and discharging unit 42, the charging voltage output end d3 of the third charging and discharging unit 41 is connected with the first end of the first switch tube MN5, the control end of the first switch tube MN5 is respectively connected with the first switch control output end CLKC and the first switching control input end ct1, the charging voltage output end d4 of the fourth charging and discharging unit 42 is connected with the first end of the second switch tube MN6, the control end of the second switch tube MN6 is respectively connected with the second switch control output end CLKD and the second switch control input end ct2, the second terminal of the first switch MN5 and the second terminal of the second switch MN6 are connected to the boost sawtooth output terminal Vsaw _ boost, and the clock signal input terminal CLK1 is connected to the clock signal output terminal CLK of the comparator 22.

In specific implementation, the current mirror module 1 provides a charging current Ic2 to the current terminal g of the charging and discharging switching subunit 432, the logic control subunit 431 outputs a discharging switching signal through the first switch control output terminal CLKC, controls the charging and discharging switching subunit 431 to turn off the current terminal g and the first current output terminal f1 to stop providing the charging current Ic2 for the third charging and discharging unit 41, and turns on the discharging terminal e and the charging terminal a3 of the third charging and discharging unit 41 to provide the discharging current Ic3 for the third charging and discharging unit 41; meanwhile, a charging switching signal is output through the second switch control output terminal CLKD, the current terminal g and the second current output terminal f2 are turned on to provide a charging current Ic2 for the fourth charging and discharging unit 42, the logic control subunit 431 outputs the charging control signal through the second charging and discharging control output terminal CLK3, the fourth charging and discharging unit 41 is charged with the charging current Ic2, the third charging and discharging unit 42 is discharged with the discharging current Ic3, at this time, the first switch tube MN5 is turned on according to the discharging switching signal, and the boost sawtooth wave output terminal Vsaw _ boost outputs the charging voltage of the third charging and discharging unit 41. When the third charge and discharge unit 41 finishes discharging for one clock cycle, the logic control subunit 431 outputs a discharge control signal through the first charge and discharge control output terminal CLK2 to control the third charge and discharge unit 41 to rapidly discharge to 0; the logic control subunit 431 outputs a discharge switching signal through the second switch control output terminal CLKD, controls the charge and discharge switching subunit 431 to turn off the current terminal g and the second current output terminal f2 to stop providing the charging current Ic2 for the fourth charge and discharge unit 42, turn on the discharge terminal e and the charging terminal a4 of the fourth charge and discharge unit 42 to provide the discharging current Ic3 for the fourth charge and discharge unit 42, and simultaneously outputs a charge switching signal through the first switch control output terminal CLKC, turn on the current terminal g and the first current output terminal f1 to provide the charging current Ic2 for the third charge and discharge unit 41, the third charge and discharge unit 41 is charged with the charging current Ic2, the fourth charge and discharge unit 42 is discharged with the discharging current Ic3, at this time, the second switch tube MN6 is turned on according to the discharge switching signal, and the boost sawtooth wave output terminal Vsaw _ boost outputs the charging voltage of the fourth charge and discharge unit 42. Since the capacitances of the first to fourth charge and discharge units (21,31,41,42) are matched, i.e., C0 ═ C1 ═ C2 ═ C3, and the currents are also matched, i.e., 2Ic0 ═ 2Ic1 ═ Ic2 ═ 2Ic3, and are controlled by the same clock signal, the above process is repeated, and a boost sawtooth wave having a target amplitude value with a valley value equal to that of the peak value of the buck sawtooth wave can be output through the boost sawtooth wave output terminal Vsaw-boost.

Preferably, the first switch tube MN5 is an N-channel MOS tube, a drain of the N-channel MOS tube is a first end of the first switch tube MN5, a source of the N-channel MOS tube is a second end of the first switch tube MN5, and a gate of the N-channel MOS tube is a control end of the first switch tube MN 5;

the second switch tube MN6 is an N-channel MOS tube, a drain of the N-channel MOS tube is a first end of the second switch tube MN6, a source of the N-channel MOS tube is a second end of the second switch tube MN6, and a gate of the N-channel MOS tube is a control end of the second switch tube MN 6.

Further, the current mirror module 1 includes a current input end IB, a seventh switching tube MP1, an eighth switching tube MP2, a ninth switching tube MP3, a tenth switching tube MP4, an eleventh switching tube MP5, a twelfth switching tube MN2, and a thirteenth switching tube MN 9;

the current input end IB is connected to a current source, the second end of the seventh switching tube MP1 is connected to the current input end IB, the control ends of the seventh to eleventh switching tubes (MP1-MP5) are all connected to the second end of the seventh switching tube MP1, the first ends of the seventh to eleventh switching tubes (MP1-MP5) are all connected to the power VCC, the second end of the eighth switching tube MP2 is connected to the charging end a1 of the first charging and discharging unit 21, the second end of the ninth switching tube MP3 is respectively connected to the first end and the control end of the twelfth switching tube MN2, the second end of the twelfth switching tube MN2 is grounded, the control end of the twelfth switching tube MN2 is connected to the control end a 9 of the thirteenth switching tube MN9 is grounded, the first end of the thirteenth switching tube 9 is connected to the discharging end e of the charging and discharging switching subunit 431, and the second end of the thirteenth switching tube MP4 is connected to the charging and discharging end a2 of the second charging and discharging unit MN 3531, a second terminal of the eleventh switching tube MP5 is connected to the current terminal g of the charge/discharge switching subunit 431.

Referring to fig. 5, it is a schematic circuit diagram of an embodiment of a logic control subunit of the sawtooth wave generating circuit provided in the present invention. As shown in fig. 5, the logic control subunit further includes a D flip-flop U3, a first delay U4, a second delay U5, a first inverter U6, a second inverter U7, a first and gate U8, and a second and gate U9;

a clock input end of the D flip-flop U3 is connected with a clock signal input end CLK1, a data input end of the D flip-flop U3 is connected with a second output end of the D flip-flop U3, a first output end of the D flip-flop U3 is connected with an input end of a first switch control output CLKC, a first delay unit U4 and a second input end of a first and gate U8, respectively, an output end of the first delay unit U4 is connected with an input end of a first inverter U6, an output end of the first inverter U6 is connected with a first input end of a first and gate U8, an output end of the first and gate U8 is connected with a first charge-discharge control output end CLK2, a second output end of the D flip-flop U3 is connected with an input end of a second switch control output CLKD, an input end of a second delay unit U5 and a first input end 686 of a second and gate U368, an output end of the second delay unit U6 is connected with an input end of a second inverter U7, an output end of the second and gate U7 is connected with a second input end, the output end of the second and gate U9 is connected to the second charge and discharge control output end CLK 3.

Further, the charge and discharge switching sub-unit 431 further includes a third switching tube MP6, a fourth switching tube MP7, a fifth switching tube MN4 and a sixth switching tube MN 10;

the first end of the third switching tube MP6 and the first end of the fourth switching tube MP7 are connected to the current end g, the control end of the third switching tube MP6 and the control end of the fifth switching tube MN4 are connected to the first switching control input end ct1, the second end of the third switching tube MP6 and the first end of the fifth switching tube MN4 are connected to the first current output end f1, the control end of the fourth switching tube MP7 and the control end of the sixth switching tube MN10 are connected to the second switching control input end ct2, the second end of the fourth switching tube MP7 and the first end of the sixth switching tube MN10 are connected to the second current output end f2, and the second end of the fifth switching tube MN4 and the second end of the sixth switching tube MN10 are connected to the discharge end e.

As shown in fig. 4 and 5, in an implementation, the capacitances of the first to fourth charge/discharge units (21,31,41,42) are matched, that is, C0 ═ C1 ═ C2 ═ C3, and the currents are also matched, that is, 2Ic0 ═ 2Ic1 ═ Ic2 ═ 2Ic 3. The control clock signals output by the first switch control output terminal CLKC, the second switch control output terminal CLKD, the first charge and discharge control output terminal CLK2 and the second charge and discharge control output terminal CLK3 are generated by the logic control subunit in fig. 5.

Referring to fig. 6, it is a timing diagram of logic control and a waveform diagram of sawtooth wave of the logic control subunit of the sawtooth wave generating circuit provided by the present invention. Referring to fig. 4, 5 and 6, when the high pulse of the clock signal output terminal CLK arrives, the second charge/discharge control output terminal CLK3 is a high pulse signal, and the potentials of the capacitor C1 and the capacitor C3 are pulled down to 0 rapidly; when the clock signal output end CLK is a low level signal, the second charge and discharge control output end CLK3 and the second switch control output end CLKD are low level signals, the voltages on the capacitor C1 and the capacitor C3 gradually rise, the first switch control output end CLKC is a high level signal, the capacitor C2 discharges with the current Ic3, and the boost sawtooth wave output end Vsaw _ boost takes the voltage of the capacitor C2; after one clock cycle, the first charge/discharge control output terminal CLK2 and the second switch control output terminal CLKD are high, the potentials of the capacitor C1 and the capacitor C2 are pulled down to 0 rapidly, the capacitor C3 discharges slowly from Ic3, in the previous cycle, the buck sawtooth wave output terminal Vsaw _ buck forms a sawtooth wave from 0 to Vsaw, the voltage of the capacitor C3 rises from 0 to 2Vsaw (therefore, Ic2 is 2Ic0), and the initial point of the capacitor C3 discharging from the capacitor Ic3 is 2 Vsaw. When the clock signal output terminal CLK and the first charge-discharge control output terminal CLK2 are at low level, the capacitor C1 and the capacitor C2 start to charge again, the potential of the capacitor C3 continuously decreases, and since the second switch control output terminal CLKD is at high at this time, the boost sawtooth wave output terminal Vsaw _ boost takes the potential of the capacitor C3, and has a peak value of 2Vsaw, which is a gradually decreasing sawtooth wave. After another clock cycle, the clock signal output terminal CLK and the second charge/discharge control output terminal CLK3 go high again, so that the potentials of the capacitor C1 and the capacitor C3 discharge to 0 quickly, the lowest value of the capacitor C3 is Vsaw, so that the voltage boost sawtooth output terminal Vsaw _ boost is a sawtooth wave with a peak value of 2Vsaw and a valley value of Vsaw, and the capacitor C2 charges for a clock cycle, at which the level is 2 Vsaw. When the clock signal output terminal CLK and the second charge-discharge control output terminal CLK3 are low again, the capacitor C1 and the capacitor C3 start to charge again, the capacitor C2 is slowly discharged from the Ic3, and the above process is repeated. In the whole working process, the circuit realizes the sawtooth wave of which the output voltage value of the voltage reduction sawtooth wave output end Vsaw _ buck is from 0 to Vsaw, and the sawtooth wave of which the output voltage value of the voltage boost sawtooth wave output end Vsaw _ boost is from Vsaw to 2 Vsaw. The adjustment is more flexible since the value of Vsaw can be set by itself.

The utility model provides a buck-boost converter, include as aforementioned embodiment sawtooth wave produce circuit.

It should be noted that, in the sawtooth wave generating circuit and the buck-boost converter provided in the foregoing embodiment, the discharge switch tubes (MN1, MN3, MN7, MN8), the first switch tube MN5, and the second switch tube MN6 are N-channel MOS tubes, which is only one implementation manner among them, in other implementations, the discharge switch tubes (MN1, MN3, MN7, MN8), the first switch tube MN5, and the second switch tube MN6 may also be replaced by P-channel MOS tubes or other three-terminal control switch devices or derivatives thereof, and in different application occasions, the selection and the setting of the switch tubes are a common design process in the prior art according to requirements such as power consumption, cost, driving power of an actual circuit, parameter matching with a driving control element of the switch tubes, and the like, and are not described herein.

The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered as the protection scope of the present invention.

Claims

1. A sawtooth wave generation circuit is characterized by comprising a current mirror module, a clock generation module, a voltage reduction sawtooth wave module and a voltage boosting sawtooth wave module, wherein the clock generation module comprises a first charge-discharge unit and a comparator unit, the voltage reduction sawtooth wave module comprises a second charge-discharge unit, and the voltage boosting sawtooth wave module comprises a third charge-discharge unit, a fourth charge-discharge unit and a control unit; the first to fourth charge and discharge units have the same circuit structure;

2. The sawtooth wave generating circuit of claim 1 wherein the first to fourth charge and discharge units each comprise a control signal input terminal, a ground terminal, a charge terminal, and a charge voltage output terminal, and the comparator unit comprises a voltage signal input terminal, a reference signal input terminal, and a clock signal output terminal;

3. The sawtooth generation circuit of claim 2 wherein the comparator unit comprises a comparator and an inverter;

4. The sawtooth wave generation circuit of claim 2 wherein the buck sawtooth wave module further comprises a buck sawtooth wave output, the charge terminal of the second charge and discharge unit is connected to the current mirror module, the control signal input terminal of the second charge and discharge unit is connected to a clock signal output terminal of the comparator unit, and the charge voltage output terminal of the second charge and discharge unit is connected to the buck sawtooth wave output terminal.

5. The sawtooth wave generation circuit of any one of claims 2 to 4 wherein the boost sawtooth wave module further comprises a boost sawtooth wave output, the control unit comprises a logic control subunit, a charge-discharge switching subunit, a first switching tube and a second switching tube, the logic control subunit comprises a clock signal input, a first charge-discharge control output, a second charge-discharge control output, a first switching control output and a second switching control output, the charge-discharge switching subunit comprises a current terminal, a first current output, a second current output, a first switching control input, a second switching control input and a discharge terminal;

6. The sawtooth wave generation circuit of claim 5 wherein the charge-discharge switching sub-unit further comprises a third switching tube, a fourth switching tube, a fifth switching tube and a sixth switching tube;

7. The sawtooth wave generation circuit of claim 5 wherein the logic control subunit further comprises a D flip-flop, a first delay, a second delay, a first inverter, a second inverter, a first AND gate, and a second AND gate;

8. The sawtooth wave generation circuit of any one of claims 2 to 4 wherein the first to fourth charge and discharge units each further comprise a discharge switch and a capacitor;

9. The sawtooth wave generation circuit of claim 5 wherein the current mirror module comprises a current input terminal, a seventh switching tube, an eighth switching tube, a ninth switching tube, a tenth switching tube, an eleventh switching tube, a twelfth switching tube and a thirteenth switching tube;

10. A buck-boost converter comprising a sawtooth wave generation circuit as claimed in any one of claims 1 to 9.