CN217216540U

CN217216540U - Oscillator circuit for detecting capacitive touch keys

Info

Publication number: CN217216540U
Application number: CN202220128841.0U
Authority: CN
Inventors: 吴国辅
Original assignee: Guowei Group Shenzhen Co ltd
Current assignee: Guowei Group Shenzhen Co ltd
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2022-08-16
Anticipated expiration: 2032-01-18

Abstract

The utility model discloses an oscillator circuit for electric capacity touch button detects, the oscillator circuit includes: the touch control circuit comprises an external capacitor connected with a touch key, a first current mirror circuit for charging the external capacitor, a second current mirror circuit for discharging the external capacitor, a first switch circuit for controlling the working states of the first current mirror circuit and the second current mirror circuit, and a comparator circuit for adjusting the control state of the first switch circuit according to the voltage of the external capacitor, wherein the output signal of the comparator circuit is used as a detection signal for detecting whether the external capacitor is touched, and when the frequency of the detection signal is changed, the external capacitor is touched. Compared with the prior art, the utility model overcomes traditional clock produces the shortcoming of oscillator circuit, has improved the interference killing feature greatly, and is insensitive to mains voltage simultaneously, and circuit structure is simple, and chip territory area has been saved in easily realizing.

Description

Oscillator circuit for detecting capacitive touch keys

Technical Field

The utility model relates to an oscillator circuit technical field, especially an oscillator circuit for electric capacity touch button detects.

Background

The capacitive touch key is a relatively new technology and has sensitivity, stability and reliability. Compared with the traditional mechanical key, the capacitive touch key has longer service life and higher sensitivity. And the capacitive touch key does not need a human body to directly contact metal, so that potential safety hazards can be avoided, and the capacitive touch key is not influenced by key materials, so that the overall appearance grade of the product can be improved in the key scheme.

Principle of capacitive touch keys: an induction capacitor always exists between the two conductors, one key, namely one bonding pad and the ground can form the induction capacitor, and under the condition that the surrounding environment is not changed, the value of the induction capacitor is a fixed value. However, when a human finger approaches the touch key, the total inductive capacitance value is increased due to the inductive capacitance formed by the inductive capacitance parallel pad formed by the human finger and the ground and the inductive capacitance formed by the ground. The capacitive touch key is used for generating a corresponding signal after detecting that the value of the induction capacitance of the key is changed. The electric quantity detected by the capacitive touch key is slightly changed, so that the requirements on the anti-interference and precision of a detection circuit are higher.

The existing detection methods mainly comprise two types: (1) an RC oscillation circuit is formed by an external capacitive touch key, a resistor and a Schmitt trigger, and whether a person touches the capacitive touch key is judged by detecting the change of oscillation frequency; (2) and establishing a constant current source to repeatedly charge and discharge the external capacitor, and judging whether the external capacitance value changes or not by detecting the charging and discharging times in unit time or the time of reaching a fixed reference voltage value during each charging. However, both of these methods have disadvantages, for example, the method (1) has a disadvantage that the probability of the occurrence of the false touch is relatively high, and no good method is available at present, although the main structure of the method (1) is simple, if a stable oscillation frequency is to be obtained, an additional filter circuit, some band gap references, a voltage stabilizing circuit and the like are required to be added, and the circuit scale is not small in practice. The method (2) has the disadvantages that the capacitor is unbalanced in charging and discharging under the interference of an external electromagnetic environment, especially under the interference of low frequency, and the power supply voltage inside the detection circuit is sensitive.

Therefore, how to design an oscillator circuit for capacitive touch key detection, which can overcome the disadvantages of the conventional clock generation oscillator circuit and improve the anti-interference capability, is a technical problem to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

To the defect that prior art exists, the utility model provides an oscillator circuit for electric capacity touch button detects.

The technical scheme of the utility model for, provide an oscillator circuit for electric capacity touch button detects, include: the touch control circuit comprises an external capacitor connected with a touch key, a first current mirror circuit for charging the external capacitor, a second current mirror circuit for discharging the external capacitor, a first switch circuit for controlling the working states of the first current mirror circuit and the second current mirror circuit, and a comparator circuit for adjusting the control state of the first switch circuit according to the voltage of the external capacitor, wherein the output signal of the comparator circuit is used as a detection signal for detecting whether the external capacitor is touched, and when the frequency of the detection signal changes, the external capacitor is touched.

The voltage divider circuit is connected with the first current mirror circuit and the second current mirror circuit, and the second switch circuit is connected with the voltage divider circuit and the comparator circuit, wherein the voltage divider circuit can output two different voltage signals as reference voltages of the comparator circuit, and the second switch circuit is used for switching the voltage signals output to the comparator circuit.

Further, the amplification factors of the first current mirror circuit and the second current mirror circuit are the same, so that the charging time of the first current mirror circuit to the external capacitor is equal to the discharging time of the second current mirror circuit to the external capacitor, and the detection signal is a clock signal with a duty ratio equal to 50%.

Further, the first switch circuit comprises a first switch connected between the first current mirror circuit and an external capacitor and a second switch connected between the second current mirror circuit and the external capacitor, the comparator circuit comprises a comparator with a non-inverting input end connected with the external capacitor and an inverter connected with an output end of the comparator, an inverting input end of the comparator is connected with a reference voltage, a control end of the first switch is connected with an output end of the inverter, and a control end of the second switch is connected with an output end of the comparator.

Further, the first current mirror circuit is a PMOS current mirror structure, and the second current mirror circuit is an NMOS current mirror structure.

Further, the second switch circuit comprises a first transmission gate and a second transmission gate which are connected with the voltage division circuit, the input end of the first transmission gate is connected to the high-voltage side of the voltage division circuit, the input end of the second transmission gate is connected to the low-voltage side of the voltage division circuit, and the output ends of the first transmission gate and the second transmission gate are connected with each other and then connected with the comparator circuit.

Furthermore, the voltage division circuit adopts components and parts according with ohm law, and the two sides of the components and parts are respectively a high-voltage side and a low-voltage side.

Further, the oscillator circuit includes: MOS transistor PM1, MOS transistor PM2, MOS transistor PM3, MOS transistor NM1, MOS transistor NM2, MOS transistor NM3, external capacitor C0, comparator COMP, inverter INV, transmission gate TG1, transmission gate TG2 and resistor R0;

a first end of the MOS transistor PM1 is connected to a power supply AVDD, a second end of the MOS transistor PM3 is connected to a first end and a third end of the MOS transistor PM2, a second end of the MOS transistor PM3 is connected to a second end of the MOS transistor NM3, a first end of the MOS transistor NM3 is connected to a second end of the MOS transistor NM1, a first end of the MOS transistor NM1 is grounded, a third end of the MOS transistor NM1 is connected to a third end of the MOS transistor NM2, a first end of the MOS transistor PM2 is connected to the power supply AVDD, a second end of the MOS transistor NM 68684, the other end of the resistor R0 is connected to a second end of the MOS transistor NM2, a first end of the MOS transistor NM2 is grounded, an input end of the transmission gate TG1 is connected between the MOS transistor PM2 and the resistor R0, an input end of the transmission gate TG2 is connected between the MOS transistor NM 6324 and the transmission gate TG 0, and an inverted phase comparator TG2 is connected to the output terminal COMP output terminal, the non-inverting input end of the comparator COMP is connected in series with the external capacitor C0, and then grounded, and the output end is connected to the third end of the MOS transistor PM3 and the third end of the MOS transistor NM3, respectively.

Further, the period of the detection signal is: t =2 RC/n;

wherein, T is the period of the detection signal, R is the resistance of the resistor R0, C is the capacitance of the external capacitor C0, and n is the ratio of the charging and discharging current of the external capacitor C0 to the current of the resistor R0.

Compared with the prior art, the utility model discloses following beneficial effect has at least:

the utility model discloses use the triangular wave to generate the clock, overcome traditional clock generation oscillator circuit's shortcoming, improved the interference killing feature greatly, it is insensitive to mains voltage change simultaneously, circuit structure is simple, easily realizes, saves chip territory area.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic circuit diagram of an oscillator circuit according to the present invention;

fig. 2 is a schematic diagram of the oscillator circuit according to the present invention.

Detailed Description

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Thus, a feature indicated in this specification will serve to explain one of the features of an embodiment of the invention, and not to imply that every embodiment of the invention must have the explained feature. Further, it should be noted that this specification describes many features. Although some features may be combined to show a possible system design, these features may also be used in other combinations not explicitly described. Thus, the combinations illustrated are not intended to be limiting unless otherwise specified.

The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and examples.

The existing detection method of the capacitive touch key mainly comprises the following steps: (1) an RC oscillation circuit is formed by an external capacitive touch key, a resistor and a Schmitt trigger, and whether a person touches the capacitive touch key is judged by detecting the change of oscillation frequency; (2) and establishing a constant current source to repeatedly charge and discharge the external capacitor, and judging whether the external capacitance value changes or not by detecting the charging and discharging times in unit time or the time of reaching a fixed reference voltage value during each charging. However, both of these methods have disadvantages, for example, the method (1) has a disadvantage that the probability of the occurrence of the false touch is relatively high, and no good method is available at present, although the main structure of the method (1) is simple, if a stable oscillation frequency is to be obtained, an additional filter circuit, some band gap references, a voltage stabilizing circuit and the like are required to be added, and the circuit scale is not small in practice. The method (2) has the disadvantages that the capacitor is unbalanced in charging and discharging under the interference of an external electromagnetic environment, especially under the interference of low frequency, and the power supply voltage inside the detection circuit is sensitive.

The utility model discloses an idea lies in, provides an oscillator circuit, and it carries out charge and discharge through a comparator circuit, two switch circuit, two current mirror circuit and a bleeder circuit to outside electric capacity to generate stable triangle wave signal, confirm whether outside electric capacity takes place the button touch action through direct frequency through detecting this triangle wave, overcome the defect of traditional scheme, improved the interference killing feature.

Specifically, the utility model provides an oscillator circuit, include: an external capacitor connected to the touch button, a first current mirror circuit for charging the external capacitor, a second current mirror circuit for discharging the external capacitor, a first switch circuit for controlling the operating states of the first current mirror circuit and the second current mirror circuit, and a comparator circuit for adjusting the control state of the first switch circuit according to the voltage of the external capacitor, the non-inverting input terminal of the comparator circuit is connected with the external capacitor for accessing the voltage on the external capacitor, the inverting input terminal thereof is accessed with a reference voltage, the output signal of the comparator circuit changes along with the charging and discharging of the first current mirror circuit and the second current mirror circuit to the external capacitor, when no one touches the external capacitor, the frequency of the signal is stable and unchanged, when a person touches the external capacitor, the frequency of the signal is also changed, and whether touch is formed or not can be determined by detecting the change of the frequency.

Furthermore, in order to reduce the influence of the power supply voltage, the oscillator circuit of the present invention further comprises a voltage dividing circuit connected to the first current mirror circuit and the second current mirror circuit, and a second switch circuit connected to the voltage dividing circuit and the comparator circuit, wherein two ends of the voltage dividing circuit can output two different voltage signals respectively, the signal is used as a reference signal to be output to an inverting input terminal of the comparator circuit, the second switch circuit is used for switching the connected voltage signal, the voltage of the external capacitor is enabled to work between two voltage signals of the voltage dividing circuit, in addition, the voltage dividing circuit can also provide reference current for the first current mirror circuit and the second current mirror circuit, the voltage dividing circuit meets ohm's law, V/I = beta, the reference current I1= (V2-V1)/β input to the current mirror, and the charge and discharge current I2= α (V2-V1)/β supplied to the capacitor. Because the magnitude of the charging and discharging current is the same, the time required by charging and discharging is also consistent, so the charging and discharging period is T =2(V2-V1)/I2, and the expression of I2 is substituted, and T =2 beta/alpha can be obtained, so the charging and discharging period is only related to the voltage and current correlation coefficient of the voltage division circuit and the amplification factor of the two current mirrors, which makes the circuit structure provided by the utility model insensitive to the change of the power supply voltage.

Preferably, the present invention provides the same amplification factor between the first current mirror circuit and the second current mirror circuit, so that the charging time of the first current mirror circuit to the external capacitor is equal to the discharging time of the second current mirror circuit to the external capacitor, and the comparator circuit can output a clock signal with a duty ratio equal to 50% for detection. In other embodiments of the present invention, if the detection clock needs a specific duty ratio, the charging and discharging time can be unequal, so that a clock with a duty ratio not equal to 50% can be generated.

Referring to fig. 1, a current mirror 1 is a first current mirror circuit, a current mirror 2 is a second current mirror circuit, the first switch circuit is composed of a switch 1 and a switch 2, the comparator circuit includes a comparator connected to an external capacitor and an inverter connected to an output terminal of the comparator, and the second switch circuit employs a single-pole double-throw switch.

The output current direction of the current mirror 1 flows out from the current mirror 1 and is used for charging an external capacitor, a PMOS current mirror structure is usually adopted, the output current direction of the current mirror 2 flows into the current mirror and is used for discharging the external capacitor, and an NMOS current mirror structure is usually adopted. It should be noted that the structures of the PMOS current mirror and the NMOS current mirror can be selected according to actual situations, and can also be replaced by other circuits with charge and discharge functions, which is not limited by the present invention;

the voltage dividing circuit is formed using a device conforming to ohm's law, having at least a high-voltage side and a low-voltage side as reference voltages for the comparator circuit, and switching the high-voltage side or the low-voltage side as the reference voltages by the second switching circuit, and further, the voltage dividing circuit needs to be connected to the two current mirror circuits, respectively, to supply reference currents;

the structure of the single-pole double-throw switch can select two transmission gates, one end of each transmission gate is connected together for realization, and a single-pole double-throw switch circuit with other structures can also be adopted, so that only the high-voltage side of the voltage division circuit is gated when the capacitor is charged and the low-voltage side of the voltage division circuit is gated when the capacitor is discharged, and the specific structure of the single-pole double-throw switch is not limited by the utility model;

the switch 1 and the switch 2 can be respectively realized by a single PMOS tube and a single NMOS tube, and the gates are used as control ends, because the PMOS tube and the NMOS tube are the switch devices with the inverters relatively, the gates of the switch 1 and the switch 2 can be connected to the output end of the comparator together without the participation of the inverters in the embodiment, in this case, when the comparator outputs a high level signal, the gate of the switch 1 receives the high level signal and is in a cut-off state, the gate of the switch 2 receives the high level signal and is in a conducting state, at the moment, the external capacitor discharges, when the comparator outputs a low level signal, the gate of the switch 1 receives the low level signal and is in a conducting state, the gate of the switch 2 receives the low level signal and is in a cut-off state, at the moment, the external capacitor charges.

The utility model discloses in other embodiments, switch 1 and switch 2 also can all adopt the NMOS pipe, and for switch 1 and switch 2's the chronogenesis that switches on is opposite under guaranteeing this condition, need be connected to switch 1's grid with the output of phase inverter to reach the same control effect.

The utility model discloses a two current mirror circuit, comparator circuit, first switch circuit, second switch circuit, bleeder circuit and outside electric capacity's cooperation has overcome traditional clock and has produced the shortcoming of oscillator circuit, has improved the interference killing feature greatly.

Specifically, please refer to fig. 2, the present invention provides an oscillator circuit, including: MOS transistor PM1, MOS transistor PM2, MOS transistor PM3, MOS transistor NM1, MOS transistor NM2, MOS transistor NM3, external capacitor C0, comparator COMP, transmission gate TG1, transmission gate TG2 and resistor R0;

a first end of the MOS transistor PM1 is connected with a power supply AVDD, a second end of the MOS transistor PM3 is connected with a first end and a third end of the MOS transistor PM2, a second end of the MOS transistor PM3 is connected with a second end of the MOS transistor NM3, a first end of the MOS transistor NM3 is connected with a second end of the MOS transistor NM1, a first end of the MOS transistor NM1 is grounded, a third end of the MOS transistor NM1 is connected with a third end of the MOS transistor NM2, a first end of the MOS transistor PM2 is connected with the power supply AVDD, a second end of the MOS transistor NM 6384 is connected with a resistor R0, the other end of the resistor R0 is connected with a second end of the MOS transistor NM2, a first end of the MOS transistor NM2 is grounded, an input end of the transmission gate TG1 is connected between the MOS transistor PM 5 and the resistor R0, an input end of the transmission gate TG2 is connected between the MOS transistor NM2 and the resistor R0, an output end of the transmission gate TG1 and the transmission gate TG2 are connected with an inverted phase comparator, the non-inverting input end of the comparator COMP is connected in series with the external capacitor C0, then grounded, and the output end is connected to the third end of the MOS transistor PM3 and the third end of the MOS transistor NM3, respectively;

in this embodiment, the input terminal of the inverter INV is connected to the output terminal of the comparator COMP, the output terminal thereof may be connected to the N control terminal of the transmission gate TG1 and the P control terminal of the transmission gate TG2, respectively, and the output terminal of the comparator COMP is connected to the P control terminal of the transmission gate TG1 and the N control terminal of the transmission gate TG2, respectively. Through the connection mode, the comparator COMP can control the two transmission gates to realize the switching of the reference voltage, specifically, when the comparator COMP outputs a low level signal, the transmission gate TG1 is turned on, and when the comparator COMP outputs a high level signal, the transmission gate TG2 is turned on.

The working principle of the voltage regulator is that (1) in an initial state, the charge amount of an external capacitor C0 is 0, namely the voltage on an external capacitor C0 is 0, the voltage at VC is 0, a comparator COMP outputs a low-level signal, a transmission gate TG1 is turned on, the voltage V2 on the high-voltage side of an access resistor R0 is used as the reference voltage of the comparator COMP, the grid of a MOS tube PM3 receives the low-level signal and is in a turned-on state, the grid of a MOS tube NM3 receives the low-level signal and is in a turned-off state, at the moment, current flowing out by a power supply AVDD sequentially passes through the MOS tube PM3 and the MOS tube NM3 and then flows into the external capacitor C0 to charge the external capacitor C0;

(2) after the external capacitor C0 is charged for a period of time, when the voltage of the external capacitor C0 is higher than V2, the voltage at VC is higher than V2, the voltage at the non-inverting input end of the comparator COMP is higher than the reference voltage at the inverting input end, a high level signal is output, the gate of the MOS transistor PM3 receives the high level signal and is in an off state, the gate of the MOS transistor NM3 receives the high level signal and is in an on state, in this case, the external capacitor C0 discharges, and the current flowing out of the external capacitor C0 sequentially passes through the MOS transistor PM3 and the MOS transistor NM1 and is guided to the ground. Meanwhile, as the comparator COMP outputs a high-level signal, the transmission gate TG1 is closed, the transmission gate TG2 is switched on, the voltage V1 on the low-voltage side of the access resistor R0 is used as a reference voltage, and as the voltage V1 is smaller than the voltage V2, the voltage of the non-inverting input end of the comparator COMP is still higher than the inverting input end, the high-level signal is output, and the external capacitor C0 continuously discharges;

(3) after the external capacitor C0 discharges for a period of time, when the voltage of the external capacitor C0 is lower than V1, the voltage of the non-inverting input terminal of the comparator COPM is lower than the reference voltage of the inverting input terminal again, the comparator COPM outputs a low level signal, the gate of the MOS transistor PM3 receives the low level signal and is in an on state, the gate of the MOS transistor NM3 receives the low level signal and is in an off state, and at this time, the current flowing out from the power supply AVDD flows into the external capacitor C0 after passing through the MOS transistor PM3 and the MOS transistor NM3 in sequence, and charges the external capacitor C0, and the voltage of the external capacitor C0 starts to rise from V1. Meanwhile, the comparator COMP outputs a low-level signal, so that the transmission gate TG1 is turned on again, the transmission gate TG2 is turned off, the voltage V2 on the high-voltage side of the access resistor R0 is used as a reference voltage, and the voltage V2 is higher than the voltage V1, so that the voltage of the non-inverting input end of the comparator COMP is still lower than the inverting input end, the low-level signal is output, and the external capacitor C0 is continuously charged;

(4) after the external capacitor C0 is charged for a period of time, when the voltage of the external capacitor C0 is higher than V2, repeating the process (2); and enters the process (3) after the process (2) is discharged for a period of time, and the processes (2) and (3) are repeated all the time thereafter, and the external capacitor C0 is charged between the voltage V1 and the voltage V2.

In addition, the MOS transistor PM2, the resistor R0 and the MOS transistor NM2 form a direct current channel, the current value of the branch is I1= (V2-V1)/R, the absolute value of the current flowing through the PM1 and the NM1 is I2 and I2= nI1 according to the width-length ratio of the MOS transistor PM1, the MOS transistor PM2, the MOS transistor NM1 and the MOS transistor NM 2.

Since the charging and discharging currents are constant and the current values are I2, the change process of VC with respect to time t is linear, i.e., VC = a × t + b, a >0 during charging and a <0 during discharging. When the offset error of the comparator is ignored, the output of the comparator immediately starts to respond when VC is greater than V2 and when VC is less than V1, the output voltage is changed from low to high or from high to low, and the charging and discharging states are immediately switched, so that VC can be considered to be changed only from V1 to V2. Then, the sum of the time of each charging and discharging process (i.e. the charging and discharging period) except the unstable state before the charging and the enabling and the process of the first time VC climbing from 0 to V2 can be obtained: t =2C (V2-V1)/I2, and then I2= nI1 and I1= (V2-V1)/R are substituted, so that T =2RC/n is reduced; wherein, T is the period of the detection signal, R is the resistance of the resistor R0, C is the capacitance of the external capacitor C0, and n is the ratio of the charging and discharging current of the external capacitor C0 to the current of the resistor R0.

The charge-discharge period is only related to the change of the external capacitance as long as R and n of the circuit are determined, which has the advantage of reducing the sensitivity of the circuit to changes in the supply voltage. When the external capacitance changes, the external capacitance can directly act on the charge-discharge period, and whether the external capacitance changes can be judged by detecting whether the charge-discharge frequency changes within a fixed time.

The result of the comparator COPM can be regarded as a clock signal and can be used as a detection. If no one touches the touch screen, the clock signal has a constant frequency, when one touches the capacitive button, the capacitance value of the external capacitor C0 changes, and the frequency of the clock signal changes, and whether the touch action occurs can be determined by detecting the change of the frequency.

Based on the oscillator circuit, the detection method comprises the following steps:

turning on an oscillator circuit;

acquiring a detection signal output by a comparator circuit;

judging whether the external capacitor has a key touch behavior according to the detection signal;

wherein, judge whether external capacitance takes place button touch action according to the detected signal, include: and acquiring the frequency of the detection signal, judging whether the frequency is changed, if so, judging that the external capacitor has a key touch behavior, and if not, judging that the external capacitor does not have the key touch behavior.

The utility model discloses a scheme is compared in traditional scheme, and it has overcome the shortcoming of traditional clock generation oscillator circuit, has improved the interference killing feature greatly, and is insensitive to mains voltage change simultaneously, and circuit structure is simple, easily realizes, saves chip territory area.

The above examples are only for illustrating the specific embodiments of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several modifications and changes can be made, and all such modifications and changes are intended to fall within the scope of the present invention.

Claims

1. An oscillator circuit for capacitive touch key detection, comprising: the touch control circuit comprises an external capacitor connected with a touch key, a first current mirror circuit for charging the external capacitor, a second current mirror circuit for discharging the external capacitor, a first switch circuit for controlling the working states of the first current mirror circuit and the second current mirror circuit, and a comparator circuit for adjusting the control state of the first switch circuit according to the voltage of the external capacitor, wherein the output signal of the comparator circuit is used as a detection signal for detecting whether the external capacitor is touched, and when the frequency of the detection signal changes, the external capacitor is touched.

2. The oscillator circuit according to claim 1, further comprising a voltage dividing circuit connected to the first current mirror circuit and the second current mirror circuit, and a second switching circuit connecting the voltage dividing circuit and the comparator circuit, the voltage dividing circuit being capable of outputting two different voltage signals as a reference voltage of the comparator circuit, the second switching circuit being configured to switch the voltage signal output to the comparator circuit.

3. The oscillator circuit according to claim 1, wherein the amplification factor of the first current mirror circuit is the same as that of the second current mirror circuit, the charging time of the external capacitor by the first current mirror circuit is equal to the discharging time of the external capacitor by the second current mirror circuit, and the detection signal is a clock signal having a duty ratio equal to 50%.

4. The oscillator circuit according to claim 1, wherein the first switch circuit includes a first switch connected between the first current mirror circuit and an external capacitor, and a second switch connected between the second current mirror circuit and the external capacitor, the comparator circuit includes a comparator having a non-inverting input connected to the external capacitor, and an inverter connected to an output of the comparator, an inverting input of the comparator is connected to a reference voltage, a control terminal of the first switch is connected to an output of the inverter, and a control terminal of the second switch is connected to an output of the comparator.

5. The oscillator circuit according to claim 1, wherein the first current mirror circuit is a PMOS current mirror structure and the second current mirror circuit is an NMOS current mirror structure.

6. The oscillator circuit of claim 2, wherein the second switch circuit comprises a first transmission gate and a second transmission gate connected to the voltage divider circuit, an input terminal of the first transmission gate is connected to a high voltage side of the voltage divider circuit, an input terminal of the second transmission gate is connected to a low voltage side of the voltage divider circuit, and output terminals of the first transmission gate and the second transmission gate are connected to the comparator circuit.

7. The oscillator circuit according to claim 2, wherein the voltage divider circuit employs a component conforming to ohm's law, and the two sides of the component are a high voltage side and a low voltage side, respectively.

8. The oscillator circuit of claim 2, wherein the oscillator circuit comprises:

MOS transistor PM1, MOS transistor PM2, MOS transistor PM3, MOS transistor NM1, MOS transistor NM2, MOS transistor NM3, external capacitor C0, comparator COMP, transmission gate TG1, transmission gate TG2 and resistor R0;

a first end of the MOS transistor PM1 is connected to a power supply AVDD, a second end of the MOS transistor PM3 is connected to a first end and a third end of the MOS transistor PM2, a second end of the MOS transistor PM3 is connected to a second end of the MOS transistor NM3, a first end of the MOS transistor NM3 is connected to a second end of the MOS transistor NM1, a first end of the MOS transistor NM1 is grounded, a third end of the MOS transistor NM1 is connected to a third end of the MOS transistor NM2, a first end of the MOS transistor PM2 is connected to the power supply AVDD, a second end of the MOS transistor NM 68684, the other end of the resistor R0 is connected to a second end of the MOS transistor NM2, a first end of the MOS transistor NM2 is grounded, an input end of the transmission gate TG1 is connected between the MOS transistor PM2 and the resistor R0, an input end of the transmission gate TG2 is connected between the MOS transistor NM 6324 and the transmission gate TG 0, and an inverted phase comparator TG2 is connected to the output terminal COMP output terminal, the non-inverting input end of the comparator COMP is connected in series with an external capacitor C0, and then grounded, and the output end is connected to the third end of the MOS transistor PM3 and the third end of the MOS transistor NM3, respectively.