CN217158193U

CN217158193U - Image sensor

Info

Publication number: CN217158193U
Application number: CN202221107592.3U
Authority: CN
Inventors: 李加; 陈维; 林子瑛
Original assignee: Zhejiang Xingxin Semiconductor Co ltd
Current assignee: Zhejiang Xingxin Semiconductor Co ltd
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2022-08-09
Anticipated expiration: 2032-05-10

Abstract

The utility model provides an image sensor, the image sensor is based on the image sensor that germanium p-i-n photodiode made, and it includes silicon control and reading circuit wafer, dielectric passivation layer, germanium photodiode layer, antireflection coating and lens layer from bottom to top in proper order; the germanium photodiode layer is of a laminated structure and sequentially comprises a residual silicon layer, an undoped germanium layer and a doped germanium layer from bottom to top, wherein the undoped germanium layer is an intrinsic layer; and depositing a dielectric passivation layer on the outward surface of the residual silicon layer. The utility model discloses make via the manufacturing process simpler relatively, specifically make for the production manufacturing process via high-speed, the short wave infrared image sensor of small pixel size. The utility model discloses an image sensor has realized low-cost, CMOS compatible shortwave infrared image sensor.

Description

Image sensor

Technical Field

The utility model belongs to the technical field of the semiconductor, a image sensor is related to, it is made by perpendicular p-i-n photodiode, perpendicular p-i-n photodiode is the perpendicular p-i-n photodiode of the infrared CMOS image sensor of shortwave.

Background

At present, short-wave infrared CMOS Image sensors (SWIRCMOS Image sensors) have been widely used in the fields of small unmanned aerial vehicle systems, motor vehicle systems, intelligent agricultural systems, monitoring systems, and the like. As is well known in the art, the use of silicon materials as photodiodes has a low quantum efficiency for infrared absorption, and in particular, there is little absorption in the wavelength band above 1 μm. Short-wave infrared CMOS image sensors based on germanium can capture images from visible light (0.4-0.75 μm) and further wavelengths (up to 1.6 μm wavelength) compared to silicon, and perform comparable to indium gallium arsenide (InGaAs). CMOS image sensors based on indium gallium arsenide, although capable of providing high quality Focal Plane Arrays (FPAs) with high quantum efficiency and relatively low dark current, are currently complex in fabrication process, expensive, low in yield, and difficult to be commercially applied on a large scale. In contrast to indium gallium arsenide, germanium is chemically compatible with silicon and compatible with silicon CMOS fabrication processes. Thus, the fabrication process of germanium-based photodiodes for short wave infrared CMOS image sensors is more flexible, cost effective and scalable and opens up consumer/mass market applications.

In the process of manufacturing a germanium-based CMOS image sensor, in the prior art, germanium is generally epitaxially grown on a silicon target wafer, but due to 4.2% of lattice mismatch between germanium and silicon, misfit dislocation and threading dislocation (thread dislocation) are generated in epitaxial growth, so that the number of defects is large, the quality is low, and the detection signal-to-noise ratio and the detection sensitivity are affected. This problem, while currently ameliorated by some technical means, can increase device structure and/or process complexity, such as selective fabrication growth using narrow apertures. Furthermore, since the use of direct epitaxial growth of germanium on a silicon target wafer is the low temperature growth of germanium on a silicon wafer, this directly results in a reduction in the quality of the germanium layer.

Based on the application requirements of the industrial market and the consumer/mass market, a process which is simpler in process, lower in cost and capable of efficiently and stably manufacturing and integrating the vertical germanium p-i-n photodiode into an image sensing integrated device structure is urgently needed.

SUMMERY OF THE UTILITY MODEL

Based on the problems existing in the prior art, the utility model provides an image sensor, it is made by perpendicular p-i-n photodiode, perpendicular p-i-n photodiode is preferably the perpendicular p-i-n photodiode of short wave infrared CMOS image sensor.

According to the technical scheme of the utility model, the utility model provides an image sensor, image sensor is based on the image sensor that germanium p-i-n photodiode made, and it includes silicon control and reading out circuit wafer, dielectric passivation layer, germanium photodiode layer, antireflection coating and lens layer from bottom to top in proper order; the germanium photodiode layer is of a laminated structure and sequentially comprises a residual silicon layer, an undoped germanium layer and a doped germanium layer from bottom to top, wherein the undoped germanium layer is an intrinsic layer; a dielectric passivation layer is deposited on the outwardly facing surface of the remaining silicon layer.

Furthermore, the germanium photodiode layer further comprises an inter-trench dielectric layer penetrating through the germanium photodiode layer laminated structure, and the inter-trench dielectric layer divides the germanium photodiode layer into a plurality of independent pixel regions. In each individual pixel region, two metal connections are provided from bottom to top on the dielectric passivation layer and the germanium photodiode layer, a first metal connection being connected to the remaining silicon layer and a second metal connection being connected to the doped germanium layer. The two metal connections are level with the dielectric passivation layer. An alignment mark is provided on an outward facing surface of the dielectric passivation layer.

Further, the outwardly facing surface of the interconnect layer of the silicon control and readout circuitry wafer is abutted against the outwardly facing surface of the dielectric passivation layer of the germanium photodiode layer temporarily bonded to the carrier, and the metallic connection of the germanium photodiode layer is connected to the circuitry of the interconnect layer by alignment marks on the outwardly facing surface of the interconnect layer of the silicon control and readout circuitry wafer and the outwardly facing surface of the dielectric passivation layer of the germanium photodiode layer temporarily bonded to the carrier ensuring that the outwardly facing surface of the interconnect layer of the silicon control and readout circuitry wafer is aligned with the outwardly facing surface of the dielectric passivation layer of the germanium photodiode layer temporarily bonded to the carrier.

Additionally, a filter layer is also present between the antireflective layer and the lens layer. And depositing an anti-reflection layer on the surface formed by the doped germanium layer and the inter-groove dielectric layer.

Compared with the prior art, the utility model discloses a beneficial technological effect as follows:

1. the utility model discloses make via the manufacturing process simpler relatively, specifically make for the production manufacturing process via high-speed, the short wave infrared image sensor of small pixel size.

2. The technical scheme of the utility model low-cost, CMOS compatible shortwave infrared image sensor (have the focal plane array) has been realized.

3. The utility model discloses image sensor has from visible light to short wave infrared wavelength's lower dark current, higher sensitivity.

4. The utility model discloses image sensor's production technology is simple relatively, the technology is mature, be suitable for the industrialization large-scale production.

5. The utility model discloses image sensor adopts germanium-silicon layer transfer technique to obtain high-quality photodiode layer single crystal germanium layer, compares with direct epitaxial growth germanium layer on silicon target wafer, has higher quality and defect still less.

6. The utility model discloses image sensor for according to the image sensor that germanium p-i-n photodiode made and integrated to the method manufacturing in the image sensor structure, it is Back Side Illumination (BSI) sensor, adopts heap CMOS structure, and silicon control and reading circuit are located the pixel layer back promptly, and this kind of structure promotes or has increased the incident photon quantity of catching on the pixel layer to noise has been reduced and the wholeness can has been improved.

7. The utility model discloses image sensor has realized perpendicular photodiode's integration according to the manufacturing process design with germanium p-i-n photodiode manufacturing and the method of integrated to the image sensor structure, and perpendicular p-i-n photodiode's metal contact all only contacts p type district and n type district from the back, can not block the shining of incident photon to the incident photon quantity of catching has been guaranteed.

8. The utility model discloses but germanium donor wafer reuse in the image sensor manufacturing process to produce more germanium transfer layers, resource utilization is higher, and manufacturing cost is lower.

Drawings

Fig. 1 to 17 are schematic diagrams illustrating a manufacturing process of the image sensor according to the present invention by manufacturing and integrating the ge p-i-n photodiode.

The names of the components indicated by reference numerals in the drawings are as follows:

1. a germanium donor wafer; 2. a germanium transfer layer; 3. a silicon target wafer; 4. a germanium-silicon mixed wafer; 5. doping a germanium layer; 6. an undoped germanium layer; 7. a germanium photodiode layer; 8. isolating the trench; 9. an inter-trench dielectric layer; 10. a surface dielectric layer; 11. a carrier; 12. a temporary adhesive; 13. a bottom of the pixel isolation; 14. a remaining silicon layer; 15. metal connection; 16. a dielectric passivation layer; 17. a silicon control and readout circuitry wafer; 18. an interconnect layer; 19. an anti-reflection layer; 20. a filter layer; 21. and a lens layer.

Detailed Description

The technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiment of the present invention. It is obvious that the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention. Additionally, the scope of the present invention should not be limited to the particular structures or components described below or to the particular parameters.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or assembly referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

The utility model provides an image sensor, it obtains through making and integrating germanium p-i-n photodiode the utility model discloses an image sensor, it is through with hydrogen ion (H) ⁺ ) Implanting a germanium donor wafer to a selected depth to determine a thickness of a germanium transfer layer; separating the germanium transfer layer from the germanium donor wafer by beta bonding the surfaces of the germanium donor wafer and the silicon target wafer to obtain a germanium-silicon mixed wafer; grinding the surface of the germanium transfer layer of the SiGe mixed wafer to dope the surface with boron ions (B) ⁺ ) Implanting a germanium transfer layer at the top of the germanium-silicon mixed crystal dome part, and implanting boron into the part of the germanium transfer layer close to the surface to form a doped germanium layer; pixel-to-pixel isolation structures are formed in the germanium photodiode layer to define photodiode regions. The utility model has the advantages of low cost, the technique of manufacturing is simpler relatively, image sensor is for having high-speed reading, little pixel size, CMOS compatible shortwave infrared image sensor (having the focal plane array), the utility model discloses image sensor is suitable for the industrialization large-scale production.

The utility model discloses image sensor is based on image sensor that germanium p-i-n photodiode made, and it includes silicon control and reading circuit wafer, dielectric passivation layer, germanium photodiode layer, antireflection coating and lens layer from bottom to top in proper order; the germanium photodiode layer is of a laminated structure and sequentially comprises a residual silicon layer, an undoped germanium layer and a doped germanium layer from bottom to top, wherein the undoped germanium layer is an intrinsic layer; a dielectric passivation layer is deposited on the outwardly facing surface of the remaining silicon layer.

The image sensor of the present invention will be further described with reference to the accompanying drawings.

Referring to fig. 17, the image sensor of the present invention is an image sensor manufactured based on a ge p-i-n photodiode, and sequentially includes, from bottom to top, a silicon control and readout circuit wafer 17, a dielectric passivation layer 16, a ge photodiode layer 7, an anti-reflection layer 19, and a lens layer 21. The germanium photodiode layer 7 is of a laminated structure and sequentially comprises a residual silicon layer 14, an undoped germanium layer 6 and a doped germanium layer 5 from bottom to top, wherein the undoped germanium layer 6 is an intrinsic layer; the residual silicon layer 14 is an n-type region, and the doped germanium layer 5 is a p-type region; in further embodiments, the remaining silicon layer 14 is a p-type region and the doped germanium layer 5 is an n-type region. The germanium photodiode layer 7 further includes an inter-trench dielectric layer 9 disposed through the stacked structure of the germanium photodiode layer 7, and the inter-trench dielectric layer 9 divides the germanium photodiode layer 7 into a plurality of independent pixel regions. In each individual pixel region, two metal connections 15 are provided from bottom to top on the dielectric passivation layer 16 and the germanium photodiode layer 7, a first metal connection being connected to the remaining silicon layer 14 and a second metal connection being connected to the doped germanium layer 5. On top of the silicon control and readout circuitry wafer 17 is an interconnect layer 18 with circuitry, the circuitry of the interconnect layer 18 being connected to two metal connections 15.

Preferably, a filter layer 20 is further provided between the antireflection layer 19 and the lens layer 21, which filter layer can selectively transmit incident light of a specific wavelength range while absorbing the remaining light.

The method of the present invention for manufacturing and integrating a germanium p-i-n photodiode into an image sensor structure can be divided into two types according to the upper and lower sequence of a p-type region and an n-type region in the germanium p-i-n photodiode, and it can be understood that the basic process principles of the two types are the same. A method a (referred to as "method a") for fabricating and integrating a germanium p-i-n photodiode into an image sensor structure is described in detail with reference to fig. 1 to 17.

Method a, boron doped germanium (p-type region) on top, doped germanium layer 5 being p-type region, the doping element ions implanted into the germanium being boron ions (B) ⁺ ) The remaining silicon layer 14 is an n-type region. Comprises the following steps.

In step S1, a germanium donor wafer 1 is provided. FIG. 1 is a schematic diagram illustrating steps S1-S2. In a preferred embodiment, the germanium donor wafer 1 is cleaned and dried, and then the surface of the germanium donor wafer 1 is polished by a chemical mechanical polishing process, wherein the chemical mechanical polishing process comprises polishing the surface of the germanium donor wafer by using a polishing solution with a certain pH value; the pH value of the polishing liquid is preferably 7 to 11, and more preferably 9. During the grinding process, according to the grinding progress and the flatness of the plane of the germanium donor wafer 1, the grinding progress is controlled by adjusting the flow rate of the grinding liquid and applying a pH value adjusting liquid, wherein the pH value adjusting liquid is preferably deionized water. The chemical mechanical polishing equipment for the germanium donor wafer comprises a polishing turntable, a polishing pad, a polishing liquid nozzle and a pH value adjusting liquid nozzle, wherein the polishing turntable is used for fixing the germanium donor wafer to be polished and providing rotary power for the germanium donor wafer to be polished; the grinding pad is used for mechanically removing the surface layer of the germanium donor wafer to be ground in the relative motion with the germanium donor wafer to be ground; the grinding fluid nozzle is arranged above the grinding pad and used for injecting grinding fluid with a certain pH value onto the grinding pad; the pH value adjusting liquid nozzle is arranged close to the grinding liquid nozzle and is used for injecting the pH value adjusting liquid onto the grinding pad and mixing the pH value adjusting liquid and the grinding liquid with a certain pH value on the grinding pad to form grinding liquid with a second pH value; and the pH value adjusting liquid nozzle is also provided with a flow controller for adjusting the flow of the pH value adjusting liquid so as to adjust the second pH value to a target pH value. And flow controllers are arranged on the pH value adjusting liquid nozzle and the grinding liquid nozzle and are respectively used for adjusting the flow of the pH value adjusting liquid and the flow of the grinding liquid so as to adjust the second pH value to the target pH value. The chemical mechanical polishing equipment further comprises a pH value detector for detecting the pH value of the polishing liquid on the polishing pad.

Step S1 of providing the germanium donor wafer 1 further includes depositing a thin layer of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon dioxide (SiO) on the germanium donor wafer 1 ₂ ) Film, silicon dioxide (SiO) ₂ ) The film thickness is between 10nm and 90nm (nanometers) to protect the surface of the germanium donor wafer 1 during the hydrogen ion implantation of the subsequent step (step S2), and the silicon dioxide film can be removed after the hydrogen ion implantation. The masking film may be silicon nitride or Al ₂ O ₃ Or a photoresist.

Step S2, hydrogen ion (H) ⁺ ) The germanium donor wafer 1 is implanted to a selected depth to determine the thickness of the germanium transfer layer 2 (i.e., the germanium film to be transferred). As shown in fig. 2.

In some embodiments, the hydrogen ion implantation may be performed by beam line ion implantation or plasma immersion ion implantation under the following conditions: dosage range: 1X 10 ¹⁵ Atom/cm ² ～1×10 ¹⁸ Atom/cm ² (preferred is>10 ¹⁶ Atom/cm ² ) (ii) a Energy range: 1keV to 1MeV (typically about 50 keV); temperature range: room temperature (e.g., 25 degrees Celsius) to 600 degrees Celsius (preferred)<400 degrees celsius to minimize escape of implanted particles by diffusion); selected depth accuracy: 0.03 microns to 0.05 microns.

Optionally, a layer of amorphous germanium (a-Ge) may be deposited (e.g., by Physical Vapor Deposition (PVD)) on top of the formed region of germanium transfer layer 2. Fig. 2 is a schematic diagram showing a state after step S2.

Step S3, providing a silicon target wafer 3 (n-type); preferably, the surface of the silicon target wafer is polished by using a chemical mechanical polishing process or apparatus in step S1, or by using a chemical mechanical polishing process or apparatus similar to that in step S1. FIG. 3 is a schematic diagram illustrating steps S3-S4.

If an amorphous germanium layer is deposited in step S2, it is further preferred that an amorphous germanium layer also be deposited on the surface of the silicon target wafer 3 (e.g. by physical vapour deposition), so that during the following steps S5 and S6 the combined amorphous germanium layer will be converted to crystalline germanium (c-Ge), thereby promoting bonding between the germanium donor wafer 1 and the silicon target wafer 3.

Step S4, beta bonds the surfaces of the germanium donor wafer 1 and the silicon target wafer 3. Wherein, a cleaning step is required before beta bonding, so as to remove the oxide on the surface. Performing ultrasonic cleaning on the surface of the germanium wafer by adopting acetone, methanol/ethanol and deionized water; in a preferred embodiment, deionized water and H are used ₂ O ₂ Further cleaning the diluent according to the proportion of (15-30): 1, preferably adopting the diluent with the proportion of 20: 1; then, deionized water and HF are used for diluting according to the dilution ratio of (30-70) to 1, preferably according to the dilution ratio of 50: 1; finally, diluted H is used according to the proportion of (15-30): 1 ₂ O ₂ The dilution is cleaned again, preferably at a 20:1 ratio. In a preferred embodiment, RCA-I solution and RCA-II solution are sequentially cleaned on the surface of a silicon wafer, followed by H ₂ O2-H ₂ SO ₄ Cleaning the cleaning liquid; after cleaning, the remaining liquid or particles on the wafer surface are removed with a dryer. In another embodiment, the cleaning process may be replaced by immersing the wafer in hydrofluoric acid.

The beta bonding process is also called self-bonding process, etc., and the method includes the first method or the second method, specifically for example:

method one, the low temperature bonding process, includes a low temperature thermal step that presses the cleaned and/or activated surfaces together at moderate pressure, preferably 0.5MPa to 2.0MPa, to ensure that the injected particles (hydrogen ions or microbubbles) do not initiate fracture, or diffuse or outgas. This weak bonding is caused by electrostatic interactions (van der waals forces).

The second method is plasma cleaning activation, using Ar and N ₂ 、NH ₃ 、Ne、H ₂ O、O ₂ The plasma of (2) strikes the silicon target wafer 3, the plasma activates the wafer surface (creating dangling bonds on the wafer surface), and then the activated silicon target wafer 3 surface is attached to the surface of the germanium donor wafer 1, and pressure is applied to the wafer to cause self-bonding at the layer-to-layer interface.

Step S5, the germanium transfer layer 2 (bonded to the silicon target wafer 3) is separated from the germanium donor wafer 1 (i.e. delaminated using thermal, mechanical or other suitable techniques) to obtain a germanium-silicon hybrid wafer 4 (i.e. a hybrid wafer composed of the germanium transfer layer 2 and the silicon target wafer 3). Fig. 4 is a schematic diagram of step S5.

Among them, the lift-off method is, for example, a selective lift-off energy placement step, and the selective lift-off energy placement method specifically adopts an energy pulse technology, and the energy pulse is that a local (small range) energy pulse is provided, such as a heat source (e.g., laser, heating lamp), a heat source and a mechanical source, so as to realize, for example, a twist lift-off; specifically heating (e.g., heating with a heat source at about 350 degrees celsius) or cooling or differentially heating or differentially cooling one side of the substrate (germanium donor wafer 1 or silicon target wafer 4). In another embodiment, the stripping process further comprises, as an ion implantation bubble separation step, specifically, the step of introducing hydrogen ions (H) ⁺ ) Implanting a germanium donor wafer 1, wherein implanted hydrogen ions capture electrons to form hydrogen, the hydrogen forms a micro-bubble layer in the bubble layer and is parallel to a cleavage plane (a crystal cleavage plane), and heating the germanium-silicon mixed wafer 4 and stripping along the cleavage plane; wherein the cleaning step and the self-bonding process can be referred to the process in beta bonding as described above.

Optionally, the separated germanium donor wafer 1 can be reused after polishing (chemical mechanical polishing (CMP)) and cleaning the surface; that is, a germanium donor wafer 1 is repeatedly used as the raw material in step S2 to form a germanium transfer layer 2 until the thickness is too thin to be used.

Step S6, completing final bonding of the sige mixed wafer 4.

The final bonding step employs the following bonding steps, for example: bonding step method one, the annealing bonding step, lasts for several hours in a process environment of less than or equal to 400 degrees celsius, preferably 3 hours in a process environment of 300 degrees celsius. Bonding step method two, apply voltage bonding step, apply voltage in order to set up the electric current through mixing the crystal defect that the crystal defect introduced in the wafer, the electric current heats and causes the bonding between the wafers, preferably use the local heating of interface (increase the series resistance) to bond.

Step S7 is to polish the surface of the germanium transfer layer 2 of the sige mixed wafer 4. The polishing is, for example, chemical mechanical polishing, and specifically, the slurry contains a mild abrasive such as borosilicate glass, titanium dioxide, titanium nitride, aluminum oxide, aluminum trioxide, ferric nitrate, cerium oxide, silicon dioxide (colloidal silica or fumed (micro powder) silica), silicon nitride, silicon carbide, graphite, diamond, and an oxidizing agent (mixed in deionized water) such as H ₂ O ₂ 、KIO ₃ And ferric nitrate.

Optionally, after grinding, a thin plasma enhanced chemical vapor deposition silicon dioxide film may be deposited on germanium transfer layer 2 on top of silicon germanium hybrid wafer 4 to protect the surface of germanium transfer layer 2 during subsequent boron ion implantation, and this silicon dioxide film may be removed after boron ion implantation.

Step S8, doping element ion boron ion (B) ⁺ ) The germanium transfer layer 2 on top of the sige-si hybrid wafer 4 is implanted so that the portion of the germanium transfer layer 2 near the surface is implanted with boron to form a doped ge layer 5 (p-type region) and the remaining portion (the portion near the silicon target wafer 3) is an undoped ge layer 6 (boron ions cannot reach and therefore no boron is present, being an intrinsic region). Followed by annealing toThe dopants are activated. Fig. 5 is a schematic diagram of step S8. The dopants, also referred to as dopants, implants, etc., are implanted boron atoms.

Fig. 6 and 7 are schematic diagrams illustrating step S9, fig. 6 is a schematic diagram illustrating a state after step S9.1 is completed, and fig. 7 is a schematic diagram illustrating a state after step S9.3 is completed. Note that fig. 7 to 17 are each an enlarged view of a single pixel region, for example, a portion shown in fig. 6 a.

In step S9, pixel-to-pixel isolation structures are formed in the ge photodiode layer 7 to define photodiode regions (i.e., photodiode arrays, i.e., pixel regions). As shown in fig. 6, the ge photodiode layer 7 is a doped ge layer 5, an undoped ge layer 6 and a portion of the target silicon wafer 3, which are connected in sequence, i.e., a portion corresponding to the ge p-i-n photodiode layer formed in the subsequent step.

Step S9 further includes:

step S9.1, forming an isolation pattern and forming an isolation trench 8 by etching to define (divide) each pixel region; for example, if the shape of the pixel to be constituted is a square, the isolation pattern resembles a square grid; patterning the mesh using a photolithography method, and then etching to generate an isolation trench 8;

step S9.2, filling the isolation trench 8 with a flowable dielectric material (e.g., polyimide) to form an inter-trench dielectric layer 9;

step S9.3, the flowable dielectric material is excessively filled to fill the isolation trench 8 and then overflow to cover the pixel region, thereby forming the surface dielectric layer 10.

FIG. 8 is a schematic diagram illustrating steps S10-S11.

Step S10, turn over the sige mixed wafer 4.

In step S11, a carrier 11 coated with a temporary bonding agent 12 is provided. The temporary bonding adhesive 12(temporary bonding adhesive) may be bonded or adhered by any conventional method.

Fig. 9 is a schematic diagram showing a state after completion of step S12.

Step S12, the sige mixed wafer 4 (the side with the flowable dielectric material) is temporarily bonded to the carrier 11 by the temporary bonding agent 12.

Fig. 10 is a schematic diagram showing a state after step S13 is completed.

In step S13, most of the silicon target wafer 3 (n-type) is removed by grinding (e.g., chemical mechanical grinding or etching (e.g., wet etching) or other suitable technique) to the bottom 13 of the pixel isolation. Thus, a remaining silicon layer 14 (n-type region) is formed (remains) on top of the undoped germanium layer 6, the remaining silicon layer 14, the undoped germanium layer 6 and the doped germanium layer 5, which are connected in series, together forming a germanium p-i-n photodiode layer (i.e. a germanium photodiode layer 7). The bottom 13 of the pixel isolation refers to a level corresponding to an end of the inter-trench dielectric layer 9 away from the surface dielectric layer 10, i.e., a level corresponding to a polished surface of the remaining silicon layer 14 that is retained according to requirements/process requirements.

Fig. 11 is a schematic diagram showing a state after completion of step S14.

In step S14, a dielectric passivation layer 16 is deposited on the outward facing surface of the remaining silicon layer 14.

Fig. 12 is a schematic diagram showing a state after completion of step S15.

Step S15 is to separately form metal connections 15 to the remaining silicon layer 14 (n-type region) and the doped germanium layer 5 (p-type region), respectively.

Step S15 further includes:

step S15.1, metal connection patterns are formed and vias are etched to the remaining silicon layer 14 (n-type region) and the doped germanium layer 5 (p-type region). A Barrier Metal (BM) and copper (Cu) seed are formed on the sidewalls of the via by Physical Vapor Deposition (PVD), and the via is filled by copper electrochemical deposition to form a metal connection 15.

Step S15.2, the surface is polished (e.g. by chemical mechanical polishing) to remove excess copper and expose the copper pad and dielectric field, so that the metal connection 15 is flush with the dielectric passivation layer 16. Wherein the dielectric passivation layer 16 may be thinned after the chemical mechanical polishing.

At step S16, alignment marks are formed (by any suitable technique) on the outwardly facing surface of the dielectric passivation layer 16.

FIG. 13 is a schematic diagram illustrating steps S17-S18.

In step S17, the silicon control and readout circuitry wafer 17 is provided.

Wherein the silicon control and readout circuitry wafer 17 has control, readout and/or other suitable circuitry for the germanium p-i-n photodiode array layer (i.e., the germanium photodiode layer 7), the p-i-n photodiode array layer (i.e., the germanium photodiode layer 7) is provided adjacent the silicon control and readout circuitry wafer 17, the surface adjacent the outer side is an interconnect layer 18 having circuitry, and the outward facing surface of the interconnect layer 18 is the surface formed after chemical mechanical polishing of the copper and barrier metal, i.e., the surface on which the outside of the circuit metal contacts (copper pads) are exposed, is an interconnect layer 18 with circuitry, and the outward facing surface of the interconnect layer 18 is the surface formed by chemical mechanical polishing of the copper and barrier metal, i.e., the surface exposed with the circuit metal contacts (copper pads).

And, step S17 further includes:

in step S17.1, alignment marks are formed (by any suitable technique) on the outward facing surface of the interconnect layer 18. This alignment mark matches the alignment mark formed on the surface of the dielectric passivation layer 16 in step S16, so that the effect of assisting alignment is achieved in the subsequent combination.

Step S18 is to interface the outward facing surface of the interconnect layer 18 of the silicon control and readout circuitry wafer 17 with the outward facing surface of the dielectric passivation layer 16 of the ge photodiode layer 7 (temporarily bonded to the carrier 11), and to connect the metal connections 15 of the ge photodiode layer 7 to the circuitry of the interconnect layer 18 by alignment marks on both to ensure alignment. And bonding, such as mixed bonding (copper-copper bonding and oxide-oxide bonding) is performed between the two. The copper-copper bonding process is a process in which the upper copper pad and the lower copper pad (the interface of the two copper portions where the metal connection 15 and the circuit of the interconnect layer 18 are butted) are connected by interdiffusion of copper during the copper grain growth.

In order for the device to function, the metal connections 15 of the germanium photodiode layer 7 and the circuitry of the interconnect layer 18 of the silicon control and readout circuitry wafer 17 must be aligned with (in circuit communication with) each other. For this purpose, at least one set of alignment marks is provided, which are highly precise features and are used as a reference for the combined positioning. The alignment marks can be set according to the prior art, and thus are not described in detail herein.

Fig. 14 is a diagram illustrating a state after completion of step S18.

In step S19, annealing is performed to complete bonding. The oxide-oxide bonding process is annealing, which links the upper and lower dielectric fields (connecting interconnect layer 18 and dielectric passivation layer 16) by a dehydration condensation reaction.

In step S20, laser bond/debonding is performed to remove the carrier 11.

Fig. 15 is a schematic diagram showing a state after completion of step S20.

In step S21, the surface dielectric layer 10 is removed by grinding (by, for example, chemical mechanical grinding or other suitable techniques). That is, the flowable dielectric material is removed from the surface portion of the pixel area (with the inter-trench dielectric layer 9 still present) leaving the doped germanium layer 5 exposed at the surface.

Fig. 16 is a diagram illustrating a state after completion of step S21.

In step S22, an anti-reflection layer 19 is deposited on the surface (the surface formed by the doped germanium layer 5 and the inter-trench dielectric layer 9).

In step S23, a lens layer 21 is formed on top of the antireflection layer 19.

Preferably, a filter layer 20 is also formed on top of the antireflection layer 19 and between the lens layer 21.

Fig. 17 is a schematic diagram of a state after completion of steps S22 and S23 in the preferred embodiment, that is, a structural diagram of a final product.

Method B, phosphorus doped germanium (n-type region) on top, doped germanium layer 5 being n-type region, the doping element ions implanted into the germanium being phosphorus ions (P) ⁺ ) The remaining silicon layer 14 is a p-type region.

The only difference from method a is that the silicon target wafer 3 provided in step S3 is p-type, so that the remaining silicon layer 14 is a p-type region; the doping element ions implanted in step S8 are phosphorus ions (P) ⁺ ) The doped germanium layer 5 formed is an n-type region, which isThe rest of the process and the operation process are the same as those of the method A.

As is well known in the art, doping a group iii element (e.g., boron) with a group iv element (e.g., germanium) forms a p-type semiconductor; doping an element of group v (e.g., phosphorus) with an element of group iv (e.g., germanium) forms an n-type semiconductor. It is therefore apparent that these similar variations are obtained by method a of the present invention described in detail above.

To sum up, the utility model discloses high-speed, little pixel size, CMOS compatible shortwave infrared image sensor (have focal plane array) have been realized to low cost, the simpler manufacturing process relatively, are suitable for the industrialization large-scale production. Simultaneously, adopt the utility model discloses an image sensor that the method was made is lower, sensitivity is higher from the dark current of visible light to shortwave infrared wavelength. Furthermore, in the method of the present invention, the germanium donor wafer can be repeatedly used to generate more germanium transfer layers, so that the resource utilization rate is higher and the manufacturing cost is lower.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the present invention. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. The image sensor is characterized by being manufactured based on a germanium p-i-n photodiode and sequentially comprising a silicon control and reading circuit wafer, a dielectric passivation layer, a germanium photodiode layer, an anti-reflection layer and a lens layer from bottom to top; the germanium photodiode layer is of a laminated structure and sequentially comprises a residual silicon layer, an undoped germanium layer and a doped germanium layer from bottom to top, wherein the undoped germanium layer is an intrinsic layer; a dielectric passivation layer is deposited on the outwardly facing surface of the remaining silicon layer.

2. The image sensor of claim 1, wherein the germanium photodiode layer further comprises an inter-trench dielectric layer disposed through the germanium photodiode layer stack, the inter-trench dielectric layer dividing the germanium photodiode layer into a plurality of independent pixel regions.

3. The image sensor of claim 1, wherein two metal connections are disposed from bottom to top on the dielectric passivation layer and the germanium photodiode layer in each individual pixel region, a first metal connection being connected to the remaining silicon layer and a second metal connection being connected to the doped germanium layer.

4. The image sensor of claim 3, wherein the metal connection is flush with the dielectric passivation layer.

5. An image sensor as claimed in claim 4, characterized in that an alignment mark is provided on an outwardly facing surface of the dielectric passivation layer.

6. The image sensor of claim 4, wherein the outwardly facing surface of the interconnect layer of the silicon control and readout circuitry wafer is in abutment with the outwardly facing surface of the dielectric passivation layer of the germanium photodiode layer temporarily bonded to the carrier, and wherein the metallic connections of the germanium photodiode layer are connected to the circuitry of the interconnect layer by alignment marks on the outwardly facing surface of the interconnect layer of the silicon control and readout circuitry wafer and the outwardly facing surface of the dielectric passivation layer of the germanium photodiode layer temporarily bonded to the carrier ensuring that the outwardly facing surface of the interconnect layer of the silicon control and readout circuitry wafer is aligned with the outwardly facing surface of the dielectric passivation layer of the germanium photodiode layer temporarily bonded to the carrier.

7. The image sensor of claim 6, further comprising a filter layer between the anti-reflective layer and the lens layer.

8. The image sensor as in claim 7, wherein an anti-reflection layer is deposited on the surface of the doped germanium layer and the inter-trench dielectric layer.