CN217062077U - Packaging structure - Google Patents

Packaging structure Download PDF

Info

Publication number
CN217062077U
CN217062077U CN202220228621.5U CN202220228621U CN217062077U CN 217062077 U CN217062077 U CN 217062077U CN 202220228621 U CN202220228621 U CN 202220228621U CN 217062077 U CN217062077 U CN 217062077U
Authority
CN
China
Prior art keywords
sensor
semiconductor wafer
control unit
back surface
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202220228621.5U
Other languages
Chinese (zh)
Inventor
刘尧青
郭亚
刘海东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Memsic Semiconductor Wuxi Co Ltd
Original Assignee
Memsic Semiconductor Wuxi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memsic Semiconductor Wuxi Co Ltd filed Critical Memsic Semiconductor Wuxi Co Ltd
Priority to CN202220228621.5U priority Critical patent/CN217062077U/en
Application granted granted Critical
Publication of CN217062077U publication Critical patent/CN217062077U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The utility model provides a packaging structure, it includes: a semiconductor wafer having a back surface opposite to the front surface thereof and a back surface located above the front surface thereof; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor; a first rewiring layer is arranged on the back surface of the semiconductor wafer, and is led out from a control unit of the sensor through the through hole and redistributed to the back surface of the semiconductor wafer; a plurality of sensor devices distributed over the first redistribution layer, each sensor device bonded to the back side of the semiconductor wafer, and a signal contact of each sensor device connected to the first redistribution layer. Compared with the prior art, the utility model discloses it is inside integrated a packaging body with a plurality of sensors and the control unit to make the integrated level of product higher, the processing cost is lower.

Description

Packaging structure
[ technical field ] A
The utility model relates to an integrated form sensor technical field especially relates to an integrated packaging structure of wafer level system with multisensor and the fusion of the control unit.
[ background ] A method for producing a semiconductor device
With the development of the technology of the internet of things, the application of the sensor is more and more extensive, and meanwhile, new requirements are put forward for the sensor technology. At present, most sensors and control units are independently packaged and further integrated at an application end according to actual application; the method requires a packaging end production line to independently control different products, has long packaging period, high packaging cost, low material utilization rate and large environmental pollution, and simultaneously causes overlarge occupied area of a sensor and a control unit at an application end, which is contrary to the development of semiconductor packaging towards light, thin, short and small directions.
Therefore, a new technical solution is needed to overcome the above technical problems.
[ Utility model ] A method for manufacturing a semiconductor device
An object of the utility model is to provide a packaging structure, it is through integrating a plurality of sensors and the control unit inside a packaging body to make the integrated level of product higher, the processing cost is lower.
According to an aspect of the utility model, the utility model provides an encapsulation structure, it includes: a semiconductor wafer having a back surface opposite to the front surface thereof and a back surface located above the front surface thereof; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor; a first rewiring layer is arranged on the back of the semiconductor wafer, and the first rewiring layer is led out from the control unit of the sensor through the through hole and redistributed to the back of the semiconductor wafer; a plurality of sensor devices distributed over the first redistribution layer, each of the sensor devices bonded to the back side of the semiconductor wafer and having signal contacts connected to the first redistribution layer.
Compared with the prior art, the utility model integrates the multiple sensors (not limited to 2) and the control unit into one package body through system integration packaging, on one hand, the processing period of the product can be shortened, and the processing cost is reduced; on the other hand, the product has higher integration level, reduces the packaging volume and has wider application prospect.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor. Wherein:
fig. 1 is a schematic longitudinal sectional view of a package structure according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating a packaging method of the package structure according to an embodiment of the present invention;
fig. 3-9 are schematic longitudinal cross-sectional views corresponding to the steps shown in fig. 2 according to an embodiment of the present invention.
[ detailed description ] embodiments
In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with at least one implementation of the invention is included. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless otherwise specified, the terms connected, and connected as used herein mean electrically connected, directly or indirectly.
Based on the problem that exists among the above-mentioned background art, the utility model discloses fuse multisensor (being not limited to multiple sensors such as accelerometer, gyroscope, magnetic sensor) and the control unit, do the integrated encapsulation of system, demand that satisfies the market that can be better.
Fig. 1 is a schematic longitudinal cross-sectional view of a package structure according to an embodiment of the present invention, which integrates a plurality of sensor devices and a sensor control unit into a package. The package structure shown in fig. 1 comprises a semiconductor wafer 1, a plurality of sensor devices 2, 3 and a molding compound 106. After the semiconductor wafer level package (or system integration package) is passed, a semiconductor wafer dicing step is performed to form a plurality of mutually independent package structures, i.e., independent chips. The semiconductor wafer 1 is a separate semiconductor wafer in a view before the semiconductor wafer is cut, i.e. in a view at the semiconductor wafer level (i.e. wafer level), and the semiconductor wafer 1 can be understood as a wafer of the semiconductor wafer in a view after the semiconductor wafer is cut, i.e. in a view at the chip level.
For ease of description, only two sensor devices 2, 3 are shown in the embodiment shown in fig. 1, and in practice, there may be more sensor devices in the present invention.
The back side of the semiconductor wafer 1 is opposite to the front side thereof, and the back side of the semiconductor wafer 1 is located above the front side thereof. The front side (i.e., circuit side) of the semiconductor wafer 1 is provided with a control unit (which includes a control circuit and a memory circuit of a sensor) 102 of the sensor and metal pads 103; a through hole 101 is formed in the semiconductor wafer 1, and the through hole 101 extends downwards from the back surface of the semiconductor wafer 1 to a control unit 102 of the sensor; the back surface (namely the non-circuit surface) of the semiconductor wafer 1 is provided with a first rewiring layer 105, and the first rewiring layer 105 is led out from the control unit 102 of the sensor through the through hole 101 and is redistributed to the back surface of the semiconductor wafer 1, so that the signals of the through hole 101 are redistributed on the back surface of the semiconductor wafer 1.
In the specific embodiment shown in fig. 1, the metal pads 103 are located below the control unit 102 of the sensor (or the metal pads 103 are closer to the front side of the semiconductor wafer 1 than the control unit 102 of the sensor); the first rewiring layer 105 is protected by a passivation layer 104; the via 101 is a through silicon via formed based on a deep silicon via technique.
The sensor devices 2, 3 are distributed over the first redistribution layer 105, each sensor device 2, 3 is bonded to the back surface of the semiconductor wafer 1, and the signal contact of each sensor device 2, 3 is connected to the first redistribution layer 105. In one embodiment, the sensor devices 2, 3 are bonded to the semiconductor wafer 1 by a flip-chip, reflow process.
In the specific embodiment shown in fig. 1, the sensor device 2 is a WLP (Wafer Level Packaging) based sensor device, and includes a substrate 201, a sensor structure layer 202, a sensor structure protective cover 203, a redistribution layer 204, and a metal bump 205, which are sequentially stacked; the sensor device 3 is a WLP-based sensor device, and includes a substrate 301, a sensor structure layer 302, a sensor structure protection cover 303, a redistribution layer 304, and a metal bump 305, which are sequentially stacked. Wherein the metal bumps 205, 305 are signal contacts of the sensor devices 2, 3 connected to the first redistribution layer 105; sensor structure layer 202 and sensor structure layer 302 each include a fixed structure at the edge of the chip and a movable structure in the middle of the chip.
It should be noted that the plurality of sensor devices 2 and 3 of the present invention may be the same type of sensor device or different types of sensor devices. The sensor devices 2 and 3 can be processed and manufactured by using sensor devices in the prior art, so the specific structures of the sensor devices 2 and 3 are not described herein again.
The integrated semiconductor wafer 1 and the plurality of sensor devices 2, 3 are subjected to plastic packaging using a plastic packaging material 106 through a plastic packaging process to form a package body. In one embodiment, the plastic packaging process is an injection molding or compression molding process.
And (3) realizing ball planting on the metal bonding pad 103 on the front surface of the semiconductor wafer 1 after plastic packaging through a ball planting process, namely arranging a solder ball 107 on the metal bonding pad 103 on the front surface of the semiconductor wafer 1 after plastic packaging.
Please refer to fig. 2, which is a schematic flow chart illustrating a packaging method of a package structure according to an embodiment of the present invention; please refer to fig. 3-9, which are schematic longitudinal sectional views corresponding to the steps shown in fig. 2 according to an embodiment of the present invention. The packaging method of the package structure shown in fig. 2 includes the following steps.
Step 210, as shown in fig. 3, providing an initial wafer 11, wherein the back surface of the initial wafer 11 is opposite to the front surface thereof, and the back surface of the initial wafer 11 is located above the front surface thereof; the front side (i.e. circuit side) of the initial wafer 11 is provided with a control unit of a sensor (which includes a control circuit and a memory circuit of the sensor) 102 and a metal pad 103; the initial wafer 11 is provided with a through hole 101 therein, the through hole 101 is located above the control unit 102 of the sensor, one end of the through hole 101 is at a predetermined distance from the back surface of the initial wafer 11, and the other end thereof extends to the control unit 102 of the sensor. In the specific embodiment shown in fig. 1, the metal pads 103 are located below the control unit 102 of the sensor (or the metal pads 103 are closer to the front side of the initial wafer 11 than the control unit 102 of the sensor); the via 101 is a through-silicon via formed based on a deep silicon via technique.
Step 220, as shown in fig. 4, thinning the back surface of the initial wafer 11 by a thinning process, so that the through hole 101 is exposed at the back surface (i.e., non-circuit surface) of the thinned initial wafer 11, thereby obtaining the semiconductor wafer 1. That is, the back surface of the semiconductor wafer 1 is opposite to the front surface thereof, and the back surface thereof is located above the front surface thereof; the front surface of the semiconductor wafer 1 is provided with a control unit 102 and a metal pad 103 of a sensor; the semiconductor wafer 1 is internally provided with a through hole 101, and the through hole 101 extends downwards from the back surface of the semiconductor wafer 1 to a control unit 102 of the sensor.
Step 230, as shown in fig. 5, by a rewiring process, a first rewiring layer 105 is disposed on the back side of the semiconductor wafer 1 (i.e., the back side of the thinned initial wafer 11), and the first rewiring layer 105 is led out from the control unit 102 of the sensor through the through hole 101 and redistributed to the back side of the semiconductor wafer 1, so that the signal of the through hole 101 is redistributed on the back side of the semiconductor wafer 1. In the embodiment shown in fig. 5, the first redistribution layer 105 is protected by the passivation layer 104.
Step 240, as shown in fig. 6, provides sensor device 2 and sensor device 3. In the specific embodiment shown in fig. 6, the sensor device 2 is a WLP (Wafer Level Packaging) based sensor device, and includes a substrate 201, a sensor structure layer 202, a sensor structure protection cover 203, a redistribution layer 204, and a metal bump 205, which are sequentially stacked; the sensor device 3 is a WLP-based sensor device, and includes a substrate 301, a sensor structure layer 302, a sensor structure protection cover 303, a redistribution layer 304, and a metal bump 305, which are sequentially stacked. The sensor structure layer 202 and the sensor structure layer 302 each include a fixed structure located at the edge of the chip and a movable structure located in the middle of the chip.
Step 250, as shown in fig. 7, the sensor devices 2 and 3 are placed above the first redistribution layer 105, each sensor device 2 and 3 is bonded to the back side of the semiconductor wafer 1, and the signal contact of each sensor device 2 and 3 is connected to the first redistribution layer 105 to form a wafer structure. In the embodiment shown in fig. 7, the sensor devices 2 and 3 are bonded to the semiconductor wafer 1 by a flip-chip, reflow process. In the embodiment shown in fig. 7, the metal bumps 205, 305 are signal contacts of the sensor devices 2, 3 connected to the first redistribution layer 105.
Step 260, as shown in fig. 8, the bonded wafer structure (i.e. the integrated semiconductor wafer 1 and the plurality of sensor devices 2 and 3) is subjected to plastic packaging by using the plastic packaging material 106 through a plastic packaging process to form a package body. In one embodiment, the plastic packaging process is an injection molding or compression molding process.
In step 270, as shown in fig. 9, solder balls 107 are formed on the metal pads 103 on the front surface of the semiconductor wafer 1 in the wafer structure after the molding by the ball mounting process.
For ease of description, only two sensor devices 2, 3 are shown in the embodiment shown in fig. 3-9, and in practice, there may be more sensor devices in the present invention. It should be noted that the plurality of sensor devices 2 and 3 of the present invention may be the same type of sensor device or different types of sensor devices. The sensor devices 2 and 3 may be processed by using a sensor device process in the prior art, and therefore, the specific structures of the sensor devices 2 and 3 are not described herein again.
To sum up, the utility model integrates the multiple sensors (not limited to 2) 2 and 3 and the sensor control unit 102 into one package body through system integration and packaging, so that on one hand, the processing period of the product can be shortened, the processing cost is reduced, and the material utilization rate is improved; on the other hand, the sensing unit and the control unit are integrated into a package body in a wafer-level system integration mode, and the sensing unit and the control unit can be used as independent system modules at an application end, so that the wafer-level system integration method has a wider prospect.
In the present invention, the terms "connected", "connecting", and the like denote electrical connections, and, unless otherwise specified, may denote direct or indirect electrical connections.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment, but all equivalent modifications or changes made by those skilled in the art according to the present invention should be included in the protection scope of the claims.

Claims (5)

1. A package structure, comprising:
a semiconductor wafer having a back surface opposite to the front surface thereof and a back surface above the front surface thereof; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor; a first rewiring layer is arranged on the back surface of the semiconductor wafer, and the first rewiring layer is led out from a control unit of the sensor through the through hole and redistributed to the back surface of the semiconductor wafer;
a plurality of sensor devices distributed over the first redistribution layer, each of the sensor devices bonded to the back side of the semiconductor wafer and having a signal contact connected to the first redistribution layer.
2. The package structure of claim 1,
the control unit of the sensor comprises a control circuit and a storage circuit of the sensor;
the sensor device is a wafer level package based sensor device;
the plurality of sensor devices are the same kind of sensor device or different kinds of sensor devices.
3. The package structure of claim 2,
the through hole is a silicon through hole formed based on a deep silicon etching hole technology;
the sensor device is bonded with the semiconductor wafer through a flip chip and reflow process.
4. The package structure of claim 1,
the sensor device comprises a substrate, a sensor structure layer, a sensor structure protective cover, a rewiring layer and metal bumps which are sequentially stacked;
the metal bumps are signal contacts in the sensor device connected with the first rewiring layer.
5. The package structure of claim 1, further comprising:
the solder balls are arranged on the metal bonding pads on the front surface of the semiconductor wafer;
and the plastic packaging material is used for carrying out plastic packaging on the integrated semiconductor wafer and the plurality of sensor devices.
CN202220228621.5U 2022-01-27 2022-01-27 Packaging structure Active CN217062077U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220228621.5U CN217062077U (en) 2022-01-27 2022-01-27 Packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220228621.5U CN217062077U (en) 2022-01-27 2022-01-27 Packaging structure

Publications (1)

Publication Number Publication Date
CN217062077U true CN217062077U (en) 2022-07-26

Family

ID=82485567

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202220228621.5U Active CN217062077U (en) 2022-01-27 2022-01-27 Packaging structure

Country Status (1)

Country Link
CN (1) CN217062077U (en)

Similar Documents

Publication Publication Date Title
US8174105B2 (en) Stacked semiconductor package having discrete components
US7326592B2 (en) Stacked die package
US7122906B2 (en) Die-wafer package and method of fabricating same
US10784178B2 (en) Wafer-level stack chip package and method of manufacturing the same
US9006882B2 (en) Semiconductor device and method of forming recessed conductive vias in saw streets
US9401338B2 (en) Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US6525413B1 (en) Die to die connection method and assemblies and packages including dice so connected
US6982491B1 (en) Sensor semiconductor package and method of manufacturing the same
US20130026609A1 (en) Package assembly including a semiconductor substrate with stress relief structure
US20150061130A1 (en) Chip arrangement and a method for manufacturing a chip arrangement
US8699232B2 (en) Integrated circuit packaging system with interposer and method of manufacture thereof
CN217062077U (en) Packaging structure
US20080237831A1 (en) Multi-chip semiconductor package structure
CN217062078U (en) Packaging structure
CN113629022A (en) Packaging structure and packaging method of six-axis integrated sensor
CN113629023A (en) Packaging structure and packaging method thereof
CN114823584A (en) Packaging structure and packaging method thereof
US10269718B2 (en) Rectangular semiconductor package and a method of manufacturing the same
CN216054656U (en) Six integrated sensor's packaging structure
CN216311756U (en) Packaging structure
CN114551388A (en) Packaging structure and packaging method thereof
CN116759410A (en) Electronic package and method for manufacturing the same
CN113998660A (en) Packaging structure and packaging method of six-axis sensor
CN112490129A (en) Semiconductor package and method of manufacturing the same
KR20110105160A (en) Semiconductor package

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant