CN114551388A - Packaging structure and packaging method thereof - Google Patents

Packaging structure and packaging method thereof Download PDF

Info

Publication number
CN114551388A
CN114551388A CN202210100418.4A CN202210100418A CN114551388A CN 114551388 A CN114551388 A CN 114551388A CN 202210100418 A CN202210100418 A CN 202210100418A CN 114551388 A CN114551388 A CN 114551388A
Authority
CN
China
Prior art keywords
sensor
semiconductor wafer
wafer
control unit
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210100418.4A
Other languages
Chinese (zh)
Inventor
刘尧青
郭亚
刘海东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Memsic Semiconductor Wuxi Co Ltd
Original Assignee
Memsic Semiconductor Wuxi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memsic Semiconductor Wuxi Co Ltd filed Critical Memsic Semiconductor Wuxi Co Ltd
Priority to CN202210100418.4A priority Critical patent/CN114551388A/en
Publication of CN114551388A publication Critical patent/CN114551388A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Abstract

The invention provides a packaging structure and a packaging method thereof, wherein the packaging structure comprises: a semiconductor wafer having a back surface positioned above a front surface thereof; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor; a first rewiring layer is arranged on the back surface of the semiconductor wafer, and is led out from a control unit of the sensor through the through hole and redistributed to the back surface of the semiconductor wafer; a plurality of sensor devices distributed on the first redistribution layer, each sensor device bonded to the back side of the semiconductor wafer, and a signal contact of each sensor device connected to the first redistribution layer; and the second rewiring layer is positioned below the metal bonding pad and is connected with the metal bonding pad. Compared with the prior art, the invention integrates a plurality of sensors and control units into one packaging body, thereby ensuring higher integration level of products.

Description

Packaging structure and packaging method thereof
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of integrated sensors, in particular to a wafer level system integrated packaging structure fusing multiple sensors and a control unit and a packaging method thereof.
[ background of the invention ]
With the continuous development of moore's law, the size of the chip is approaching to the limit of the mask, which presents a more serious challenge to the development of the semiconductor package in the directions of being light, thin, short and small. At present, most of the sensor packages adopt single-chip, single-function, frame type and substrate type packages, and have the advantages of large package size, low integration level and single function. The development of high integration, versatility, small size, and modularity of semiconductor devices requires new requirements and challenges for the packaging of sensors.
[ summary of the invention ]
One of the objectives of the present invention is to provide a package structure and a packaging method thereof, which integrate a plurality of sensors and a control unit into one package, thereby achieving higher integration of products and lower processing cost.
According to an aspect of the present invention, there is provided a package structure, including: a semiconductor wafer having a back surface opposite to the front surface thereof and a back surface above the front surface thereof; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor; a first rewiring layer is arranged on the back of the semiconductor wafer, and the first rewiring layer is led out from the control unit of the sensor through the through hole and redistributed to the back of the semiconductor wafer; a plurality of sensor devices distributed on the first redistribution layer, each of the sensor devices being bonded to the back side of the semiconductor wafer and a signal contact of each of the sensor devices being connected to the first redistribution layer; and the second rewiring layer is positioned below the metal bonding pad and is connected with the metal bonding pad.
According to another aspect of the present invention, there is provided a method of packaging a package structure, including: providing a semiconductor wafer, wherein the back surface of the semiconductor wafer is opposite to the front surface of the semiconductor wafer, and the back surface of the semiconductor wafer is positioned above the front surface of the semiconductor wafer; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor; arranging a first rewiring layer on the back surface of the semiconductor wafer, wherein the first rewiring layer is led out from a control unit of the sensor through the through hole and is redistributed to the back surface of the semiconductor wafer; providing a plurality of sensor devices; placing a plurality of the sensor devices on the first redistribution layer, bonding each sensor device to the back side of the semiconductor wafer, and connecting a signal contact of each sensor device to the first redistribution layer to form a wafer structure;
cutting the wafer structure to obtain a plurality of single chips, and distributing the single chips on a carrier plate, wherein in each single chip, the metal bonding pad is adjacent to the carrier plate, and the plurality of sensor devices deviate from the carrier plate; performing plastic packaging on a plurality of single chips distributed on the carrier plate by using a plastic packaging material through a plastic packaging process to form a plastic packaged product; and forming a second rewiring layer on the surface of one side of the plastic package product, from which the carrier plate is stripped, wherein the second rewiring layer is positioned below the metal bonding pad in the single chip and is connected with the metal bonding pad.
Compared with the prior art, the invention integrates multiple sensors (not limited to 2) and a control unit into one packaging body through system integration packaging, thereby realizing the diversification, integration and modularization of the functions of a single packaged sensor; the occupied area in the terminal application is effectively reduced, the production period and the processing cost of the terminal are shortened, and the application prospect is wider.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:
FIG. 1 is a schematic longitudinal cross-sectional view of a package structure according to an embodiment of the invention;
FIG. 2 is a flow chart illustrating a method for packaging a package structure according to an embodiment of the invention;
fig. 3-13 are schematic longitudinal cross-sectional views corresponding to the steps shown in fig. 2 in one embodiment of the present invention.
[ detailed description ] embodiments
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless otherwise specified, the terms connected, and connected as used herein mean electrically connected, directly or indirectly.
Fig. 1 is a schematic longitudinal cross-sectional view of a package structure according to an embodiment of the invention, which integrates a plurality of sensor devices and a sensor control unit into a package. The package structure shown in fig. 1 comprises a semiconductor wafer 1, a plurality of sensor devices 2, 3 and a molding compound 5. After the semiconductor wafer level package (or system integration package) is passed, a semiconductor wafer dicing step is performed to form a plurality of mutually independent package structures, i.e., independent chips. The semiconductor wafer 1 is a separate semiconductor wafer in a view before the semiconductor wafer is cut, i.e. in a view at the semiconductor wafer level (i.e. wafer level), and the semiconductor wafer 1 can be understood as a wafer of the semiconductor wafer in a view after the semiconductor wafer is cut, i.e. in a view at the chip level.
For ease of description, only two sensor devices 2, 3 are shown in the embodiment shown in fig. 1, and in practice, there may be more sensor devices in the present invention.
The back surface of the semiconductor wafer 1 is opposite to the front surface thereof, and the back surface of the semiconductor wafer 1 is positioned above the front surface thereof. The front side (i.e. the circuit side) of the semiconductor wafer 1 is provided with a control unit (which includes a control circuit and a memory circuit of the sensor) 102 of the sensor and a metal pad 103; a through hole 101 is formed in the semiconductor wafer 1, and the through hole 101 extends downwards from the back surface of the semiconductor wafer 1 to a control unit 102 of the sensor; the back surface (i.e. non-circuit surface) of the semiconductor wafer 1 is provided with a first rewiring layer 105, and the first rewiring layer 105 is led out from the control unit 102 of the sensor through the through hole 101 and is redistributed to the back surface of the semiconductor wafer 1, so that the signal of the through hole 101 is redistributed on the back surface of the semiconductor wafer 1.
In the specific embodiment shown in fig. 1, the metal pads 103 are located below the control unit 102 of the sensor (or the metal pads 103 are closer to the front surface of the semiconductor wafer 1 than the control unit 102 of the sensor); the first rewiring layer 105 is protected by a passivation layer 104; the via 101 is a through silicon via formed based on a deep silicon via technique.
The sensor devices 2, 3 are distributed on the first redistribution layer 105, each sensor device 2, 3 is bonded to the back surface of the semiconductor wafer 1, and a signal contact of each sensor device 2, 3 is connected to the first redistribution layer 105. In one embodiment, the sensor devices 2, 3 are bonded to the semiconductor wafer 1 by a flip-chip, reflow process.
In the specific embodiment shown in fig. 1, the sensor device 2 is a WLP (Wafer Level Packaging) based sensor device, and includes a substrate 201, a sensor structure layer 202, a sensor structure protective cover 203, a redistribution layer 204, and a metal bump 205, which are sequentially stacked; the sensor device 3 is a WLP-based sensor device, and includes a substrate 301, a sensor structure layer 302, a sensor structure protective cover 303, a redistribution layer 304, and a metal bump 305, which are sequentially stacked. Wherein the metal bumps 205, 305 are signal contacts of the sensor devices 2, 3 connected to the first redistribution layer 105; sensor structure layer 202 and sensor structure layer 302 each include a fixed structure at the edge of the chip and a movable structure in the middle of the chip.
In particular, the plurality of sensor devices 2 and 3 in the present invention may be the same type of sensor device or different types of sensor devices. The sensor devices 2 and 3 may be sensor devices in the prior art, and thus the specific structures of the sensor devices 2 and 3 are not described herein again.
In the embodiment shown in fig. 1, a second redistribution layer 501 is disposed on the front surface of the bonded semiconductor wafer 1, the second redistribution layer 501 is located below the metal pad 103, the second redistribution layer 501 is connected to the metal pad 103, so that signal output ends are redistributed through a redistribution process, and the second redistribution layer 501 is protected by a dielectric layer 502.
Solder balls 503 are provided on the second redistribution layer 501 on the front surface of the semiconductor wafer 1. In one embodiment, the metal layer may be formed by a ball-planting or electroplating process. The integrated semiconductor wafer 1 and the plurality of sensor devices 2, 3 are subjected to plastic packaging by a plastic packaging process using a plastic packaging material 5 to form a final package.
Fig. 2 is a schematic flow chart illustrating a packaging method of a package structure according to an embodiment of the invention; please refer to fig. 3-13, which are schematic longitudinal cross-sectional views corresponding to the steps shown in fig. 2 according to an embodiment of the present invention. The packaging method of the package structure shown in fig. 2 includes the following steps.
Step 210, as shown in fig. 3, providing an initial wafer 11, wherein the back surface of the initial wafer 11 is opposite to the front surface thereof, and the back surface of the initial wafer 11 is located above the front surface thereof; the front side (i.e. circuit side) of the initial wafer 11 is provided with a control unit of a sensor (which includes a control circuit and a memory circuit of the sensor) 102 and a metal pad 103; the initial wafer 11 is provided with a through hole 101 therein, the through hole 101 is located above the control unit 102 of the sensor, one end of the through hole 101 is at a predetermined distance from the back surface of the initial wafer 11, and the other end thereof extends to the control unit 102 of the sensor. In the specific embodiment shown in fig. 1, the metal pads 103 are located below the control unit 102 of the sensor (or the metal pads 103 are closer to the front side of the initial wafer 11 than the control unit 102 of the sensor); the via 101 is a through silicon via formed based on a deep silicon via technique.
In step 220, as shown in fig. 4, thinning the back surface of the initial wafer 11 by a thinning process to expose the through holes 101 on the thinned back surface (i.e., non-circuit surface) of the initial wafer 11, thereby obtaining the semiconductor wafer 1. That is, the back surface of the semiconductor wafer 1 is opposite to the front surface thereof, and the back surface thereof is located above the front surface thereof; the front surface of the semiconductor wafer 1 is provided with a control unit 102 and a metal pad 103 of a sensor; the semiconductor wafer 1 is internally provided with a through hole 101, and the through hole 101 extends downwards from the back surface of the semiconductor wafer 1 to a control unit 102 of the sensor.
Step 230, as shown in fig. 5, a first redistribution layer 105 is disposed on the back side of the semiconductor wafer 1 (i.e. the back side of the thinned initial wafer 11) through a redistribution process, and the first redistribution layer 105 is led out from the control unit 102 of the sensor through the through hole 101 and redistributed to the back side of the semiconductor wafer 1, so that the signal of the through hole 101 is redistributed on the back side of the semiconductor wafer 1. In the embodiment shown in fig. 5, the first redistribution layer 105 is protected by a passivation layer 104.
Step 240, as shown in fig. 6, provides sensor device 2 and sensor device 3. In the specific embodiment shown in fig. 6, the sensor device 2 is a WLP (Wafer Level Packaging) based sensor device, and includes a substrate 201, a sensor structure layer 202, a sensor structure protection cover 203, a redistribution layer 204, and a metal bump 205, which are sequentially stacked; the sensor device 3 is a WLP-based sensor device, and includes a substrate 301, a sensor structure layer 302, a sensor structure protective cover 303, a redistribution layer 304, and a metal bump 305, which are sequentially stacked. Wherein the sensor structure layer 202 and the sensor structure layer 302 each include a fixed structure located at the edge of the chip and a movable structure located in the middle of the chip.
Step 250, as shown in fig. 7, the sensor devices 2 and 3 are placed on the first redistribution layer 105, each sensor device 2 and 3 is bonded to the back surface of the semiconductor wafer 1, and the signal contact of each sensor device 2 and 3 is connected to the first redistribution layer 105 to form a wafer structure. In the embodiment shown in fig. 7, the sensor devices 2 and 3 are bonded to the semiconductor wafer 1 by a flip-chip, reflow process. In the embodiment shown in fig. 7, the metal bumps 205, 305 are signal contacts of the sensor devices 2, 3 connected to the first redistribution layer 105.
Step 260, as shown in fig. 8, the wafer structure is cut to obtain a plurality of single chips, and the single chips are distributed on the carrier 4 by a redistribution process. Wherein in each single chip the metal pads 103 are adjacent to said carrier plate 4 and the sensor devices 2, 3 are facing away from said carrier plate 4.
Step 270, as shown in fig. 9, performing plastic package on the plurality of single chips distributed on the carrier plate 4 by using a plastic package material 5 through a plastic package process to form a plastic package product.
Step 280, as shown in fig. 10, peeling off the carrier plate 4 on the plastic package product under a certain process condition.
Step 290, as shown in fig. 11, a second redistribution layer 501 is formed on the surface of the side of the plastic package product from which the carrier plate 4 is peeled, the second redistribution layer 501 is located below the metal pad 103 in each single chip, and the second redistribution layer 501 is connected to the metal pad 103, so that the signal output ends are redistributed through a redistribution process. In the embodiment shown in fig. 11, the second redistribution layer 501 is protected by a dielectric layer 502.
Step 300, as shown in fig. 12, solder balls 503 are formed on the second redistribution layer 501 of the plastic package product. In one embodiment, the metal layer may be formed by a ball-planting or electroplating process.
Step 310, as shown in fig. 13, the packaged product formed with the solder balls 503 is separated by a cutting process, so as to form a single packaged chip.
For ease of description, only two sensor devices 2, 3 are shown in the embodiment shown in fig. 3-13, and in practice, there may be more sensor devices in the present invention. In particular, the plurality of sensor devices 2 and 3 in the present invention may be the same type of sensor device or different types of sensor devices. The sensor devices 2 and 3 may be sensor devices in the prior art, and thus the specific structures of the sensor devices 2 and 3 are not described herein again.
In summary, the present invention integrates multiple sensors (not limited to 2 sensors) 2 and 3 and the sensor control unit 102 into one package through system integration and packaging, so as to realize diversification, integration and modularization of functions of a single packaged sensor; the occupied area in the terminal application is effectively reduced, the production period and the processing cost of the terminal are shortened, and the application prospect is wider.
In the present invention, the terms "connected", "connecting", and the like mean electrical connections, and direct or indirect electrical connections unless otherwise specified.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.

Claims (10)

1. A package structure, comprising:
a semiconductor wafer having a back surface opposite to the front surface thereof and a back surface above the front surface thereof; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor; a first rewiring layer is arranged on the back of the semiconductor wafer, and the first rewiring layer is led out from the control unit of the sensor through the through hole and redistributed to the back of the semiconductor wafer;
a plurality of sensor devices distributed on the first redistribution layer, each of the sensor devices being bonded to the back side of the semiconductor wafer and a signal contact of each of the sensor devices being connected to the first redistribution layer;
and the second rewiring layer is positioned below the metal bonding pad and is connected with the metal bonding pad.
2. The package structure of claim 1,
the control unit of the sensor comprises a control circuit and a storage circuit of the sensor;
the sensor device is a wafer level package based sensor device;
the plurality of sensor devices are the same kind of sensor device or different kinds of sensor devices.
3. The package structure of claim 2,
the through hole is a silicon through hole formed based on a deep silicon via technology;
the sensor device is bonded with the semiconductor wafer through a flip chip and reflow process.
4. The package structure of claim 1,
the sensor device comprises a substrate, a sensor structure layer, a sensor structure protective cover, a rewiring layer and metal bumps which are sequentially stacked;
the metal bumps are signal contacts connected with the first rewiring layer in the sensor device.
5. The package structure of claim 1, further comprising:
the solder balls are arranged on the second rewiring layer on the front surface of the semiconductor wafer;
and the plastic packaging material is used for plastically packaging the integrated semiconductor wafer and the plurality of sensor devices.
6. A packaging method of a packaging structure is characterized by comprising the following steps:
providing a semiconductor wafer, wherein the back surface of the semiconductor wafer is opposite to the front surface of the semiconductor wafer, and the back surface of the semiconductor wafer is positioned above the front surface of the semiconductor wafer; the front surface of the semiconductor wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the semiconductor wafer and extends downwards from the back surface of the semiconductor wafer to the control unit of the sensor;
arranging a first rewiring layer on the back surface of the semiconductor wafer, wherein the first rewiring layer is led out from a control unit of the sensor through the through hole and is redistributed to the back surface of the semiconductor wafer;
providing a plurality of sensor devices;
placing a plurality of the sensor devices on the first redistribution layer, bonding each sensor device to the back side of the semiconductor wafer, and connecting a signal contact of each sensor device to the first redistribution layer to form a wafer structure;
cutting the wafer structure to obtain a plurality of single chips, and distributing the single chips on a carrier plate, wherein in each single chip, the metal bonding pad is adjacent to the carrier plate, and the plurality of sensor devices deviate from the carrier plate;
performing plastic packaging on a plurality of single chips distributed on the carrier plate by using a plastic packaging material through a plastic packaging process to form a plastic packaged product;
and forming a second rewiring layer on the surface of one side of the plastic package product, from which the carrier plate is stripped, wherein the second rewiring layer is positioned below the metal bonding pad in the single chip and is connected with the metal bonding pad.
7. The method of claim 6, further comprising:
forming a solder ball on the second redistribution layer of the plastic package product;
and separating the packaged product with the solder balls through a cutting process to form a single packaged chip.
8. The packaging method of the packaging structure according to claim 6 or 7,
the step of providing a semiconductor wafer comprises:
providing an initial wafer 11, wherein the back surface of the initial wafer is opposite to the front surface of the initial wafer, and the back surface of the initial wafer is positioned above the front surface of the initial wafer; the front side of the initial wafer is provided with a control unit of a sensor and a metal bonding pad; a through hole is formed in the initial wafer and is positioned above the control unit of the sensor, one end of the through hole is a preset distance away from the back of the initial wafer, and the other end of the through hole extends to the control unit of the sensor;
and thinning the back surface of the initial wafer to expose the through hole on the thinned back surface of the initial wafer so as to obtain the semiconductor wafer.
9. The method of claim 6,
the control unit of the sensor comprises a control circuit and a storage circuit of the sensor;
the sensor device is a wafer level package based sensor device;
the plurality of sensor devices are the same kind of sensor devices or different kinds of sensor devices;
the through hole is a silicon through hole formed based on a deep silicon via technology;
the sensor device is bonded with the semiconductor wafer through a flip chip and reflow process.
10. The method of claim 6,
the sensor device comprises a substrate, a sensor structure layer, a sensor structure protective cover, a rewiring layer and metal bumps which are sequentially stacked;
the metal bumps are signal contacts connected with the first rewiring layer in the sensor device.
CN202210100418.4A 2022-01-27 2022-01-27 Packaging structure and packaging method thereof Pending CN114551388A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210100418.4A CN114551388A (en) 2022-01-27 2022-01-27 Packaging structure and packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210100418.4A CN114551388A (en) 2022-01-27 2022-01-27 Packaging structure and packaging method thereof

Publications (1)

Publication Number Publication Date
CN114551388A true CN114551388A (en) 2022-05-27

Family

ID=81673422

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210100418.4A Pending CN114551388A (en) 2022-01-27 2022-01-27 Packaging structure and packaging method thereof

Country Status (1)

Country Link
CN (1) CN114551388A (en)

Similar Documents

Publication Publication Date Title
CN109585404B (en) Semiconductor package and method of forming the same
US7326592B2 (en) Stacked die package
US9293449B2 (en) Methods and apparatus for package on package devices with reversed stud bump through via interconnections
CN110034106B (en) Package structure and method for manufacturing the same
US7105930B2 (en) Semiconductor substrates including I/O redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same
US8354742B2 (en) Method and apparatus for a package having multiple stacked die
US8492201B2 (en) Semiconductor device and method of forming through vias with reflowed conductive material
US7345361B2 (en) Stackable integrated circuit packaging
US20040032013A1 (en) Semiconductor dice packages employing at least one redistribution layer and methods of fabrication
US11088100B2 (en) Semiconductor package and manufacturing method thereof
EP3547364B1 (en) Semiconductor chip and semiconductor package including the same
US20230361091A1 (en) Electronic package and manufacturing method thereof
US20130069223A1 (en) Flash memory card without a substrate and its fabrication method
US20230055425A1 (en) Semiconductor assemblies with system and methods for conveying signals using through mold vias
CN217062078U (en) Packaging structure
CN114551388A (en) Packaging structure and packaging method thereof
CN217062077U (en) Packaging structure
CN114823584A (en) Packaging structure and packaging method thereof
US11469219B1 (en) Dual die semiconductor package and manufacturing method thereof
CN220585231U (en) Packaging structure
US11538761B2 (en) Semiconductor package having molded die and semiconductor die and manufacturing method thereof
CN111354686B (en) Electronic package, method for fabricating the same, substrate for packaging, and method for fabricating the same
KR101931450B1 (en) Semiconductor packages and methods of forming the same
CN116613111A (en) Electronic package and method for manufacturing the same
CN114725028A (en) System-in-package chip of printer driving system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination