CN217060967U

CN217060967U - Interface acceleration board card

Info

Publication number: CN217060967U
Application number: CN202220530789.1U
Authority: CN
Inventors: 杨志炜
Original assignee: Shenzhen Intellifusion Technologies Co Ltd
Current assignee: Shenzhen Intellifusion Technologies Co Ltd
Priority date: 2022-03-10
Filing date: 2022-03-10
Publication date: 2022-07-26
Anticipated expiration: 2032-03-10

Abstract

The utility model provides an interface integrated circuit board with higher speed, include: the device comprises a main control module, a first storage module, a second storage module, an interface selection module, an interface conversion module, a first interface bus, a second interface bus, a third interface bus, a fourth interface bus and an external interface; the first storage module and the second storage module are electrically connected with the main control module; the main control module is connected with the interface selection module through the first interface bus; the interface selection module is connected with the interface conversion module through the second interface bus; the interface conversion module is connected with the external interface through the third interface bus; the external interface is connected with the interface selection module through the fourth interface bus; the main control module is a DP1000 chip. The utility model discloses can improve the cost/performance ratio of interface acceleration integrated circuit board and realize multiple interface function.

Description

Interface acceleration board card

Technical Field

The utility model belongs to the technical field of the interface integrated circuit board, especially, relate to an interface acceleration integrated circuit board.

Background

The PCIE card for accelerating the hard disk is an expansion card for accelerating the data read-write speed of the computer hard disk. When the hard disk acceleration PCIE card is used, the hard disk acceleration PCIE card is plugged into a PCIE interface of a computer mainboard. The most common expansion card is the Mini PCIeAI accelerator card. The Mini pci ieee AI accelerator card in the current market is generally an AI accelerator chip of a large foreign factory, and has the disadvantages of high price, high hardware cost and single interface function.

SUMMERY OF THE UTILITY MODEL

The utility model provides an interface acceleration integrated circuit board aims at reducing the hardware cost and realizes the effect of multiple interface function.

The utility model discloses a realize like this, provide an interface integrated circuit board with higher speed, include: the device comprises a main control module, a first storage module, a second storage module, an interface selection module, an interface conversion module, a first interface bus, a second interface bus, a third interface bus, a fourth interface bus and an external interface;

the first storage module and the second storage module are electrically connected with the main control module;

the main control module is connected with the interface selection module through the first interface bus;

the interface selection module is connected with the interface conversion module through the second interface bus;

the interface conversion module is connected with the external interface through the third interface bus;

the external interface is connected with the interface selection module through the fourth interface bus;

the main control module is a DP1000 chip.

Further, the first storage module includes: the first memory cell and the second memory cell are respectively and electrically connected with the DP1000 chip.

Furthermore, the first memory cell and the second memory cell are DDR4 grains.

Furthermore, the data transmission protocols in the first interface bus and the second interface bus are both USB3.0 transmission protocols.

Further, the data transmission protocol in the third interface bus is PCIe Gen2 x1 interface protocol.

Furthermore, the external interface is provided with a general input/output interface.

Furthermore, the data transmission protocol in the fourth interface bus is a USB2.0 transmission protocol.

Further, the interface acceleration board further includes: and the dial switch is electrically connected with the interface selection module.

Furthermore, the interface selection module is an SGM7222 chip.

Furthermore, the interface conversion module is an ASM1042A chip.

The utility model discloses the beneficial effect who reaches: the DP1000 chip with high cost ratio is used, so that the interface calculation force acceleration card function of the interface acceleration card is realized, and the switching of the second interface bus and the third interface bus is realized by arranging an interface selection module so as to adapt to different interface devices. And the data conversion between the second interface bus and the third interface bus is realized through the interface conversion module so as to realize various interface functions. And then improve the cost performance of the interface acceleration integrated circuit board and realize multiple interface functions.

Drawings

Fig. 1 is a schematic block diagram of an interface acceleration board provided by the present invention;

fig. 2 is a circuit diagram of another interface acceleration board provided by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 1, fig. 1 is a schematic block diagram of an interface acceleration board card according to the present invention.

This interface accelerates integrated circuit board includes: the device comprises a main control module 1, a first storage module 2, a second storage module 3, an interface selection module 4, an interface conversion module 5, a first interface bus 6, a second interface bus 12, a third interface bus 7, a fourth interface bus 8 and an external interface. The first storage module 2 and the second storage module 3 are both electrically connected with the main control module 1, and provide sufficient operating space and storage space for the main control module 1. The main control module 1 is connected with the interface selection module 4 through the first interface bus 6. The interface selection module 4 is connected with the interface conversion module 5 through the second interface bus 12. The interface conversion module 5 is electrically connected with an external interface 11 through the third interface bus 7. The external interface 11 is connected with the interface selection module 4 through the fourth interface bus 8. Master module 1 is the DP1000 chip, and the DP1000 chip is 1 high performance low-power consumption AI acceleration chip of single-chip, can realize single-chip full rate work, and then can improve the operating efficiency of interface acceleration integrated circuit board.

The first interface bus 6 and the second interface bus 12 may be the same type of interface bus, and the corresponding data transmission protocols may also be the same, for example, the corresponding data transmission protocols may both be USB3.0 transmission protocols. The data transmission protocol corresponding to the third interface bus 7 may be a PCIe Gen2 x1 interface protocol, the external interface 11 may be a Mini PCIe interface, and the data transmission protocol of the Mini PCIe interface may be a USB2.0 transmission protocol and a PCIe Gen2 x1 interface protocol to adapt to different external devices. When the data transmission protocol of the Mini PCIe interface is the USB2.0 transmission protocol, the Mini PCIe interface can realize the function of the USB2.0 interface. When the data transmission protocol of the Mini PCIe interface is PCIe Gen2 x1 interface protocol, the Mini PCIe interface can realize the PCIe interface function.

The embodiment of the utility model provides an in, through the DP1000 chip that usability price ratio is high, realize that the interface of interface acceleration integrated circuit board calculates power acceleration card function to select module 4 to realize the switching of second interface bus 12 and third interface bus 7 through setting up the interface, with the different interface device of adaptation. The data conversion of the second interface bus 12 and the third interface bus 7 is also realized through the interface conversion module to realize various interface functions. And then improve the cost performance of the interface acceleration integrated circuit board and realize multiple interface functions.

In this embodiment, the interface selection module 4 is configured to switch the second interface bus 12 and the fourth interface bus 8, and when the interface selection module is switched to the second interface bus 12, the interface conversion module 5 switches the second interface bus 12 to the third interface bus 7 to transmit PCIe signal data, so as to implement a PCIe interface function. When the interface is switched to the fourth interface bus 8, the USB2.0 signal data is transmitted through the fourth interface bus 8, so as to implement the USB2.0 interface function, thereby ensuring that the external interface 11 can implement the PCIe interface function and also implement the USB2.0 interface function. Specifically, when the PCIe interface function needs to be used, the PCIe Gen2 x1 interface protocol may be converted into the USB3.0 transport protocol through the interface conversion module 5, and communicate with the DP1000 chip through the interface selection module 4. Or, when the USB2.0 interface function needs to be used, the USB2.0 interface bus is selected by the interface selection module 4 and then connected to the DP1000 chip. The interface conversion module 5 is configured to implement switching between the second interface bus 12 and the fourth interface bus 8 to implement signal data conversion between PCIe and USB3.0, and specifically may be configured to implement conversion between a PCIe Gen2 x1 interface protocol and a USB3.0 transport protocol interface to complete data transmission between the PCIe interface and the USB3.0 interface. The interface selection module 4 may specifically be an SGM7222 chip, and the interface conversion module 5 may specifically be an ASM1042A chip.

In the embodiment of the present invention, as shown in fig. 1, the first storage module 2 includes: the memory device includes a first memory cell 9 and a second memory cell 10, and the first memory cell 9 and the second memory cell 10 are electrically connected to a DP1000 chip. The first memory cell 9 and the second memory cell 10 are DDR4 grains, and each DDR4 grain has a size of 1GB, so that the total capacity of the first memory module 2 is 2 GB. The second storage module 3 is a 4GB eMMC (solid state disk). The first storage module 2 provides sufficient operating space for the interface acceleration board, and the second storage module 3 provides sufficient storage space for the interface acceleration board. The first storage module 2 and the second storage module 3 can guarantee the reasoning acceleration computing power of the interface acceleration board card, and the performance of the interface acceleration board card is further improved.

In the present embodiment, as shown in fig. 2, the external interface 11(Mini PCIe interface) is provided with a general purpose input/output interface (not shown in the figure). The CPU on the mainboard can control the reset and BOOT start modes of the DP1000 chip through a general purpose input output interface (GPIO). The reset of the DP1000 chip corresponds to a rest interface of the DP1000 chip, the BOOT mode of the DP1000 chip corresponds to a BOOT _ set interface of the DP1000 chip, and both the rest interface and the BOOT _ set interface may be connected to the external interface 11. When the DP1000 chip operates abnormally, the CPU on the motherboard may perform a hardware reset operation on a rest interface of the DP1000 chip through a general purpose input output interface (GPIO). When the program of the DP1000 chip is damaged and cannot be recovered through resetting, the CPU on the mainboard can perform BOOT mode control on a BOOT _ set interface of the DP1000 chip through a general purpose input/output interface (GPIO), so that the DP1000 chip enters a USB burning start mode to perform program re-burning.

The CPU on the motherboard can transmit the video or image data to be processed to the DP1000 chip through the PCIe Gen2 x1 interface protocol or the USB2.0 transmission protocol in the external interface 11(Mini PCIe interface) via the third interface bus 7 or the fourth interface bus 8, and the DP1000 chip can also reversely transmit the processing result data.

In this embodiment, as shown in fig. 2, the interface acceleration board further includes: the dial switch 13 and the dial switch 13 are electrically connected with the interface selection module 4. The user can trigger the interface selection module 4 through the dial switch 13 to select whether to use the PCIe interface function or the USB interface function, can be compatible with Mini PCIe interfaces of different protocols, and then adapt to different application scenes, and then improve the performance of the interface acceleration board card and realize various interface functions.

The embodiment of the utility model provides an in, through the DP1000 chip that usability price ratio is high, realize that the interface of interface acceleration integrated circuit board calculates power acceleration card function to select module 4 to realize the switching of second interface bus 12 and third interface bus 7 through setting up the interface, with the different interface device of adaptation. The data conversion of the second interface bus 12 and the third interface bus 7 is also realized through the interface conversion module 5, so as to realize various interface functions. And then improve the cost performance of the interface acceleration integrated circuit board and realize multiple interface functions. The mainboard can also flexibly control the interface acceleration board card to perform abnormal resetting, burning, upgrading and the like. The interface acceleration board card has high cost performance, is autonomously controllable in home-made, and has high application value in the field of industrial control.

The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. An interface acceleration board, comprising: the device comprises a main control module, a first storage module, a second storage module, an interface selection module, an interface conversion module, a first interface bus, a second interface bus, a third interface bus, a fourth interface bus and an external interface;

the main control module is a DP1000 chip.

2. The interface acceleration board of claim 1, wherein the first storage module comprises: the first memory cell and the second memory cell are respectively and electrically connected with the DP1000 chip.

3. The interface acceleration board of claim 2, wherein the first storage unit and the second storage unit are both DDR4 granules.

4. The interface acceleration board of claim 1, wherein the data transmission protocol in the first interface bus and the second interface bus are both USB3.0 transmission protocols.

5. The interface acceleration board of claim 1, wherein the data transfer protocol in the third interface bus is the PCIe Gen2 x1 interface protocol.

6. The interface acceleration board card of claim 1, wherein the external interface is provided with a general purpose input output interface.

7. The interface acceleration board of claim 1, wherein the data transmission protocol in the fourth interface bus is a USB2.0 transmission protocol.

8. The interface acceleration board of claim 1, wherein the interface acceleration board further comprises: and the dial switch is electrically connected with the interface selection module.

9. The interface acceleration board according to any one of claims 1 to 8, wherein the interface selection module is an SGM7222 chip.

10. The interface acceleration board of claim 1, wherein the interface conversion module is an ASM1042A chip.