CN217009176U - Packaging structure - Google Patents
Packaging structure Download PDFInfo
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- CN217009176U CN217009176U CN202220515607.3U CN202220515607U CN217009176U CN 217009176 U CN217009176 U CN 217009176U CN 202220515607 U CN202220515607 U CN 202220515607U CN 217009176 U CN217009176 U CN 217009176U
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Abstract
The utility model discloses a packaging structure, comprising: the chip unit comprises a first surface and a second surface which are opposite, the first surface is provided with an induction area and a welding pad, the welding pad is electrically coupled with the induction area, the second surface of the chip unit is provided with a through hole which penetrates through the chip unit, the through hole is used for exposing the welding pad, and the thickness of the chip unit is less than 60 mu m; a protective cover plate opposite to the first surface of the chip unit; the substrate is opposite to the second surface of the chip unit, and a through hole communicated with the through hole is formed in the substrate; the insulating layer at least covers the inner wall of the via hole; and the welding bulge is arranged on the surface of the substrate departing from the chip unit and is electrically connected with the welding pad through a rewiring layer arranged in the through hole and the through hole. The via hole obtained by the packaging structure is good in uniformity, and the coverage rate of the insulating layer on the inner wall of the via hole is high.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and more particularly, to a package structure.
Background
Wafer Level Chip Packaging (WLCSP) is a technology in which a whole Wafer is subjected to a Packaging test and then cut to obtain individual finished chips. The chip packaged by the wafer level chip packaging technology achieves high miniaturization, and the chip cost is obviously reduced along with the reduction of the chip and the increase of the wafer size. The technology conforms to the market requirements for increasingly light, small, short, thin and low-price microelectronic products, thereby becoming a hot spot and development trend in the current packaging field.
TSV (through silicon via technology) is the latest technology for realizing interconnection between chips by making vertical vias between chips and between wafers. Different from the traditional IC packaging bonding and bump stacking technology, the TSV can enable the stacking density of the chips in the three-dimensional direction to be the largest, the overall dimension to be the smallest, and the chip speed and the low power consumption performance to be greatly improved.
When a chip is packaged in the existing wafer level packaging method, the thickness of the chip is 150-180 μm, a through hole exposing a welding pad is formed by etching the chip, and then an insulating layer is deposited in the through hole, but because the thickness of the chip is large, the depth-to-width ratio of the through hole formed by TSV exceeds 3: 1, after etching, the uniformity of holes formed on the wafer is poor, the warping of the whole wafer is serious, the final packaging yield is very low, and the coverage rate of insulating layers on the inner surfaces and the bottoms of the holes is low.
The information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a packaging structure which can solve the problems of poor uniformity of etching holes and low coverage rate of an insulating layer formed in the holes in the prior art.
To achieve the above object, an embodiment of the present invention provides a package structure, including:
the chip unit comprises a first surface and a second surface which are opposite, the first surface is provided with an induction area and a welding pad, the welding pad is electrically coupled with the induction area, the second surface of the chip unit is provided with a through hole which penetrates through the chip unit, the through hole is used for exposing the welding pad, and the thickness of the chip unit is smaller than 60 mu m;
a protective cover plate opposite to the first surface of the chip unit;
the substrate is opposite to the second surface of the chip unit, and a through hole communicated with the through hole is formed in the substrate;
the insulating layer at least covers the inner wall of the via hole;
and the welding bulge is arranged on the surface of the substrate deviating from the chip unit and is electrically connected with the welding pad through a rewiring layer arranged in the through hole and the through hole.
In one or more embodiments of the present invention, the via hole is a through hole, and/or the through hole is a through hole.
In one or more embodiments of the present invention, the depth of the via is less than the width of the via. In one or more embodiments of the present invention, the width of the via hole is 40 to 60 μm.
In one or more embodiments of the utility model, the substrate is bonded to the second surface of the chip unit.
In one or more embodiments of the utility model, the insulating layer extends between the chip unit and the substrate.
In one or more embodiments of the utility model, the substrate is bonded to the second surface of the chip unit.
In one or more embodiments of the present invention, the material of the substrate is selected from glass.
In one or more embodiments of the present invention, the substrate has a thickness of 100 to 120 μm.
In one or more embodiments of the present invention, the chip unit further includes a supporting structure, the supporting structure is located between the first surface of the chip unit and the protective cover plate, and the sensing region is located in a groove enclosed by the supporting structure and the protective cover plate.
Compared with the prior art, the packaging method provided by the utility model has the advantages that the chip is thinned, the thickness of the chip is reduced, and then the through hole is formed by etching, so that the uniformity of the obtained through hole is good, and the coverage rate of the insulating layer on the inner wall of the through hole is high.
Drawings
Fig. 1 is a schematic diagram of a package structure according to embodiment 1 of the present invention;
fig. 2a to 2h are schematic intermediate structures of a manufacturing process of a package structure according to embodiment 2 of the present invention;
fig. 3 is a top view of a structure of a wafer according to embodiment 3 of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
Example 1
As shown in fig. 1, a package structure 100 according to a preferred embodiment of the present invention includes a chip unit 10, a protective cover 20, a substrate 30, an insulating layer 40, and a solder bump 50. The chip unit 10 comprises a first surface 11 and a second surface 12 which are opposite, the first surface is provided with an induction area 111 and a welding pad 112, the welding pad 112 is electrically coupled with the induction area 111, the second surface 12 of the chip unit 10 is provided with a through hole 13 which penetrates through the chip unit 10, and the through hole 13 is used for exposing the welding pad 112; the protective cover 20 is opposite to the first surface 11 of the chip unit 10; the substrate 30 is opposite to the second surface 12 of the chip unit 10, and a through hole 31 communicated with the through hole 13 is formed in the substrate 30; the insulating layer 40 at least covers the inner wall of the via hole 13; the bonding bumps 50 are disposed on the surface of the substrate 30 away from the chip unit 10, and the bonding bumps 50 are electrically connected to the bonding pads 112 through the redistribution layer 60 disposed in the vias 13 and the through holes 31.
In an embodiment, the sensing region 111 of the chip unit 10 is provided with a plurality of pixel points arranged in an array, and the chip unit 10 may be a capacitive sensing chip, such as a fingerprint identification chip.
In another embodiment, the chip unit 10 may also be a photosensitive chip, and in this case, in order to facilitate the sensing information of the sensing region 111, the protective cover 20 is made of a transparent material, such as glass, which may be organic glass or inorganic glass. In this case, the chip unit 10 may be an image sensing chip.
If the chip unit 10 is too thick, for example, the thickness is greater than 60 μm, the uniformity of the via holes etched through the TSVs is poor, which causes severe warpage of the whole chip unit and a low final packaging yield. In order to solve this problem, the thickness of the chip unit 10 in the present embodiment can be controlled to be 60 μm or less by thinning, and the thickness can be, for example, 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, or 55 μm. It is theoretically better that the thickness of the chip unit 10 is smaller and the bonding pad 112 is directly exposed. In the case where the thickness of the chip unit 10 is relatively small, the uniformity of the through-holes formed by the TSV etching is good.
In order to further improve the coverage of the insulating layer 40 in the via hole 13, the aspect ratio b/a of the via hole 13 in the present embodiment is less than 1, and in a preferred embodiment, the width (inner diameter) of the via hole 13 is 40 μm to 60 μm, more preferably 40 μm to 55 μm, and may be 45 μm, 47 μm, or 50 μm, for example.
The via 13 is used to expose the pad 112, so that the solder bump 50 is electrically connected to the pad 112. In one embodiment, the vias 13 are through holes, on one hand, the axes of which are perpendicular to the surface on which the chip units are located, and on the other hand, the vias 13 have the same aperture in their axial direction. In other embodiments, the through hole 13 may also be an oblique through hole, and the axial direction of the oblique through hole forms an oblique included angle with the plane of the chip unit. The shape of the through hole 13 may be a trumpet shape with a wide top and a narrow bottom, and the inner diameter of the trumpet shape gradually decreases from top to bottom. The shape of the via hole 13 may be a triangular hole, a square hole, etc., and this embodiment is merely an example.
The mechanical strength of the chip unit 10 after thinning is weak, in order to further enhance the mechanical strength of the package structure, in this embodiment, a substrate 30 with certain hardness and thickness is disposed on the second surface 12 of the chip unit 10, and in one embodiment, the substrate 30 may be made of an insulating material, preferably glass, and the glass may be organic glass or inorganic glass. The substrate 30 is provided to ensure the strength of the package and to control the thickness of the package, so the thickness of the substrate 30 is 100 μm to 120 μm, preferably 100 μm to 110 μm, such as 103 μm, 105 μm, 108 μm.
The substrate 30 and the chip unit 10 are bonded, and in one embodiment, silicon bonding may be used.
The through hole 31 on the substrate 30 is communicated with the via hole 13 for the redistribution layer 60 to pass through, and the through hole 31 is preferably a through hole, and the axial direction of the through hole is perpendicular to the plane of the substrate 30. In other embodiments, the through hole 31 may also be a slanted through hole. In an embodiment, the inner diameter of the through hole 31 is the same as the inner diameter of the via hole 13, and in this embodiment, a step structure is formed between the through hole 31 and the top of the insulating layer 40; in one embodiment, the inner diameter of the through hole 31 is the same as the inner diameter formed by the insulating layer 40, so that the redistribution layer 60 can extend on the flat inner wall surface, and the combination degree of the redistribution layer 60 and the inner wall surfaces of the through hole 31 and the via hole 13 is firmer; in another embodiment, the through hole 31 and the via hole 13 may form a double-step structure, and an average inner diameter of the through hole 31 is greater than an inner diameter of the via hole 13.
The insulating layer 40 also extends between the chip unit 10 and the substrate 30. The insulating layer 40 covers the inner wall surface of the via hole 13 and the second surface of the exposed chip unit, and when the substrate 30 is bonded to the chip unit 10, the insulating layer 40 can be clamped between the substrate 30 and the chip unit 10, so that edge warping of the edge of the insulating layer 40 can be avoided. In one embodiment, the material of the insulating layer is silicon dioxide.
The package structure 100 further includes a supporting structure 70, the supporting structure 70 is located between the first surface 11 of the chip unit 10 and the protective cover 20, and the sensing region 111 is located in a groove defined by the supporting structure 70 and the protective cover 20.
The package structure 100 further includes a solder mask 80, wherein the solder mask 80 covers the redistribution layer 60 and the through hole 31.
Example 2
Referring to fig. 2a to 2h, a packaging method according to an embodiment of the present invention includes the following steps.
Step s101, referring to fig. 2a, a chip unit 10 is provided, where the chip unit 10 includes a first surface 11 and a second surface 12 opposite to each other, the first surface has a sensing region 111 and a pad 112, and the pad 112 is electrically coupled to the sensing region 111.
In an embodiment, the sensing region 111 of the chip unit 10 is provided with a plurality of pixel points arranged in an array, and the chip unit 10 may be a capacitive sensing chip, such as a fingerprint identification chip. In another embodiment, the chip unit 10 may also be a photosensitive chip, such as an image sensor chip.
Step s102, referring to fig. 2b, a protective cover 20 is provided.
When the chip unit 10 is a photosensitive chip, in order to facilitate the sensing region 111 to sense the photosensitive information, the protective cover 20 is made of a transparent material, such as glass, which may be organic glass or inorganic glass.
Step s103, referring to fig. 2c, a support structure 70 is fabricated on the surface of the protective cover 20.
Step s104, referring to fig. 2d, the protective cover 20 is bonded to the first surface 11 of the chip unit 10. Wherein, the supporting structure 70 is located between the first surface 11 of the chip unit 10 and the protective cover 20, and the sensing region 111 is located in the groove 13 enclosed by the supporting structure 70 and the protective cover 20.
Step s105, referring to fig. 2e, thinning the second surface 12 of the chip unit 10, and controlling the thickness of the chip unit 10 to be less than 60 μm. The thinning can be performed by mechanical grinding or chemical etching.
Step s106, referring to fig. 2f, forming a via hole 13 penetrating through the chip unit on the second surface 12 of the chip unit 10, where the via hole 13 exposes the pad 112.
The aspect ratio b/a of the via 13 is less than 1, and in a preferred embodiment, the width (inner diameter) of the via 13 is 40 μm to 60 μm, more preferably 40 μm to 55 μm, and may be 45 μm, 47 μm, or 50 μm, for example. The via 13 is used to expose the pad 112, so that the solder bump 50 is electrically connected to the pad 112. In one embodiment, the vias 13 are through holes, on one hand, the axes of which are perpendicular to the surface on which the chip units are located, and on the other hand, the vias 13 have the same aperture in their axial direction.
Step s107, referring to fig. 2g, an insulating layer 40 is formed covering the second surface 12 of the chip unit 10 and the sidewalls of the via hole 13.
Step s108, referring to fig. 2h, providing a substrate 30, and forming a through hole 31 communicating with the via hole 13 on the substrate 30.
The substrate 30 is bonded to the second surface 12 of the chip unit 10.
The substrate 30 may be made of glass, which may be organic glass or inorganic glass. The substrate 30 is provided to ensure the strength of the package and to control the thickness of the package, so that the thickness of the substrate 30 is 100 μm to 120 μm, preferably 100 μm to 110 μm, such as 103 μm, 105 μm, and 108 μm.
Step s109, referring to fig. 1, a bonding bump 50 is formed on the surface of the substrate 30 away from the chip unit 10, and the bonding bump 50 is electrically connected to the bonding pad 112 through the redistribution layer 60 disposed in the via hole 13 and the via hole. Finally, a solder mask 80 is formed to cover the redistribution layer 60 and the through holes 31.
In step s103, the supporting structure 70 may be fabricated on the first surface 11 of the chip unit 10, and then the protective cover 20 is bonded to the chip unit 10.
In step s108, the substrate 30 and the chip unit 10 may be bonded, and then the through hole 31 may be formed in the substrate 30.
Example 3
Referring to fig. 3, and fig. 2a to 2h, a packaging method according to an embodiment of the present invention includes the following steps.
Step s201, a wafer 200 is provided, and the wafer includes a plurality of chip units 100 arranged in an array.
Wherein figure 2a is a cross-sectional view in the direction a-a' in figure 3. Each of the chip units includes a first surface 11 and a second surface 12 opposite to each other, the first surface has a sensing region 111 and a pad 112, and the pad 112 is electrically coupled to the sensing region 111.
In an embodiment, the sensing region 111 of the chip unit 10 is provided with a plurality of pixel points arranged in an array, and the chip unit 10 may be a capacitive sensing chip, such as a fingerprint identification chip. In another embodiment, the chip unit 10 may also be a photosensitive chip, such as an image sensing chip.
Step s202, referring to fig. 2b, provides a protective cover 20.
When the chip unit 10 is a photosensitive chip, in order to facilitate the sensing area 111 to sense the photosensitive information, the protective cover 20 is made of a transparent material, such as glass, which may be organic glass or inorganic glass.
Step s203, referring to fig. 2c, a support structure 70 is fabricated on the surface of the protective cover 20.
Step s204, referring to fig. 2d, the protective cover 20 is bonded to the first surface 11 of the chip unit 10. Wherein, the supporting structure 70 is located between the first surface 11 of the chip unit 10 and the protective cover 20, and the sensing region 111 is located in the groove 13 enclosed by the supporting structure 70 and the protective cover 20.
Step s205, referring to fig. 2e, the second surface 12 of the chip unit 10 is thinned, and the thickness of the chip unit 10 is controlled to be less than 60 μm. The thinning can be performed by mechanical grinding or chemical etching.
Step s206, referring to fig. 2f, a via hole 13 penetrating through the chip unit is formed on the second surface 12 of the chip unit 10, and the pad 112 is exposed from the via hole 13.
The aspect ratio b/a of the via 13 is less than 1, and in a preferred embodiment, the width (inner diameter) of the via 13 is 40 μm to 60 μm, more preferably 40 μm to 55 μm, and may be 45 μm, 47 μm, or 50 μm, for example. The via 13 is used to expose the pad 112, so that the solder bump 50 is electrically connected to the pad 112. In one embodiment, the vias 13 are through holes, on one hand, the axes of which are perpendicular to the surface on which the chip units are located, and on the other hand, the vias 13 have the same aperture in their axial direction.
Step s207, referring to fig. 2g, an insulating layer 40 is formed covering the second surface 12 of the chip unit 10 and the sidewalls of the via hole 13.
Step s208, referring to fig. 2h, a substrate 30 is provided, and a through hole 31 communicating with the via hole 13 is formed on the substrate 30.
The substrate 30 is bonded to the second surface 12 of the chip unit 10.
The substrate 30 may be made of glass, which may be organic glass or inorganic glass. The substrate 30 is provided to ensure the strength of the package and to control the thickness of the package, so that the thickness of the substrate 30 is 100 μm to 120 μm, preferably 100 μm to 110 μm, such as 103 μm, 105 μm, and 108 μm.
Step s209, referring to fig. 1, a bonding bump 50 is formed on a surface of the substrate 30 away from the chip unit 10, and the bonding bump 50 is electrically connected to the bonding pad 112 through the redistribution layer 60 disposed in the via hole 13 and the via hole. Finally, a solder mask 80 is formed to cover the redistribution layer 60 and the through holes 31.
Step s210, referring to fig. 3, the wafer 200 is divided by a dicing process along the dicing channels 201 to form the package structure 100 of a plurality of chip units.
In step s203, the supporting structure 70 may be fabricated on the first surface 11 of the chip unit 10, and then the protective cover 20 is bonded to the chip unit 10.
In step s208, the substrate 30 and the chip unit 10 may be bonded, and then the through hole 31 may be formed in the substrate 30.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the utility model to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the utility model and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the utility model and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the utility model be defined by the claims and their equivalents.
Claims (8)
1. A package structure, comprising:
the chip unit comprises a first surface and a second surface which are opposite, the first surface is provided with an induction area and a welding pad, the welding pad is electrically coupled with the induction area, the second surface of the chip unit is provided with a through hole which penetrates through the chip unit, the through hole is used for exposing the welding pad, and the thickness of the chip unit is smaller than 60 mu m;
a protective cover plate opposite to the first surface of the chip unit;
the substrate is opposite to the second surface of the chip unit, and a through hole communicated with the through hole is formed in the substrate;
the insulating layer at least covers the inner wall of the via hole;
and the welding bulge is arranged on the surface of the substrate deviating from the chip unit and is electrically connected with the welding pad through a rewiring layer arranged in the through hole and the through hole.
2. The package structure of claim 1, wherein the via is a through via, and/or
The through hole is a through hole.
3. The package structure of claim 1 or 2, wherein a depth of the via is less than a width of the via.
4. The package structure of claim 3, wherein the width of the via is 40 μm to 60 μm.
5. The package structure of claim 1, wherein the substrate is bonded to the second surface of the chip unit.
6. The package structure of claim 1, wherein the substrate is made of a material selected from glass.
7. The package structure according to claim 1 or 5, wherein the substrate has a thickness of 100 μm to 120 μm.
8. The package structure of claim 1, further comprising a support structure located between the first surface of the chip unit and the protective cover, wherein the sensing region is located in a recess defined by the support structure and the protective cover.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220515607.3U CN217009176U (en) | 2022-03-10 | 2022-03-10 | Packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220515607.3U CN217009176U (en) | 2022-03-10 | 2022-03-10 | Packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217009176U true CN217009176U (en) | 2022-07-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220515607.3U Active CN217009176U (en) | 2022-03-10 | 2022-03-10 | Packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217009176U (en) |
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2022
- 2022-03-10 CN CN202220515607.3U patent/CN217009176U/en active Active
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