CN216981785U - Dynamic voltage conversion circuit - Google Patents
Dynamic voltage conversion circuit Download PDFInfo
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- CN216981785U CN216981785U CN202220125948.XU CN202220125948U CN216981785U CN 216981785 U CN216981785 U CN 216981785U CN 202220125948 U CN202220125948 U CN 202220125948U CN 216981785 U CN216981785 U CN 216981785U
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Abstract
The utility model provides a dynamic voltage conversion circuit, which comprises a linear voltage stabilizer, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein the first resistor is connected with the first resistor; an input voltage pin and an enabling pin of the linear voltage stabilizer are connected with an input voltage, and a grounding pin is grounded; one end of the first resistor and one end of the second resistor are connected with a voltage feedback pin of the linear voltage stabilizer, and the other end of the second resistor is connected with one end of the third resistor and one end of the fourth resistor; the other end of the third resistor is connected with the main control chip, and the other end of the fourth resistor is grounded; the other end of the first resistor is connected with an output voltage pin of the linear voltage stabilizer and is used as an output end of the dynamic voltage conversion circuit to provide power supply voltage for the post-stage circuit. On the basis of the existing conversion circuit, an MOS (metal oxide semiconductor) tube and a resistor are omitted, the design cost is more advantageous, the power consumption of the LDO device is lower, the performance is more stable, and the market competitiveness of the product can be improved more.
Description
Technical Field
The utility model relates to the technical field of dynamic voltage conversion, in particular to a dynamic voltage conversion circuit.
Background
In the existing circuit application, the situation that the port power supply adapts to the power supply voltage according to the actual requirement is often used, for example, a TF (also called Micro SD) or SD card interface which is often used by people, the main control chip supports the TF card function by itself, the TF card function is realized through an SDIO (Secure Digital Input and Output) interface protocol, when the main control chip supports the SDIO3.0 protocol, the power supply of the internal SDIO module can support 2 voltage modes of 1.8V and 3.3V, and the power supply voltage is Input from the outside. The device works in an SDIO3.0 mode (needing external TF/SD card support) when the power supply is 1.8V, works in an SDIO2.0 mode when the power supply voltage is 3.3V, and has a faster data transmission rate in the SDIO3.0 mode. Now, as shown in fig. 1, an IO port is used to control on/off of a MOS transistor QP1, so that whether a resistor RP4 and a resistor RP3 form a parallel connection relationship or not is determined, and thus the resistance of a feedback resistor is changed to achieve the purpose of adjusting an output voltage.
The technical problem with the circuit shown in fig. 1 is that:
an MOS tube is needed to be used for switch control, so that the cost of design materials is increased;
the switching state of the MOS tube is changed to have a certain time delay, so that the output level state also has a corresponding time delay;
the MOS tube needs certain driving capability for starting, and the general IO port may have insufficient driving condition to cause the MOS tube to be incapable of being normally opened and to cause the output voltage to be incapable of being adjusted;
using a 5V input voltage increases the power consumption consumed by the device itself, while increasing the product design risk.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a dynamic voltage conversion circuit, which can solve the problem of material cost increase in the prior art by reducing one MOS (metal oxide semiconductor) transistor and can solve other problems caused by the use of the MOS transistor in the prior art.
The purpose of the utility model is realized by the following technical scheme:
a dynamic voltage conversion circuit comprises a linear voltage stabilizer, a first resistor, a second resistor, a third resistor and a fourth resistor; the linear voltage stabilizer at least comprises an input voltage pin, an enabling pin, a voltage feedback pin, a grounding pin and an output voltage pin; the input voltage pin and the enable pin are connected with an input voltage, and the grounding pin is grounded; one end of the first resistor and one end of the second resistor are connected with the voltage feedback pin, and the other end of the second resistor is connected with one end of the third resistor and one end of the fourth resistor; the other end of the third resistor is connected with the main control chip, and the other end of the fourth resistor is grounded; the other end of the first resistor is connected with the output voltage pin and serves as an output end of the dynamic voltage conversion circuit to provide power supply voltage for a post-stage circuit.
Furthermore, the main control chip outputs a control signal to control the third resistor and the fourth resistor to be connected in series or in parallel, when the control signal is at a low level, the third resistor and the fourth resistor are connected in parallel, and when the control signal is at a high level, the third resistor and the fourth resistor are connected in series.
Further, the dynamic voltage conversion circuit further comprises an input filter circuit, and the input filter circuit is connected between an input voltage pin and a ground pin of the linear voltage regulator.
Further, the input filter circuit comprises a first capacitor and a second capacitor, after the first capacitor and the second capacitor are connected in parallel, one end of the first capacitor is connected with the input voltage pin, and the other end of the first capacitor is connected with the grounding pin.
Further, the dynamic voltage conversion circuit further comprises an output filter circuit, and the output filter circuit is connected between an output voltage pin of the linear voltage regulator and ground.
Furthermore, the output filter circuit comprises a third capacitor and a fourth capacitor, after the third capacitor and the fourth capacitor are connected in parallel, one end of the third capacitor is connected with the output voltage pin VOUT, and the other end of the third capacitor is grounded.
Further, the dynamic voltage conversion circuit further comprises an anti-surge device, and the anti-surge device is connected between the output voltage pin and the ground.
The dynamic voltage conversion circuit provided by the utility model has the advantages that an MOS (metal oxide semiconductor) tube and a resistor are omitted on the basis of the conventional conversion circuit, the design cost is more advantageous, the power consumption of an LDO (low dropout regulator) device is lower, the performance is more stable, and the market competitiveness of a product can be improved more.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit schematic of a prior art dynamic voltage conversion circuit;
fig. 2 is a schematic circuit diagram of the dynamic voltage conversion circuit of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be carried into practice or applied to various other specific embodiments, and various modifications and changes may be made in the details within the description and the drawings without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
A dynamic voltage conversion circuit is shown in FIG. 2 and includes a Low Dropout Regulator (LDO) UW1, a first resistor RW1, a second resistor RW2, a third resistor RW3, and a fourth resistor RW 4. The linear regulator UW1 includes at least an input voltage pin VIN, an enable pin EN, a voltage feedback pin FB, a ground pin GND, and an output voltage pin VOUT. The input voltage pin VIN and the enable pin EN are connected with the input voltage, and the grounding pin GND is grounded. One end of the first resistor RW1 and one end of the second resistor RW2 are connected to the voltage feedback pin FB, and the other end of the second resistor RW2 is connected to one end of the third resistor RW3 and one end of the fourth resistor RW 4. The other end of the third resistor RW3 is connected to the main control chip, and the other end of the fourth resistor RW4 is grounded. The other end of the first resistor RW1 is connected to the output voltage pin VOUT and serves as an output terminal of the dynamic voltage conversion circuit for outputting a supply voltage to a subsequent circuit.
Further, the dynamic voltage conversion circuit of the present invention further includes an input filter circuit, and the input filter circuit is connected between the input voltage pin VIN of the linear regulator UW1 and the ground pin GND. The input filter circuit may be any circuit capable of filtering impurities in the input voltage, and for explaining the present invention in more detail, the input filter circuit of the present invention is illustrated as follows, but the input filter circuit of the present invention is not limited thereto, and any circuit capable of implementing a filter function should be within the scope of the present invention.
Furthermore, the input filter circuit comprises a first capacitor CW1 and a second capacitor CW2, wherein after the first capacitor CW1 and the second capacitor CW2 are connected in parallel, one end of the first capacitor CW1 is connected to the input voltage pin VIN, and the other end of the first capacitor CW2 is connected to the ground pin GND.
Further, the dynamic voltage conversion circuit of the present invention further includes an output filter circuit, and the output filter circuit is connected between the output voltage pin VOUT of the linear regulator UW1 and ground. Similarly, the output filter circuit may be any circuit capable of filtering out impurities in the output voltage, and for explaining the present invention in more detail, the output filter circuit of the present invention is illustrated as follows, but the output filter circuit of the present invention is not limited thereto, and all that can achieve the filter function should be within the protection scope of the present invention.
Furthermore, the output filter circuit comprises a third capacitor CW3 and a fourth capacitor CW4, wherein after the third capacitor CW3 and the fourth capacitor CW4 are connected in parallel, one end of the third capacitor CW3 is connected to the output voltage pin VOUT, and the other end of the third capacitor CW4 is grounded.
Further, the dynamic voltage conversion circuit of the present invention further includes an anti-surge device DW1, and the anti-surge device DW1 is connected between the output voltage pin VOUT and ground. The anti-surge device can prevent instant high voltage (such as static electricity) from entering the chip to cause chip damage.
The working principle of the dynamic voltage conversion circuit of the utility model is as follows:
the input and output voltage drops of the existing LDO (low dropout regulator) device are very small, and by utilizing the characteristics of the device, the original circuit is improved into the circuit shown in FIG. 2, UW1 is the LDO (low dropout regulator), the input voltage is VDDIO _3V3(3.3V voltage), VDDIO _1V8/3V3 is an LDO output network, and 1.8V and 3.3V voltages can be output. The master control chip controls the series connection or the parallel connection of the third resistor RW3 and the fourth resistor RW4 by outputting the VDDIOC _ SW signal, so as to control the output voltage of the LDO. When VDDIOC _ SW is at a low level, the third resistor RW3 and the fourth resistor RW4 form a parallel connection relationship, the equivalent resistor after the parallel connection is recorded as RW34, the second resistor RW2 forms a series resistor with RW34, and then is connected in series with the pull-up resistor RW1 according to a formula
The voltage value V of the output pin of the LDO can be calculatedout。
In the above formula: ruIs the value of pull-up resistor RW1, RdFor an equivalent resistance value formed by pull-down resistors, namely a second resistor RW2, a third resistor RW3 and a fourth resistor RW4, when the high level of the VDDIOC _ SW network at the main control chip end is 1.8V, the low level is 0V, and the VDDIOC _ SW network is 0V, the network voltage of the LDO output VDDIO _1V8/3V3 is 3.4V through a calculation formula theory, but because the LDO can only reduce voltage and can not increase voltage, the output voltage can only follow the input voltage, and the network voltage of the VDDIO _1V8/3V3 is also 3.3V at the moment; when VDDIOC _ SW is 1.8V (high level), the third resistor RW3 and the fourth resistor RW4 are connected in series, the currents on RW1, RW2 and RW4 are calculated through the principle of current equivalence, and then VDDIO _1V8/3 is obtainedThe V3 network is 1.8V, and similarly, other voltage values lower than the input voltage can be obtained by changing the resistances of the resistors RW1, RW2, RW3 and RW4 and the high-level voltage of the VDDIOC _ SW network. The capacitors CW 1-CW 4 are filter capacitors for input and output of the LDO device, reduce the ripple voltage of the input and output, and are energy storage capacitors.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The above description is for the purpose of illustrating embodiments of the utility model and is not intended to limit the utility model, and it will be apparent to those skilled in the art that any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the utility model shall fall within the protection scope of the utility model.
Claims (7)
1. A dynamic voltage conversion circuit is characterized by comprising a linear voltage stabilizer, a first resistor, a second resistor, a third resistor and a fourth resistor; the linear voltage stabilizer at least comprises an input voltage pin, an enabling pin, a voltage feedback pin, a grounding pin and an output voltage pin; the input voltage pin and the enable pin are connected with an input voltage, and the grounding pin is grounded; one end of the first resistor and one end of the second resistor are connected with the voltage feedback pin, and the other end of the second resistor is connected with one end of the third resistor and one end of the fourth resistor; the other end of the third resistor is connected with the main control chip, and the other end of the fourth resistor is grounded; the other end of the first resistor is connected with the output voltage pin and serves as an output end of the dynamic voltage conversion circuit to provide power supply voltage for a rear-stage circuit.
2. The dynamic voltage conversion circuit of claim 1, wherein the main control chip outputs the control signal to control the third resistor and the fourth resistor to be connected in series or in parallel, and when the control signal is low, the third resistor and the fourth resistor are connected in parallel, and when the control signal is high, the third resistor and the fourth resistor are connected in series.
3. The dynamic voltage conversion circuit of claim 1, further comprising an input filter circuit connected between an input voltage pin and a ground pin of the linear regulator.
4. The dynamic voltage conversion circuit of claim 3, wherein the input filter circuit comprises a first capacitor and a second capacitor, and after the first capacitor and the second capacitor are connected in parallel, one end of the first capacitor is connected to the input voltage pin, and the other end of the first capacitor is connected to the ground pin.
5. The dynamic voltage conversion circuit of claim 1 or 3, further comprising an output filter circuit connected between an output voltage pin of the linear regulator and ground.
6. The dynamic voltage conversion circuit of claim 5, wherein the output filter circuit comprises a third capacitor and a fourth capacitor, and after the third capacitor and the fourth capacitor are connected in parallel, one end of the third capacitor is connected to the output voltage pin VOUT, and the other end of the third capacitor is grounded.
7. The dynamic voltage conversion circuit of claim 5, further comprising an anti-surge device connected between the output voltage pin and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220125948.XU CN216981785U (en) | 2022-01-18 | 2022-01-18 | Dynamic voltage conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220125948.XU CN216981785U (en) | 2022-01-18 | 2022-01-18 | Dynamic voltage conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216981785U true CN216981785U (en) | 2022-07-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220125948.XU Active CN216981785U (en) | 2022-01-18 | 2022-01-18 | Dynamic voltage conversion circuit |
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| Country | Link |
|---|---|
| CN (1) | CN216981785U (en) |
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- 2022-01-18 CN CN202220125948.XU patent/CN216981785U/en active Active
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