CN216980093U

CN216980093U - Display driving chip and LED lamp panel

Info

Publication number: CN216980093U
Application number: CN202122944376.6U
Authority: CN
Inventors: 李晓; 王伙荣
Original assignee: Xi'an Ti Pt Sr Electronic Technology Co ltd
Current assignee: Xi'an Ti Pt Sr Electronic Technology Co ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2022-07-15
Anticipated expiration: 2031-11-26

Abstract

The embodiment of the utility model discloses a display driving chip and an LED lamp panel. The display driving chip includes: a shadow eliminating configuration circuit; the shadow eliminating circuit is electrically connected with the shadow eliminating configuration circuit; the shadow eliminating configuration circuit outputs a shadow eliminating adjusting signal and a shadow eliminating control signal; after the shadow elimination function is started, the shadow elimination circuit determines to work in a target shadow elimination mode in a plurality of shadow elimination modes based on the shadow elimination control signal, and controls the voltage of the diode electrode end of the light-emitting diode to rise or fall based on the shadow elimination adjustment signal in the target shadow elimination mode. The display driving chip disclosed by the embodiment of the utility model provides multiple shadow elimination modes and the shadow elimination capability is adjustable.

Description

Display driving chip and LED lamp panel

Technical Field

The utility model relates to the technical field of display control, in particular to a display driving chip and an LED lamp panel.

Background

The current LED driving scheme controls the on/off of the corresponding LED by controlling the voltages of the anode and the cathode of the LED lamp in the LED array, and controls the brightness of the LED by controlling the current flowing through the LED and the turn-on time. Wherein, the row line and the row line in the LED array all have parasitic capacitance, and parasitic capacitance derives from lamp plate PCB and walks the line, shows the in-process at the LED lamp plate, and parasitic capacitance can be charged for store corresponding electric charge on its bipolar plate, and can not disappear along with the outage, and parasitic capacitance can continue to maintain the voltage size before the disconnection promptly after the outage promptly, and these parasitic capacitances can lead to LED to produce the ghost like this, and the LED that should not light promptly still can give out light, seriously influences the display effect.

In order to solve the above problems, currently, a shadow eliminating technology is adopted to process the voltages of the anode and the cathode of the LED lamp, however, although the related shadow eliminating technology can eliminate the ghost shadow, the shadow eliminating scheme is single, the shadow eliminating scheme cannot be adjusted according to different application requirements, and the shadow eliminating capability cannot be adjusted.

Therefore, it is an urgent need to provide a shadow elimination scheme with adjustable shadow elimination scheme and adjustable shadow elimination capability.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defects and shortcomings of the prior art, the embodiment of the utility model provides a display driving chip and an LED lamp panel.

In one aspect, a display driving chip provided in an embodiment of the present invention includes: a shadow eliminating configuration circuit; the shadow eliminating circuit is electrically connected with the shadow eliminating configuration circuit; the image elimination configuration circuit outputs an image elimination adjusting signal and an image elimination control signal; after the shadow elimination function is started, the shadow elimination circuit determines to work in a target shadow elimination mode in a plurality of shadow elimination modes based on the shadow elimination control signal, and controls the voltage of the diode electrode end of the light-emitting diode to rise or fall based on the shadow elimination adjustment signal in the target shadow elimination mode.

The display driving chip is provided with the shadow elimination configuration circuit and the shadow elimination circuit, and the shadow elimination circuit determines to work in a target shadow elimination mode in a plurality of shadow elimination modes based on the shadow elimination control signal after the shadow elimination function is started, namely the shadow elimination circuit can realize a plurality of shadow elimination modes, so that the condition that the existing shadow elimination scheme is single and cannot be subjected to scheme adjustment aiming at the blind application requirement can be avoided; in addition, the shadow elimination circuit disclosed by the utility model can realize line shadow elimination and column shadow elimination by setting the shadow elimination adjusting signal to control the voltage rise or fall of the electrode terminal of the diode based on the shadow elimination adjusting signal, and realizes the adjustability of the shadow elimination capability by setting the shadow elimination adjusting signal, namely, a user can flexibly set the shadow elimination adjusting signal according to the actual working condition of the display driving chip to adjust the shadow elimination capability, thereby solving the problems of EMI (electro-magnetic interference) caused by too fast shadow elimination capability and too slow shadow elimination capability occupying too much display time, and the shadow elimination circuit can effectively remove the ghost phenomenon in the LED display process and improve the display effect.

In one embodiment of the present invention, the display driving chip further includes: the shadow eliminating protection circuit is electrically connected with the shadow eliminating circuit and the shadow eliminating configuration circuit; the shadow elimination protection circuit acquires a port voltage signal of the diode electrode end and a preset voltage signal input by the shadow elimination configuration circuit to generate a shadow elimination enabling signal, and outputs the shadow elimination enabling signal to the shadow elimination circuit to control whether the shadow elimination function is started or not.

Through set up the protection circuit that disappears in showing driver chip, can avoid current shadow scheme of disappearing to be in the condition that LED influences the LED life-span that the anti-partially state is for a long time when carrying out the shadow, realized that the automation of shadow function of disappearing is opened or is closed, adaptability and practicality are better.

In one embodiment of the present invention, the image erasing circuit includes: the first shadow eliminating control module is electrically connected with the shadow eliminating configuration circuit; the first shadow elimination execution module is electrically connected with the first shadow elimination control module; wherein the plurality of vanishing modes include a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: a first, a second and a third vanishing control signals; the first shadow elimination control module receives the first shadow elimination control signal, the second shadow elimination control signal and the shadow elimination adjusting signal; when the first and second vanishing control signals indicate that the vanishing function is turned on and the first vanishing control signal indicates that the first vanishing mode is the target vanishing mode, the first vanishing control module generates a vanishing execution signal based on a reference voltage signal, a first chip voltage signal and the vanishing adjustment signal, and the first vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or when the first and second vanishing control signals indicate that the vanishing function is turned on and the second and third vanishing control signals received by the first vanishing control module indicate that the second vanishing mode is the target vanishing mode, the first vanishing control module generates a vanishing execution signal based on a bias voltage signal, a second chip voltage signal and the vanishing adjustment signal, and the first vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or when the first and second shadow elimination control signals represent that the shadow elimination function is turned on, and the second and third shadow elimination control signals received by the first shadow elimination control module represent that the third shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module generates a shadow elimination execution signal based on the shadow elimination adjustment signal, and the first shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal.

In an embodiment of the present invention, the first vanishing control module includes: the first mode control unit is electrically connected with the first shadow elimination execution module and the shadow elimination configuration circuit; the first shadow eliminating adjusting unit is electrically connected with the first mode control unit and the shadow eliminating configuration circuit; wherein the first mode control unit receives the first, second and third vanishing control signals to determine the target vanishing mode, wherein when the first vanishing mode is the target vanishing mode, the first vanishing adjusting unit generates the vanishing performing signal based on the reference voltage signal, the first chip voltage signal and the vanishing adjusting signal and outputs the vanishing performing signal to the first vanishing performing module via the first mode control unit; or when the second vanishing mode is the target vanishing mode, the first vanishing adjusting unit generates the vanishing executing signal based on the bias voltage signal, the second chip voltage signal and the vanishing adjusting signal and outputs the vanishing executing signal to the first vanishing executing module through the first mode control unit; or when the third vanishing mode is the target vanishing mode, the first mode control unit generates the vanishing execution signal based on the vanishing adjustment signal and outputs the vanishing execution signal to the first vanishing execution module.

In one embodiment of the present invention, the first mode control unit includes: the first control selector is connected with the first shadow elimination adjusting unit at a first input end, connected with a first signal source at a second input end, connected with the shadow elimination configuration circuit to receive the first shadow elimination control signal at a selection end, and connected with the first shadow elimination execution module at an output end; a first input end of the first control selector is connected with the first shadow elimination adjusting unit, a second input end of the second control selector is connected with the shadow elimination configuration circuit, and a selection end of the second control selector is connected with the shadow elimination configuration circuit to receive the third shadow elimination control signal; and the first input end of the third control selector is connected with the output end of the second control selector, the second input end of the third control selector is connected with the second signal source, the selection end of the third control selector is connected with the vanishing configuration circuit to receive the second vanishing control signal, and the output end of the third control selector is connected with the first vanishing execution module.

In one embodiment of the present invention, the image erasing circuit includes: the second shadow eliminating control module is electrically connected with the shadow eliminating configuration circuit and the shadow eliminating protection circuit; the second shadow elimination execution module is electrically connected with the second shadow elimination control module; wherein the plurality of vanishing modes include a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: a first, a second and a third vanishing control signals; the second shadow elimination control module receives the shadow elimination enabling signal, the first shadow elimination control signal, the second shadow elimination control signal and the shadow elimination adjusting signal, generates a first shadow elimination configuration signal based on the shadow elimination enabling signal and the first shadow elimination control signal and generates a second shadow elimination configuration signal based on the shadow elimination enabling signal and the second shadow elimination control signal; when the first and second vanishing configuration signals represent that the vanishing function is turned on and the first vanishing configuration signal represents that the first vanishing mode is the target vanishing mode, the second vanishing control module generates a vanishing execution signal based on a reference voltage signal, a first chip voltage signal and the vanishing adjustment signal, and the second vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or when the first and second vanishing configuration signals represent that the vanishing function is turned on, and the second vanishing configuration signal and the third vanishing control signal received by the second vanishing control module represent that the second vanishing mode is the target vanishing mode, the second vanishing control module generates a vanishing execution signal based on a bias voltage signal, a second chip voltage signal and the vanishing adjustment signal, and the second vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or when the first and second vanishing configuration signals indicate that the vanishing function is turned on, and the second and third vanishing control signals received by the second vanishing control module indicate that the third vanishing mode is the target vanishing mode, the second vanishing control module generates a vanishing execution signal based on the vanishing adjustment signal, and the second vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal.

In an embodiment of the present invention, the second vanishing control module includes: the second mode control unit is electrically connected with the second shadow elimination execution module, the shadow elimination configuration circuit and the shadow elimination protection circuit; the second shadow elimination adjusting unit is electrically connected with the second mode control unit and the shadow elimination configuration circuit; wherein the second mode control unit receives the vanishing enable signal, the first vanishing control signal, the second vanishing control signal, and the third vanishing control signal to determine the target vanishing mode, wherein when the first vanishing mode is the target vanishing mode, the second vanishing adjusting unit generates the vanishing performing signal based on the reference voltage signal, the first chip voltage signal, and the vanishing adjusting signal and outputs the vanishing performing signal to the second vanishing performing module via the second mode control unit; or when the second vanishing mode is the target vanishing mode, the second vanishing adjusting unit generates the vanishing executing signal based on the bias voltage signal, the second chip voltage signal and the vanishing adjusting signal and outputs the vanishing executing signal to the second vanishing executing module through the second mode control unit; or when the third vanishing mode is the target vanishing mode, the second mode control unit generates the vanishing execution signal based on the vanishing adjustment signal and outputs the vanishing execution signal to the second vanishing execution module.

In one embodiment of the present invention, the second mode control unit includes: the first input end of the first AND gate is connected with the shadow eliminating configuration circuit to receive the first shadow eliminating control signal, and the second input end of the first AND gate is connected with the shadow eliminating protection circuit to receive the shadow eliminating enabling signal; a fourth control selector, a first input end of which is connected with the second vanishing adjusting unit, a second input end of which is connected with the first signal source, a selection end of which is connected with the output end of the first and gate to receive the first vanishing configuration signal, and an output end of which is connected with the second vanishing executing module; a fifth control selector, a first input end of which is connected with the second vanishing adjusting unit, a second input end of which is connected with the vanishing configuration circuit, and a selection end of which is connected with the vanishing configuration circuit to receive the third vanishing control signal; the first input end of the second AND gate is connected with the shadow eliminating configuration circuit to receive the second shadow eliminating control signal, and the second input end of the second AND gate is connected with the shadow eliminating protection circuit to receive the shadow eliminating enabling signal; and a sixth control selector, wherein the first input end of the sixth control selector is connected with the output end of the fifth control selector, the second input end of the sixth control selector is connected with the second signal source, the selection end of the sixth control selector is connected with the output end of the second and gate to receive the second vanishing configuration signal, and the output end of the sixth control selector is connected with the second vanishing executing module.

In one embodiment of the present invention, the first vanishing adjusting unit includes: the first input end of the first adjusting selector is connected with the vanishing configuration circuit, the second input end of the first adjusting selector is connected with the first signal source, the selecting end of the first adjusting selector is connected with the vanishing configuration circuit, and the output end of the first adjusting selector is connected with the first mode control unit; and a second adjusting selector, wherein the first input end is connected with the constant current source generating circuit, the second input end is connected with the second signal source, the selecting end is connected with the vanishing configuration circuit, and the output end is connected with the first mode control unit.

In an embodiment of the present invention, the first shadow elimination execution module includes: the first shadow elimination execution unit is connected with the first shadow elimination control module; the second shadow elimination execution unit is connected with the first shadow elimination control module, and the first shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal in the first shadow elimination mode and outputs the shadow elimination current to the diode electrode end; or the second shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal in the second shadow elimination mode or the third shadow elimination mode.

In an embodiment of the present invention, the second vanishing performing module includes: the third shadow elimination execution unit is connected with the second shadow elimination control module; the fourth shadow elimination execution unit is connected with the second shadow elimination control module, and the third shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal in the first shadow elimination mode and outputs the shadow elimination current to the diode electrode terminal; or the fourth shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal in the second shadow elimination mode or the third shadow elimination mode.

In one embodiment of the present invention, the second vanishing adjusting unit includes: a first input end of the first adjustment selector is connected with the first signal source, a second input end of the first adjustment selector is connected with the second signal source, a selection end of the first adjustment selector is connected with the second signal source, and an output end of the first adjustment selector is connected with the second mode control unit; and a fourth adjusting selector, wherein the first input end of the fourth adjusting selector is connected with the constant current source generating circuit, the second input end of the fourth adjusting selector is connected with the second signal source, the selecting end of the fourth adjusting selector is connected with the vanishing configuration circuit, and the output end of the fourth adjusting selector is connected with the second mode control unit.

In an embodiment of the present invention, the first shadow elimination execution unit includes: a control end of the first switch element is connected with the first shadow elimination control module, an output end of the first switch element is connected with the diode electrode end, and an input end of the first switch element is connected with the second signal source; and the second shadow elimination execution unit comprises: and the control end of the second switch element is connected with the first shadow elimination control module, the output end of the second switch element is connected with the diode electrode end, and the input end of the second switch element is connected with the second signal source.

In an embodiment of the present invention, the third shadow elimination execution unit includes: a control end of the third switching element is connected with the second shadow elimination control module, an output end of the third switching element is connected with the diode electrode end, and an input end of the third switching element is connected with the second signal source; and the fourth shadow elimination execution unit comprises: and the control end of the fourth switching element is connected with the second shadow elimination control module, the output end of the fourth switching element is connected with the diode electrode end, and the input end of the fourth switching element is connected with the second signal source.

In one embodiment of the present invention, the shadow protection circuit includes: and the voltage comparison unit is electrically connected with the shadow eliminating configuration circuit and the diode electrode end and generates the shadow eliminating enabling signal based on the port voltage signal and the preset voltage signal.

On the other hand, an embodiment of the present invention provides an LED lamp panel, including: a display unit array including a plurality of display units, each of the display units including a plurality of light emitting diodes; and any one of the display driving chips, wherein the shadow eliminating circuit of the display driving chip is connected with the diode electrode end of the light emitting diode.

One or more of the above technical solutions may have the following advantages or beneficial effects: the display driving chip is provided with the shadow elimination configuration circuit and the shadow elimination circuit, and the shadow elimination circuit determines to work in a target shadow elimination mode in a plurality of shadow elimination modes based on the shadow elimination control signal after the shadow elimination function is started, namely the shadow elimination circuit can realize a plurality of shadow elimination modes, so that the condition that the existing shadow elimination scheme is single and cannot be subjected to scheme adjustment aiming at the blind application requirement can be avoided; in addition, the shadow elimination circuit disclosed by the utility model can realize row shadow elimination and column shadow elimination by setting the shadow elimination adjusting signal to control the voltage of the electrode end of the diode to rise or fall, and in addition, the adjustability of the shadow elimination capability is realized by setting the shadow elimination adjusting signal, namely, a user can flexibly set the shadow elimination adjusting signal according to the actual working condition of the display driving chip to adjust the shadow elimination capability, so that the problems that EMI is generated when the shadow elimination capability is too fast and the shadow elimination capability occupies too much display time when the shadow elimination capability is too slow are solved, the shadow elimination circuit can effectively remove the ghost phenomenon in the LED display process, and the display effect is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display driver chip according to an embodiment of the present invention.

Fig. 2 is another schematic structural diagram of a display driver chip according to an embodiment of the disclosure.

Fig. 3 is a schematic diagram of a specific structure of the display driver chip shown in fig. 1.

Fig. 4 is a schematic diagram of a specific structure of the display driver chip shown in fig. 2.

Fig. 5 is a schematic circuit structure diagram of a partial structure of an LED lamp panel according to an embodiment of the present invention.

Fig. 6 is a schematic circuit structure diagram of a partial structure of an LED lamp panel according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a circuit structure of the shading circuit in the display driver chip shown in FIG. 4, which is applied to perform row shading under the LED common cathode driving scheme.

FIG. 8 is a schematic diagram of a circuit structure of the display driver chip shown in FIG. 4, wherein the image elimination circuit is applied under the LED common cathode driving scheme to perform the following image elimination.

FIG. 9 is a schematic diagram of a circuit structure of a row-blanking circuit applied to the LED common-cathode driving scheme in the display driving chip shown in FIG. 3.

FIG. 10 is a schematic diagram of a circuit structure of a shadow elimination circuit applied in the LED common cathode driving scheme in the display driving chip shown in FIG. 3 for performing the following shadow elimination.

Description of the main component symbols:

100: a display driving chip; 10: a shadow eliminating circuit; 30: a shadow eliminating configuration circuit; 11 a: a first shadow elimination control module; 11 b: a second shadow elimination control module; 13 a: a first shadow elimination execution module; 13 b: a second shadow elimination execution module; 111 a: a first mode control unit; 111 b: a second mode control unit; 113 a: a first shading adjustment unit; 113 b: a second vanishing adjusting unit; 131 a: a first shadow elimination execution unit; 133 a: a second shadow elimination execution unit; 131 b: a third shadow elimination execution unit; 133 b: a fourth shadow elimination execution unit; 40: a shadow elimination protection circuit; 41: and a voltage comparison unit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, an embodiment of the present invention discloses a display driving chip 100, for example, including: a shadow-eliminating circuit 10 and a shadow-eliminating configuration circuit 30.

The shadow elimination configuration circuit 30 outputs a shadow elimination adjustment signal and a shadow elimination control signal. After the shadow elimination function is started, the shadow elimination circuit 10 determines to work in a target shadow elimination mode in a plurality of shadow elimination modes based on the shadow elimination control signal, and controls the voltage of the diode electrode end of the light-emitting diode to rise or fall based on the shadow elimination adjustment signal in the target shadow elimination mode.

The light emitting diodes are, for example, LEDs, and the diode electrode terminals may be understood as that the display driving chip 100 disclosed in this embodiment is used to connect display unit arrays to form an LED lamp panel, each display unit array includes a plurality of display units, each display unit includes a plurality of light emitting diodes, for example, three light emitting diodes, which respectively correspond to a red light emitting diode, a green light emitting diode, and a blue light emitting diode, each light emitting diode has two diode electrode terminals, that is, a positive electrode terminal and a negative electrode terminal, and the shadow eliminating circuit 10 of the display driving chip 100 disclosed in this embodiment may be connected to a positive electrode terminal or a negative electrode terminal of the light emitting diode. In addition, a plurality of the image erasing circuits 10 may be provided in one display driving chip 100, and the present embodiment does not limit the number of the image erasing circuits 10 in a single display driving chip 100, and the positive electrode terminal and the negative electrode terminal of each light emitting diode are connected to the image erasing circuits 10, for example.

The shadow configuration circuit 30 may be understood as a digital logic circuit inside an existing display driving chip, and for example, includes a plurality of registers, each of which outputs a signal correspondingly, or includes a controller, for example, which directly outputs a plurality of signals, and the specific structure of the shadow configuration circuit 30 is not described herein again.

In an embodiment of the present invention, as shown in fig. 3, the shadow elimination circuit 10 includes, for example: a first vanishing control module 11a and a first vanishing execution module 13 a. The first vanishing controlling module 11a is electrically connected to the vanishing configuring circuit 30, and the first vanishing executing module 13a is electrically connected to the first vanishing controlling module 11 a.

For example, the shadow elimination circuit 10 has a plurality of shadow elimination modes, and for example, includes a first shadow elimination mode, a second shadow elimination mode, and a third shadow elimination mode, and the shadow elimination control signal includes, for example: a first, a second and a third shadow elimination control signals.

Wherein the first shadow elimination control module 11a receives the first shadow elimination control signal, the second shadow elimination control signal and the shadow elimination adjustment signal;

when the first and second vanishing control signals indicate that the vanishing function is turned on and the first vanishing control signal indicates that the first vanishing mode is the target vanishing mode, the first vanishing control module 11a generates a vanishing executing signal based on a reference voltage signal, a first chip voltage signal and the vanishing adjusting signal, and the first vanishing executing module 13a generates a vanishing current based on the vanishing executing signal and outputs the vanishing current to the diode electrode terminal; or alternatively

When the first and second vanishing control signals indicate that the vanishing function is turned on, and the second and third vanishing control signals received by the first vanishing control module 11a indicate that the second vanishing mode is the target vanishing mode, the first vanishing control module 11a generates a vanishing execution signal based on a bias voltage signal, a second chip voltage signal and the vanishing adjustment signal, and the first vanishing execution module 13a generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or alternatively

When the first and second vanishing control signals indicate that the vanishing function is turned on, and the second and third vanishing control signals received by the first vanishing control module 11a indicate that the third vanishing mode is the target vanishing mode, the first vanishing control module 11a generates a vanishing execution signal based on the vanishing adjustment signal, and the first vanishing execution module 13a generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal.

In one embodiment of the present invention, referring to fig. 3, the first vanishing control module 11a includes: a first mode control unit 111a and a first shading adjustment unit 113 a. The first mode control unit 111a is electrically connected to the first shadow execution module 13a and the shadow configuration circuit 30. The first vanishing adjusting unit 113a is electrically connected to the first mode control unit 111a and the vanishing configuring circuit 30.

In one embodiment of the present invention, referring to fig. 3, the first vanishing performing module 13a includes: a first vanishing performing unit 131a and a second vanishing performing unit 133 a. The first vanishing executing unit 131a is connected to the first vanishing control module 11 a. The second vanishing performing unit 133a is connected to the first vanishing controlling module 11 a.

Specifically, as shown in fig. 1, the first mode control unit 111a is electrically connected to the first and second vanishing performing

units

131a and 133a, the first vanishing adjusting unit 113a, and the vanishing configuring circuit 30.

Wherein the first mode control unit 111a receives the first, second and third vanishing control signals to determine the target vanishing mode;

when the first vanishing mode is the target vanishing mode, the first vanishing adjusting unit 113a generates the vanishing performing signal based on the reference voltage signal, the first chip voltage signal and the vanishing adjusting signal and outputs the vanishing performing signal to the first vanishing performing module 13a via the first mode control unit 111a, for example, to the first vanishing performing unit 131a, so that it generates the vanishing current based on the vanishing performing signal in the first vanishing mode and outputs the vanishing current to the diode electrode terminal; or alternatively

When the second vanishing mode is the target vanishing mode, the first vanishing adjusting unit 113a generates the vanishing executing signal based on the bias voltage signal, the second chip voltage signal and the vanishing adjusting signal, and outputs the vanishing executing signal to the first vanishing executing module 13a via the first mode control unit 111a, for example, to a second vanishing executing unit 133a, so that the first vanishing executing unit generates the vanishing current based on the vanishing executing signal in the second vanishing mode and outputs the vanishing current to the diode electrode terminal; or

When the third vanishing mode is the target vanishing mode, the first mode control unit 111a generates the vanishing performing signal based on the vanishing adjusting signal and outputs the vanishing performing signal to the first vanishing performing module 13a, for example, to the second vanishing performing unit 133a, so that the first vanishing performing module generates the vanishing current based on the vanishing performing signal and outputs the vanishing current to the diode electrode terminal in the third vanishing mode.

Specifically, the first mode control unit 111a includes, for example: a first control selector, a second control selector, and a third control selector. The first input end of the first control selector is connected with the first vanishing adjusting unit, the second input end of the first control selector is connected with the first signal source, the selecting end of the first control selector is connected with the vanishing configuration circuit to receive the first vanishing control signal, and the output end of the first control selector is connected with the first vanishing executing module. And a first input end of the second control selector is connected with the first vanishing adjusting unit, a second input end of the second control selector is connected with the vanishing configuration circuit, and a selection end of the second control selector is connected with the vanishing configuration circuit to receive the third vanishing control signal. And the first input end of the third control selector is connected with the output end of the second control selector, the second input end of the third control selector is connected with the second signal source, the selection end of the third control selector is connected with the vanishing configuration circuit to receive the second vanishing control signal, and the output end of the third control selector is connected with the first vanishing execution module.

Specifically, the first vanishing adjusting unit 113a includes, for example: a first adjustment selector and a second adjustment selector. The first input end of the first adjusting selector is connected with the vanishing configuration circuit, the second input end of the first adjusting selector is connected with the first signal source, the selecting end of the first adjusting selector is connected with the vanishing configuration circuit, and the output end of the first adjusting selector is connected with the first mode control unit. And the first input end of the second adjustment selector is connected with the constant current source generating circuit, the second input end of the second adjustment selector is connected with the second signal source, the selection end of the second adjustment selector is connected with the vanishing configuration circuit, and the output end of the second adjustment selector is connected with the first mode control unit.

Specifically, the first shadow execution unit 131a includes, for example: and the control end of the first switch element is connected with the first shadow eliminating control module, the output end of the first switch element is connected with the diode electrode end, and the input end of the first switch element is connected with the second signal source. The second vanishing performing unit 133a includes, for example: and the control end of the second switch element is connected with the first shadow elimination control module, the output end of the second switch element is connected with the diode electrode end, and the input end of the second switch element is connected with the second signal source.

In another embodiment of the present invention, as shown in fig. 2, the display driving chip 100 further includes: a shadow-eliminating protection circuit 40. The shadow elimination protection circuit 40 is electrically connected to the shadow elimination circuit 10 and the shadow elimination configuration circuit 30, the shadow elimination protection circuit 40 obtains a port voltage signal of the diode electrode terminal and a preset voltage signal input by the shadow elimination configuration circuit 30 to generate a shadow elimination enable signal, and outputs the shadow elimination enable signal to the shadow elimination circuit 10 to control whether to start the shadow elimination function.

In another embodiment of the present invention, as shown in fig. 4, the shadow circuit 10 shown in fig. 2 includes, for example: a second vanishing control module 11b and a second vanishing executing module 13 b.

Specifically, the second vanishing control module 11b electrically connects the vanishing configuring circuit 30 and the vanishing protection circuit 40. The second vanishing executing module 13b is electrically connected to the second vanishing controlling module 11 b.

The image erasing circuit 10 has a plurality of image erasing modes, for example, including: a first elimination mode, a second elimination mode and a third elimination mode; the shadow elimination control signal comprises: a first, a second and a third shadow elimination control signals. The second shadow elimination control module 11b receives the shadow elimination enable signal, the first shadow elimination control signal, the second shadow elimination control signal and the shadow elimination adjustment signal, generates a first shadow elimination configuration signal based on the shadow elimination enable signal and the first shadow elimination control signal, and generates a second shadow elimination configuration signal based on the shadow elimination enable signal and the second shadow elimination control signal;

when the first and second vanishing configuration signals indicate that the vanishing function is turned on and the first vanishing configuration signal indicates that the first vanishing mode is the target vanishing mode, the second vanishing control module 11b generates a vanishing execution signal based on a reference voltage signal, a first chip voltage signal and the vanishing adjustment signal, and the second vanishing execution module 13b generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or

When the first and second vanishing configuration signals indicate that the vanishing function is turned on, and the second and third vanishing control signals received by the second vanishing control module 11b indicate that the second vanishing mode is the target vanishing mode, the second vanishing control module 11b generates a vanishing execution signal based on a bias voltage signal, a second chip voltage signal and the vanishing adjustment signal, and the second vanishing execution module 13b generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the electrode diode terminal; or alternatively

When the first and second vanishing configuration signals indicate that the vanishing function is turned on, and the second and third vanishing control signals received by the second vanishing control module 11b indicate that the third vanishing mode is the target vanishing mode, the second vanishing control module 11b generates a vanishing execution signal based on the vanishing adjustment signal, and the second vanishing execution module 13b generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal.

In one embodiment of the present invention, referring to fig. 4, the second vanishing control module 11b includes, for example: a second mode control unit 111b and a second shading adjustment unit 113 b. The second mode control unit 111b is electrically connected to the second shadow execution module 13b, the shadow configuration circuit 30, and the shadow protection circuit 40. The second vanishing adjusting unit 113b is electrically connected to the second mode control unit 111b and the vanishing configuring circuit 30.

As shown in fig. 4, the second vanishing executing module 13b includes: a third vanishing performing unit 131b and a fourth vanishing performing unit 133 b.

The third shadow elimination execution unit 131b is connected to the second shadow elimination control module 11 b. The fourth vanishing performing unit 133b is connected to the second vanishing control module 11 b.

Specifically, as shown in fig. 4, the second mode control unit 111b is electrically connected to the third and fourth

shading execution units

131b and 133b, the second shading adjustment unit 113b, the shading configuration circuit 30, and the shading protection circuit 40.

Wherein the second mode control unit 111b receives the vanishing enable signal, the first vanishing control signal, the second vanishing control signal, and the third vanishing control signal to determine the target vanishing mode;

when the first vanishing mode is the target vanishing mode, the second vanishing adjusting unit 113b generates the vanishing performing signal based on the reference voltage signal, the first chip voltage signal and the vanishing adjusting signal, and outputs the vanishing performing signal to the second vanishing performing module 13b via the second mode control unit 111b, for example, to a third vanishing performing unit 131b, so that it generates the vanishing current based on the vanishing performing signal in the first vanishing mode and outputs the vanishing current to the diode electrode terminal; or

When the second vanishing mode is the target vanishing mode, the second vanishing adjusting unit 113b generates the vanishing executing signal based on the bias voltage signal, the second chip voltage signal and the vanishing adjusting signal, and outputs the vanishing executing signal to the second vanishing executing module 13b via the second mode control unit 111b, for example, to a fourth vanishing executing unit 133b, so that the second vanishing executing unit generates the vanishing current based on the vanishing executing signal in the second vanishing mode and outputs the vanishing current to the diode electrode terminal; or

When the third vanishing mode is the target vanishing mode, the second mode control unit 111b generates the vanishing performing signal based on the vanishing adjusting signal and outputs the vanishing performing signal to the second vanishing performing module 13b, for example, to the fourth vanishing performing unit 133b, so that it generates the vanishing current based on the vanishing performing signal in the third vanishing mode and outputs the vanishing current to the diode electrode terminal.

In one embodiment of the present invention, as shown in fig. 4, the shadow protection circuit 40 includes, for example: a voltage comparison unit 41.

The voltage comparing unit 41 is electrically connected to the shadow elimination configuration circuit 30 and the diode electrode terminal, and generates the shadow elimination enable signal based on the port voltage signal and the preset voltage signal, and outputs the shadow elimination enable signal to the second mode control unit 111b of the second shadow elimination control module 11 b.

Specifically, the second mode control unit 111b includes, for example: the first AND gate, the second AND gate, the fourth control selector, the fifth control selector and the sixth control selector. The first input end of the first AND gate is connected with the shadow eliminating configuration circuit to receive the first shadow eliminating control signal, and the second input end of the first AND gate is connected with the shadow eliminating protection circuit to receive the shadow eliminating enabling signal. And a fourth control selector, wherein the first input end of the fourth control selector is connected with the second vanishing adjusting unit, the second input end of the fourth control selector is connected with the first signal source, the selection end of the fourth control selector is connected with the output end of the first AND gate to receive the first vanishing configuration signal, and the output end of the fourth control selector is connected with the second vanishing executing module. And a fifth control selector, wherein a first input end of the fifth control selector is connected with the second vanishing adjusting unit, a second input end of the fifth control selector is connected with the vanishing configuration circuit, and a selection end of the fifth control selector is connected with the vanishing configuration circuit to receive the third vanishing control signal. And the first input end of the second AND gate is connected with the shadow eliminating configuration circuit to receive the second shadow eliminating control signal, and the second input end of the second AND gate is connected with the shadow eliminating protection circuit to receive the shadow eliminating enabling signal. And a first input end of the sixth control selector is connected with the output end of the fifth control selector, a second input end of the sixth control selector is connected with a second signal source, a selection end of the sixth control selector is connected with the output end of the second AND gate to receive the second vanishing configuration signal, and an output end of the sixth control selector is connected with the second vanishing execution module.

Specifically, the second shading adjustment unit 113b includes, for example: a third adjustment selector and a fourth adjustment selector. And the first input end of the third adjusting selector is connected with the vanishing configuration circuit, the second input end of the third adjusting selector is connected with the first signal source, the selecting end of the third adjusting selector is connected with the vanishing configuration circuit, and the output end of the third adjusting selector is connected with the second mode control unit. And a first input end of the fourth adjusting selector is connected with the constant current source generating circuit, a second input end of the fourth adjusting selector is connected with the second signal source, a selecting end of the fourth adjusting selector is connected with the vanishing configuration circuit, and an output end of the fourth adjusting selector is connected with the second mode control unit.

Specifically, the third shadow elimination execution unit 131b includes, for example: and the control end of the third switching element is connected with the second shadow elimination control module, the output end of the third switching element is connected with the electrode end of the diode, and the input end of the third switching element is connected with the second signal source. The fourth vanishing performing unit 133b includes, for example: and the control end of the fourth switching element is connected with the second shadow elimination control module, the output end of the fourth switching element is connected with the diode electrode end, and the input end of the fourth switching element is connected with the second signal source.

It should be noted that most of the structures of the image elimination circuit in the display driving chip shown in fig. 3 and the image elimination circuit in the display driving chip shown in fig. 4 are the same, including:

1. the first shading adjustment unit 113a shown in fig. 3 has the same structure as the second shading adjustment unit 113b shown in fig. 4, that is, the first adjustment selector in the aforementioned first shading adjustment unit is the same as the third adjustment selector in the second shading adjustment unit, and the second adjustment selector in the first shading adjustment unit is the same as the fourth adjustment selector in the second shading adjustment unit.

2. The first vanishing performing module 13a shown in fig. 3 has the same structure as the second vanishing performing module 13b shown in fig. 4, that is: the first vanishing performing unit 131a shown in fig. 3 has the same structure as the third vanishing performing unit 131b shown in fig. 4, i.e. the first switch element in the first vanishing performing unit is the same as the third switch element in the third vanishing performing unit; and the second vanishing performing unit 133a shown in fig. 3 has the same structure as the fourth vanishing performing unit 133b shown in fig. 4, that is, the second switch element in the second vanishing performing unit is the same as the fourth switch element in the fourth vanishing performing unit.

3. The first mode control unit 111a shown in fig. 3 has the same structure as part of the second mode control unit 111b shown in fig. 4, that is, the first control selector in the first mode control unit 111a has the same structure as the fourth control selector in the second mode control unit 111b, the second control selector in the first mode control unit 111a has the same structure as the fifth control selector in the second mode control unit 111b, and the third control selector in the first mode control unit 111a has the same structure as the sixth control selector in the second mode control unit 111 b.

The main difference between the vanishing circuit 10 shown in fig. 3 and the vanishing circuit 10 shown in fig. 4 is that the second mode control unit 111b shown in fig. 4 further includes a first and a second and as compared to the first mode control unit 111a shown in fig. 3, that is, in the vanishing circuit 10 shown in fig. 3, the first mode control unit 111a controls whether the vanishing function is turned on or off by the first and the second vanishing control signals respectively received by the first and the second control selectors from the vanishing configuring circuit 30, so as to implement the non-automatic control of the turning on or off of the vanishing function. In the shadow elimination circuit 10 shown in fig. 4, the second mode control unit 111b receives the shadow elimination enable signal input from the shadow elimination protection circuit 40 and the first shadow elimination control signal and the second shadow elimination control signal from the shadow elimination configuration circuit 30 through the first and second and gates to output the first shadow elimination configuration signal and the second shadow elimination configuration signal to the fourth control selector and the fifth control selector, respectively, that is, the third control selector and the fourth control selector in the second mode control unit 111a shown in fig. 4 are the same in structure as the first control selector and the second control selector in the first mode control unit 111a shown in fig. 3, but receive different signals at their selection terminals, and the selection terminals of the third control selector and the fourth control selector in the second mode control unit 111a shown in fig. 4 receive the first shadow elimination configuration signal and the second shadow elimination configuration signal output by the first and second and gates, the selection terminals of the first control selector and the second control selector in the first mode control unit 111a shown in fig. 3 respectively receive the first vanishing control signal and the second vanishing control signal output by the vanishing configuration circuit, and the vanishing enable signal in the vanishing circuit shown in fig. 4 can control whether the vanishing function is turned on, so as to realize the automatic control of turning on or off of the vanishing function.

The display driving chip 100 disclosed in the foregoing embodiments is exemplified below.

As shown in fig. 5, the LED lamp panel includes, for example, a display unit array, the display unit array is formed by arranging a plurality of display units 210, and each display unit 210 includes, for example, a plurality of Light Emitting Diodes (LEDs), for example, 3 LEDs. As shown in fig. 5, the channels CHN1-CNH3 are respectively connected to a constant current source generating circuit, and the constant current source generating circuit outputs a driving current to light the LEDs in the corresponding channels.

The image elimination circuit 10 in the display driving chip 100 is connected to, for example, an LED electrode terminal, for example, as shown in fig. 5, two image elimination circuits 10 are respectively connected to a positive electrode terminal (point a) and a negative electrode terminal (point B) of the LED11 to perform row image elimination and column image elimination, that is, the image elimination circuit 10 disclosed in this embodiment can implement row image elimination and also implement column image elimination. It should be noted that fig. 5 shows an LED common cathode driving scheme, that is, the shadow eliminating circuit 10 disclosed in this embodiment is applicable to the LED common cathode driving scheme, and in addition, the shadow eliminating circuit 10 disclosed in this embodiment is also applicable to the LED common anode driving scheme.

As is apparent from the foregoing description, the shadow elimination circuit shown in fig. 4 has the same partial structure as that of the shadow elimination circuit shown in fig. 3, and for the convenience of embodying the shadow elimination circuit shown in fig. 3 and 4, the first adjustment selector and the third adjustment selector mentioned above are both referred to as adjustment selector BT1, the second adjustment selector and the fourth adjustment selector are both referred to as adjustment selector BT2, the first switching element and the third switching element are both referred to as switching element M1, the second switching element and the fourth switching element are both referred to as switching element M2, the first control selector and the fourth control selector are both referred to as control selector BC1, the second control selector and the fifth control selector are both referred to as control selector BC2, and the third control selector and the sixth control selector are both referred to as BC 3.

The operation of the display driver chip shown in fig. 4 will be described with reference to fig. 6 to 8.

First, the operation principle of the shadow protection circuit 40 will be described. As shown in fig. 6, the voltage comparing unit 41 of the shadow protection circuit 40 includes, for example, a comparator C1, and the comparator C1 receives the port voltage signal and the preset voltage signal DEG _ VREF from the shadow configuration circuit 30 and outputs a shadow enable signal EN to the second mode control unit 111b of the shadow circuit 10.

Taking row shadow elimination as an example, for the LED common cathode driving scheme, when row shadow elimination is performed, a point B (row tube pad) is pulled high, that is, the voltage at the point B is controlled to rise, the comparator C1 compares a port voltage signal at the point B with the preset voltage signal DEG _ VREF, wherein the DEG _ VREF can be adjusted by the shadow elimination configuration circuit 30, if the port voltage signal, that is, the voltage at the point B is higher than the preset voltage signal DEG _ VREF, the shadow elimination enable signal EN is low, the shadow elimination circuit 10 is in an off state, and shadow elimination is stopped. If the voltage of the point B, namely the port voltage signal is lower than the preset voltage signal DEG _ VREF, the shadow elimination enabling signal EN is high, and at the moment, the shadow elimination circuit is in an enabling state to continue to eliminate shadows; therefore, the comparator C1 of the shadow protection circuit 40 is matched with the DEG _ VREF which can be adjusted, so that line shadow can be automatically cut off.

For the column shadow elimination, the principle is similar, for the LED common cathode driving scheme, when the column shadow is eliminated, the a (channel pad) point is pulled low, that is, the voltage of the a point is controlled to decrease, the comparator C1 compares the voltage of the a point, that is, the port voltage signal, with the preset voltage signal DEG _ VREF, if the voltage of the a point, that is, the port voltage signal, is higher than the preset voltage signal DEG _ VREF, the shadow elimination enable signal EN is high, the shadow elimination circuit is in the enable state, and the shadow elimination can be continued; if the voltage of the point A is lower than the preset voltage signal DEG _ VREF, the shadow elimination enabling signal EN is low, at the moment, the shadow elimination circuit is in a closed state, and shadow elimination is stopped. Therefore, the comparator C1 of the shadow elimination protection circuit 40 is matched with the adjustable preset voltage signal DEG _ VREF, so that the column shadow elimination can be automatically disconnected.

Next, specific circuit configurations of the second vanishing control block 11b and the second vanishing executing block 13b in the vanishing circuit 10 shown in fig. 4 will be described with reference to fig. 7 and 8. Fig. 7 is a circuit configuration diagram of the image-erasing circuit 10 shown in fig. 4 for performing line image-erasing under the LED common cathode driving, and fig. 8 is a circuit configuration diagram of the image-erasing circuit 10 shown in fig. 4 for performing column image-erasing under the LED common anode driving.

As shown in fig. 7, the third shadow elimination execution unit 131b includes, for example: at least one switch element M1 and at least one switch element M1 are, for example, 3 switch elements M1, so that the shadow-eliminating adjustment of 8 gears can be realized, although the utility model is not limited to the specific number of switch elements M1, and can be set according to practical situations, for example, two switch elements M1 are provided, and the shadow-eliminating adjustment of 4 gears can be realized. Specifically, when the LED common cathode driving scheme performs the shadow elimination, as shown in fig. 7, the switching element M1 is an NMOS transistor, the control terminal is connected to the second mode control unit 111B, the output terminal is connected to the diode electrode terminal, i.e., the negative electrode terminal of LED11, which is referred to as point B, and the input terminal is connected to the power supply terminal for receiving VDD. When the LED common cathode driving scheme performs column dimming, as shown in fig. 8, the switching element M1 is a PMOS transistor, the control terminal is connected to the second mode control unit 111b, the output terminal is connected to the positive electrode terminal of the diode electrode terminal, such as LED11, which is referred to as point a, and the input terminal is connected to the ground terminal to receive VSS.

The fourth vanishing performing unit 133b includes, for example: at least one switch element M2, and at least one switch element M2 is, for example, 3 switch elements M2, so that the shadow elimination adjustment function of 8 shift positions can be realized, although the utility model is not limited to the specific number of switch elements M2, and can be set according to practical situations. Specifically, when the LED common cathode driving scheme performs the shadow elimination, as shown in fig. 7, the switching element M2 is, for example, a PMOS transistor, and has a control terminal connected to the second mode control unit 111B, an output terminal connected to the point B, and an input terminal connected to the power supply terminal. When the LED common cathode driving scheme performs column dimming, as shown in fig. 8, the switching element M2 is, for example, an NMOS transistor, and has a control terminal connected to the second mode control unit 111b, an output terminal connected to the point a, and an input terminal connected to the ground terminal.

The second mode control unit 111b includes, for example: a control selector BC1, a control selector BC2, a control selector BC3, a first and gate CY1 and a second and gate CY 2. The control selector BC1, the control selector BC2 and the control selector BC3 are all alternative selectors.

Specifically, the first input terminal of the first and gate CY1 is connected to the deghosting configuration circuit 30 to receive the first deghosting control signal ENN, the second input terminal is connected to the deghosting protection circuit 40, specifically, the output terminal of the comparator C1 to receive the deghosting enable signal EN, and the output terminal outputs the first deghosting configuration signal ENA.

The second and gate CY2 has a first input terminal connected to the degaussing configuration circuit 30 for receiving the second degaussing control signal ENP, a second input terminal connected to the degaussing protection circuit 40, specifically to the output terminal of the comparator C1 for receiving the degaussing enable signal EN, and an output terminal for outputting the second degaussing configuration signal ENB.

The control selector BC1 has a first input terminal connected to the second degaussing adjustment unit 113b, a selection terminal connected to the output terminal of the first and gate for receiving the first degaussing configuration signal ENA, and an output terminal connected to the control terminal of the switching element M1. It should be understood here that the number of control selectors BC1 is the same as the number of switch elements M1, for example, the number of switch elements M1 is three, then three control selectors BC1 are provided to be connected to the control terminals of switch elements M1, and fig. 7 is a simplified schematic diagram of three control selectors BC 1. When the control selector BC1 performs row blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the ground terminal to receive VSS; when the control selector BC1 performs column dimming in the LED common cathode driving scheme, as shown in fig. 8, the second input terminal is connected to the power source terminal to receive VDD. It is to be understood that when the row deghosting is performed in the LED common cathode driving scheme, the first signal source is the ground terminal and the first chip voltage signal is VSS, and when the column deghosting is performed in the LED common cathode driving scheme, the first signal source is the power terminal and the first chip voltage signal is VDD.

A first input terminal of the control selector BC2 is connected to the second vanishing adjusting unit 113b, a second input terminal is connected to the vanishing configuring circuit 30, and a selection terminal is connected to the vanishing configuring circuit 30 to receive the third vanishing control signal ENS. It should be noted that, if the number of the control selectors BC2 is the same as that of the switch elements M2, for example, if the number of the switch elements M2 is three, three control selectors BC2 are provided to receive three vanishing control signals SR <2:0>, respectively, and fig. 7 is a simplified illustration of three control selectors BC 2. When the control selector BC2 performs line-blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the blanking configuration circuit to receive the inverted blanking adjustment signal! SR <2:0 >; when the control selector BC2 performs column dimming in the LED common cathode driving scheme, as shown in FIG. 8, the second input terminal is connected to the dimming configuration circuit to receive the dimming control signal SR <2:0 >.

A first input terminal of the control selector BC3 is connected to the output terminal of the control selector BC2, a selection terminal is connected to the output terminal of the second and gate for receiving the second vanishing configuration signal ENB, and an output terminal is connected to a control terminal of the switching element M2. It should be understood here that the number of control selectors BC3 is the same as the number of switch elements M2, for example, the number of switch elements M2 is three, three control selectors BC3 are provided to be connected to the control terminals of the switch elements M2, and fig. 7 is a simplified schematic diagram of three control selectors BC 3. When the control selector BC3 performs row blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the power source terminal to receive VDD; when the control selector BC3 performs column dimming in the LED common cathode driving scheme, as shown in fig. 8, the second input terminal is connected to the ground terminal to receive VSS. It is to be understood herein that the second signal source is a power source terminal and the second chip voltage signal is VDD when the row blanking is performed in the LED common cathode driving scheme, and the second signal source is a ground terminal and the second chip voltage signal is VSS when the column blanking is performed in the LED common cathode driving scheme.

The second vanishing adjusting unit 113b includes, for example: at least one regulation selector BT1 and at least one regulation selector BT 2. In fig. 7 and 8, three adjusting selectors BT1 and three adjusting selectors BT2 are illustrated, but the present invention is not limited thereto, and the number of adjusting selectors BT1 may be set based on the number of switching elements M1, for example, the same as the number of switching elements M1, and the number of adjusting selectors BT2 may be set based on the number of switching elements M2, for example, the same as the number of switching elements M2. The adjustment selector BT1 and the adjustment selector BT2 are alternative selectors.

Specifically, the adjustment selector BT1 has a first input terminal connected to the deghosting configuration circuit 30 for receiving the reference voltage signal VB1_ REF, a selection terminal connected to the deghosting configuration circuit 30 for receiving the deghosting adjustment signal SR, and an output terminal connected to a first input terminal of the control selector BC 1. When the adjustment selector BT1 performs row blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the ground terminal to receive VSS; when the tuning selector BT1 performs column dimming in the LED common cathode driving scheme, as shown in fig. 8, the second input terminal is connected to the power source terminal to receive VDD.

The adjusting selector BT2 has a first input terminal connected to the constant current source generating circuit for receiving the bias voltage signal VBP, a selection terminal connected to the degaussing configuration circuit 30 for receiving the degaussing adjusting signal SR, and an output terminal connected to a first input terminal of the control selector BC 2. Wherein, when the adjustment selector BT2 performs line dimming in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the power supply terminal to receive VDD; when the adjustment selector BT2 performs column dimming in the LED common cathode driving scheme, as shown in fig. 8, the second input terminal is connected to ground to receive VSS.

The shadow elimination circuit 10 performs the shadow elimination function, and has three shadow elimination modes whether the row shadow elimination or the column shadow elimination is performed: the first and second image-eliminating modes are constant-current source image-eliminating modes and the third image-eliminating mode is super image-eliminating mode. When the shadow elimination circuit executes row shadow elimination in the LED common cathode driving scheme, the first shadow elimination mode is an NMOS shadow elimination mode, and when the shadow elimination circuit executes column shadow elimination in the LED common cathode driving scheme, the first shadow elimination mode is a PMOS shadow elimination mode. The switching of the three kinds of shading modes can be realized by a shading control signal.

The operation of the shadow circuit 10 shown in fig. 4 will be described with reference to fig. 7, taking the shadow circuit 10 as an example for performing line shadow in the LED common cathode driving scheme.

When the first and-gate CY1 outputs the first vanishing configuration signal ENA to "1" and the second and-gate CY2 outputs the second vanishing configuration signal ENB to "0" when the vanishing enable signal EN is "1", the first vanishing control signal ENN is "1" and the second vanishing control signal ENP is "0", and at this time, the control selector BC3 inputs VDD to the control terminal of the switching element M2 based on the second vanishing configuration signal ENB to "0", the switching element M2 is turned off, and the vanishing circuit 10 operates in the first vanishing mode, i.e., the NMOS vanishing mode.

In the first shading mode, the shading arrangement circuit 30 outputs shading adjustment signals SR <2:0> to the selection terminals of three adjustment selectors BT1, respectively, each adjustment selector BT1 selects an output based on the input shading adjustment signal, taking VB1<0> as an example, the adjustment selector BT1 outputs the reference voltage signal VB1_ REF as VB1<0> when SR <0> is 1, and the adjustment selector BT1 outputs the VSS signal as VB1<0> when SR <0> is 0. The control selector BC1 outputs the received VB1<2:0> as a shading execution signal V <2:0> to the control terminals of the three switching elements M1, respectively, and when the control terminal voltage of the switching element M1 is high, the switching element M1 is turned on, and a constant current of a certain magnitude, that is, a shading current for shading (charging a point B) is generated, and when the control terminal voltage of the switching element M1 is low, the switching element M1 is turned off, and the shading current corresponding to this switching element M1 is 0. The three switch elements M1 are controlled to be turned on or off by the shading adjustment signal SR <2:0>, so that the adjustment of the shading capability in the first shading mode is realized, and the turning on of the switch elements M1 with different numbers and different positions corresponds to different shading capabilities, that is, the shading circuit 10 shown in fig. 7 works in the first shading mode and has 8 kinds of shading capabilities.

When the degaussing enable signal EN is "1", the first degaussing control signal ENN is "0", and the second degaussing control signal ENP is "1", the first and gate CY1 outputs the first degaussing configuration signal ENA of "0", the second and gate CY2 outputs the second degaussing configuration signal ENB of "1", for example, the third degaussing control signal ENs is "0", the control selector BC1 outputs the signal VSS to the control terminal of the switching element M1 based on the first degaussing configuration signal ENA of "0", so that the switching element M1 is turned off, and the control selector BC2 outputs VB2<2:0> as the signal VC <2:0>, and the degaussing circuit 10 operates in the second degaussing mode.

In the second shading mode, the shading configuration circuit 30 outputs shading adjustment signals SR <2:0> to the control terminals of three adjustment selectors BT2, respectively, each adjustment selector BT2 selects an output based on the input shading adjustment signal, taking VB2<0> as an example, the adjustment selector BT2 outputs the bias voltage signal VBP from the constant current source generating circuit as VB2<0> when SR <0> is 1, and the adjustment selector BT2 outputs the VDD signal as VB2<0> when SR <0> is 0. The control selector BC2 inputs VB2<2:0> as VC <2:0> to the control selector BT3, the control selector BT3 outputs VC <2:0> as a subtraction execution signal V <2:0> to the control terminals of the three switching elements M2, respectively, and when the control terminal voltage of the switching element M2 is low, the switching element M2 is turned on to generate a constant current of a certain magnitude, that is, a shading current for shading (charging point B), and when the control terminal voltage of the switching element M2 is high, the switching element M2 is turned off, and the shading current corresponding to the switching element M2 is 0, thus, the three switching elements M2 are controlled to be opened or closed by the shading adjustment signals SR <2:0>, therefore, the adjustment of the shadow eliminating capability in the second shadow eliminating mode is realized, the conduction of the switch elements M2 with different numbers and different positions corresponds to different shadow eliminating capabilities, that is, the image-erasing circuit 10 shown in fig. 7 has 8 image-erasing capabilities when operating in the second image-erasing mode. It is worth mentioning that the second shadow elimination mode, namely the constant current source shadow elimination mode, is characterized in that the shadow elimination current can be adjusted, and constant current is provided under each gear, namely the shadow elimination current of all chips under the same gear is the same, so that good consistency is maintained, the overall shadow elimination speed is slow, and good EMI characteristics are provided.

When the erase enable signal EN is "1", the first erase control signal ENN is "0", and the second erase control signal ENP is "1", the first and gate CY1 outputs the first erase configuration signal ENA of "0", the second and gate CY2 outputs the second erase configuration signal ENB of "1", for example, the third erase control signal ENs is "1", the control selector BC1 outputs the signal VSS to the control terminal of the switching element M1 based on the first erase configuration signal ENA of "0", so that the switching element M1 is turned off, and the control selector BC2 turns the signal | off! SR <2:0> is output as the signal VC <2:0>, and the image erasing circuit 10 is operated in the third image erasing mode.

In the third erase mode, the erase configuration circuit 30 outputs the erase adjustment signal after the inversion process! SR <2:0> to three control selectors BC2, respectively, each control selector BC2 being "1" based on the third shadow control signal! SR <2:0> is output as a signal VC <2:0>, and taking VC <0> as an example, when SR <0> is 1, VC <0> is 0, and when SR <0> is 0, VC <0> is 1. The control selector BT3 outputs VC <2:0> as a shading execution signal V <2:0> to the control terminals of the three switching elements M2, respectively, when the control terminal voltage of the switching element M2 is low, the switching element M2 is turned on, a constant current, that is, a shading current of a certain magnitude is generated for shading (charging a point B), when the control terminal voltage of the switching element M2 is high, the switching element M2 is turned off, and the shading current corresponding to this switching element M2 is 0, whereby the on or off of the three switching elements M2 is controlled by a shading adjustment signal SR <2:0>, thereby realizing adjustment of the shading capability in the third shading mode. It should be noted that the third shadow elimination mode, i.e. the super shadow elimination mode, is characterized in that the size of the shadow elimination current can be adjusted, and since the gate voltage, i.e. the control terminal voltage, is directly 0 when the switching element M2 is turned on, the shadow elimination speed is very fast, and for the lamp panel with a relatively large row parasitic capacitance, the shadow elimination time can be greatly reduced, and the real display time is increased.

The operation principle of the shadow elimination circuit 10 shown in fig. 4 for performing column shadow elimination in the LED common cathode driving scheme is similar to that for performing row shadow elimination in the LED common cathode driving scheme, and the operation principle of the shadow elimination circuit 10 will be described below with reference to fig. 8 by taking the shadow elimination circuit 10 for performing column shadow elimination in the LED common cathode driving scheme as an example.

When the image-elimination enable signal EN is "1", the first image-elimination control signal ENN is "1", and the second image-elimination control signal ENP is "0", the first and gate CY1 outputs the first image-elimination configuration signal ENA of "1", the second and gate CY2 outputs the second image-elimination configuration signal ENB of "0", the control selector BC3 inputs VSS to the control terminal of the switching element M2 based on the second image-elimination configuration signal ENB of "0", the switching element M2 is turned off, and the image-elimination circuit 10 operates in the first image-elimination mode, that is, the PMOS image-elimination mode.

In the first shading mode, the shading configuration circuit 30 outputs shading adjustment signals SR <2:0> to the selection terminals of three adjustment selectors BT1, respectively, each adjustment selector BT1 selects an output based on the input shading adjustment signal, taking VB1<0> as an example, the adjustment selector BT1 outputs the reference voltage signal VB1_ REF as VB1<0> when SR <0> is 1, and the adjustment selector BT1 outputs the VDD signal as VB1<0> when SR <0> is 0. Wherein the reference voltage signal VB1_ REF can be adjusted by the deghosting configuration circuit 30. The control selector BC1 outputs the received VB1<2:0> as a shading execution signal V <2:0> to the control terminals of the three switching elements M1, respectively, and when the control terminal voltage of the switching element M1 is low, the switching element M1 is turned on, and a constant current of a certain magnitude, that is, a shading current for shading (discharging a point a) is generated, and when the control terminal voltage of the switching element M1 is high, the switching element M1 is turned off, and the shading current corresponding to this switching element M1 is 0. The on or off of the three switch elements M1 is controlled by the shading adjustment signal SR <2:0>, so as to adjust the shading capability in the first shading mode, and the on of the switch elements M1 with different numbers and different positions corresponds to different shading capabilities, that is, the shading circuit 10 shown in fig. 8 operates in the first shading mode and has 8 types of shading capabilities. The PMOS shadow eliminating mode can control the channel voltage (the source voltage of the PMOS is the lowest equal to the gate voltage) after the final PMOS shadow elimination is finished, and through the PMOS shadow eliminating mode, after the shadow elimination is finished, certain driving capability can be provided for the voltage of a channel pin (an LED anode), so that the output pin is prevented from being in a suspended state, and the coupling optimization is facilitated.

When the degaussing enable signal EN is "1", the first degaussing control signal ENN is "0", and the second degaussing control signal ENP is "1", the first and gate CY1 outputs the first degaussing configuration signal ENA of "0", the second and gate CY2 outputs the second degaussing configuration signal ENB of "1", for example, the third degaussing control signal ENs received at this time is "0", the control selector BC1 outputs the signal VDD to the control terminal of the switching element M1 based on the first degaussing configuration signal ENA of "0", so that the switching element M1 is turned off, and the control selector BC2 outputs VB2<2:0> as the signal VC <2:0>, and the degaussing circuit 10 operates in the second degaussing mode at this time.

In the second shading mode, the shading arrangement circuit 30 outputs shading adjustment signals SR <2:0> to the selection terminals of three adjustment selectors BT2, respectively, each adjustment selector BT2 selects an output based on the input shading adjustment signal, taking VB2<0> as an example, the adjustment selector BT2 outputs the bias voltage signal VBP from the constant current source generation circuit as VB2<0> when SR <0> is 1, and the adjustment selector BT2 outputs the VSS signal as VB2<0> when SR <0> is 0. It is worth mentioning that the magnitude of the current bias voltage signal VBP is different from that of the bias voltage signal of the shadow elimination circuit in the line shadow elimination performed by the LED common cathode driving scheme, and the current bias voltage signal VBP can be understood as "1", and then the bias voltage signal of the shadow elimination circuit when the line shadow elimination performed by the LED common cathode driving scheme can be understood as "0". Control selector BC2 inputs VB2<2:0> as VC <2:0> to control selector BT3, control selector BT3 outputs VC <2:0> as shading execution signals V <2:0> to the control terminals of three switching elements M2, respectively, and when the control terminal voltage of switching element M2 is high, the switching element M2 is turned on to generate a constant current of a certain magnitude, that is, a shading current for shading (discharging a point a), and when the control terminal voltage of the switching element M2 is low, the switching element M2 is turned off, and the shading current corresponding to the switching element M2 is 0, thus, the three switching elements M2 are controlled to be opened or closed by the shading adjustment signals SR <2:0>, thereby realizing the adjustment of the shadow eliminating capability in the second shadow eliminating mode, the conduction of the second switch elements M2 with different numbers and different positions corresponds to different shadow eliminating capabilities, that is, the image-erasing circuit 10 shown in fig. 6 has 8 image-erasing capabilities when operating in the second image-erasing mode. It is worth mentioning that the second shadow elimination mode, namely the constant current source shadow elimination mode, is characterized in that the shadow elimination current can be adjusted, and constant current is provided under each gear, namely the shadow elimination current of all chips under the same gear is the same, so that good consistency is maintained, the overall shadow elimination speed is slow, and good EMI characteristics are provided.

When the image-elimination enable signal EN is "1", the first image-elimination control signal ENN is "0", and the second image-elimination control signal ENP is "1", the first and gate CY1 outputs the first image-elimination configuration signal ENA of "0", the second and gate CY2 outputs the second image-elimination configuration signal ENB of "1", for example, the third image-elimination control signal ENs received at this time is "1", the control selector BC1 outputs the signal VDD to the control terminal of the switching element M1 based on the first image-elimination configuration signal ENA of "0", so that the switching element M1 is turned off, and the control selector BC2 outputs SR <2:0> as the signal VC <2:0>, and the image-elimination circuit 10 operates in the third image-elimination mode.

In the third subtraction mode, the subtraction configuration circuit 30 outputs the subtraction adjustment signals SR <2:0> to the three control selectors BC2, respectively, and the control selector BC2 outputs SR <2:0> as the signals VC <2:0> based on the third subtraction control signal being "1", for example, VC <0> being 1 when SR <0> being 1, and VC <0> being 0 when SR <0> being 0. The control selector BT3 outputs VC <2:0> as a shading execution signal V <2:0> to the control terminals of the three switching elements M2, respectively, and when the control terminal voltage of the switching element M2 is high, the switching element M2 is turned on, and generates a constant current of a certain magnitude, that is, a shading current for shading (discharging a point a), and when the control terminal voltage of the switching element M2 is low, the switching element M2 is turned off, and the shading current corresponding to this switching element M2 is 0, whereby the on or off of the three switching elements M2 is controlled by the shading adjustment signal SR <2:0>, and thereby the adjustment of the shading capability in the third shading mode is realized. It should be noted that the third shadow elimination mode, i.e. the super shadow elimination mode, is characterized in that the size of the shadow elimination current can be adjusted, and since the gate voltage, i.e. the control terminal voltage, is directly VDD when the switching element M2 is turned on, the shadow elimination speed is very fast, and for a lamp panel with a relatively large row parasitic capacitance, the shadow elimination time can be greatly reduced, and the real display time is increased.

In addition, the operation principle of the display driving chip shown in fig. 3 is basically the same as that of the display driving chip shown in fig. 4, and the display driving chip includes three identical shading modes, except that: since the display driving chip shown in fig. 3 does not include the shadow protection circuit, the shadow circuit 10 shown in fig. 3 does not need to receive the shadow enable signal EN, and thus the structure of the first mode control unit 111a is different from that of the second mode control unit 111 b. Fig. 9 is a circuit configuration diagram of the image-removing circuit 10 shown in fig. 3 for performing line image-removing under the LED common cathode driving scheme, and fig. 10 is a circuit configuration diagram of the image-removing circuit 10 shown in fig. 3 for performing the following image-removing under the LED common cathode driving scheme, and as shown in fig. 9 and 10, the first mode control unit 111a includes: the control selector BC1, the control selector BC2, and the control selector BC3 do not include the first and gate CY1 and the second and gate CY2 shown in fig. 7 and 8. The control selector BC1, the control selector BC2 and the control selector BC3 shown in fig. 9 and 10 are all alternative selectors, and are different from the control selector BC1, the control selector BC2 and the control selector BC3 shown in fig. 7 and 8 in that a selection terminal of the control selector BC1 shown in fig. 9 and 10 is connected to the vanishing configuring circuit 30 to receive the first vanishing control signal ENN, and a selection terminal of the control selector BC3 is connected to the vanishing configuring circuit 30 to receive the second vanishing control signal ENP.

It should be understood that, when the display driver chip does not include the shadow protection circuit 40, whether the shadow function is turned on may be controlled by the first shadow control signal ENN and the second shadow control signal ENP output by the shadow configuration circuit 30. The operation principle of the image elimination circuit shown in fig. 3 is the same as that of the image elimination circuit shown in fig. 4 for executing image elimination according to the first image elimination configuration signal ENA and the second image elimination configuration signal ENB, that is, the operation principle of the first image elimination control signal ENN and the second image elimination control signal ENP in the image elimination circuit shown in fig. 9 and 10 is equivalent to that of the first image elimination configuration signal ENA and the second image elimination configuration signal ENB in the image elimination circuit shown in fig. 7 and 8, and therefore, the specific operation process of the image elimination circuit shown in fig. 3, that is, the principle of the structures shown in fig. 9 and 10, can be referred to the related description of fig. 7 and 8, respectively, and will not be described again here.

In addition, the foregoing image elimination circuit 10 in the display driving chip 100 disclosed in the present embodiment is also applicable to performing image elimination under the LED common-anode driving scheme, which is basically the same as the foregoing principle of performing image elimination under the LED common-cathode driving scheme, except that: the downlink elimination of the LED common-anode driving scheme is to pull down the B point (LED anode) by the elimination circuit, that is, discharge the row parasitic capacitance to a low voltage through the pull-down tube, that is, control the voltage drop of the B point, so the schemes shown in fig. 8 and 10 are suitable for the row elimination under the LED common-anode driving scheme; the following shadow elimination in the LED common anode driving scheme is to require a shadow elimination circuit to pull up the point a (the LED cathode), i.e. to charge the row parasitic capacitance to a high voltage through the pull-down tube, i.e. to control the voltage rise at the point a, so the schemes shown in fig. 7 and 9 are suitable for the column shadow elimination in the LED common anode driving scheme. The specific operation process of the image erasing circuit 10 in the display driving chip 100 executing image erasing under the LED common-positive driving scheme is not described herein again. It should be noted that the specific setting of the height of the vanishing adjusting signal SR <2:0> in the foregoing example is to achieve the maximum vanishing capability of the vanishing circuit 10 when the SR <2:0> is all high, but the utility model is not limited thereto, and the height of the signal may be set according to actual requirements.

In summary, the display driving chip 100 disclosed in the foregoing embodiments of the utility model has the following advantages:

1. by arranging the shadow elimination configuration circuit 30 and the shadow elimination circuit 10 in the display driving chip 100, after the shadow elimination function is started, the shadow elimination circuit 10 determines to work in a target shadow elimination mode in a plurality of shadow elimination modes based on a shadow elimination control signal, namely, the shadow elimination circuit 10 can realize a plurality of shadow elimination modes, so that the condition that the conventional shadow elimination scheme is single and cannot be subjected to scheme adjustment aiming at an obstructed application requirement can be avoided, the shadow elimination circuit 10 determines the target shadow elimination mode in the plurality of shadow elimination modes based on the shadow elimination control signal, different application requirements can be met, a shadow phenomenon in the LED display process can be effectively removed, and the display effect is improved;

2. the shadow eliminating circuit 10 controls the voltage of the electrode end of the diode to rise or fall through setting the shadow eliminating adjusting signal, so that the adjustability of the shadow eliminating capability is realized, namely, a user can flexibly set the shadow eliminating adjusting signal according to the actual working condition of the display driving chip to adjust the shadow eliminating capability, and the problems that the EMI is generated due to the too fast shadow eliminating capability and the too slow shadow eliminating capability occupies too much display time are solved;

3. by arranging the shadow elimination protection circuit 40 in the shadow elimination circuit 10, the condition that the service life of the LED is influenced by the fact that the LED is in a reverse bias state for a long time in the shadow elimination of the existing shadow elimination scheme can be avoided, the shadow elimination function is automatically turned on or turned off, the service life of the LED is considered while shadow elimination is carried out, and the adaptability and the practicability are better;

4. the image elimination circuit 10 in the display driving chip 100 can perform an image elimination function under an LED common-cathode driving scheme and also can perform an image elimination function under an LED common-anode driving scheme, and further, the image elimination circuit 10 is not only suitable for line image elimination, but also suitable for column image elimination, and is wider in application range;

5. the display driving chip 100 can perform row and column shading simultaneously by providing a plurality of shading circuits 10, thereby further enhancing the shading effect and improving the display effect.

In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments can be arbitrarily combined and collocated without conflict between technical features and structures, and without departing from the purpose of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and/or method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units/modules is only one logical division, and there may be other divisions in actual implementation, for example, multiple units or modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units/modules described as separate parts may or may not be physically separate, and parts displayed as units/modules may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit/module in the embodiments of the present invention may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated unit/module may be implemented in the form of hardware, or may be implemented in the form of hardware plus a software functional unit/module.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A display driver chip, comprising:

a shadow eliminating configuration circuit;

the shadow eliminating circuit is electrically connected with the shadow eliminating configuration circuit;

the shadow eliminating configuration circuit outputs a shadow eliminating adjusting signal and a shadow eliminating control signal; after the shadow elimination function is started, the shadow elimination circuit determines to work in a target shadow elimination mode in a plurality of shadow elimination modes based on the shadow elimination control signal, and controls the voltage of the diode electrode end of the light-emitting diode to rise or fall based on the shadow elimination adjustment signal in the target shadow elimination mode.

2. The display driver chip of claim 1, further comprising:

the shadow eliminating protection circuit is electrically connected with the shadow eliminating circuit and the shadow eliminating configuration circuit; the shadow eliminating protection circuit acquires a port voltage signal of the diode electrode end and a preset voltage signal input by the shadow eliminating configuration circuit to generate a shadow eliminating enabling signal, and outputs the shadow eliminating enabling signal to the shadow eliminating circuit to control whether to start the shadow eliminating function.

3. The display driver chip of claim 1, wherein the degaussing circuit comprises:

the first shadow eliminating control module is electrically connected with the shadow eliminating configuration circuit;

the first shadow elimination execution module is electrically connected with the first shadow elimination control module;

wherein the plurality of vanishing modes include a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: a first, a second and a third shadow elimination control signals; the first shadow elimination control module receives the first shadow elimination control signal, the second shadow elimination control signal and the shadow elimination adjusting signal;

when the first and second vanishing control signals indicate that the vanishing function is started and the first vanishing control signal indicates that the first vanishing mode is the target vanishing mode, the first vanishing control module generates a vanishing execution signal based on a reference voltage signal, a first chip voltage signal and the vanishing adjustment signal, and the first vanishing execution module generates a vanishing current to the diode electrode terminal based on the vanishing execution signal; or

When the first and second vanishing control signals indicate that the vanishing function is turned on and the second and third vanishing control signals received by the first vanishing control module indicate that the second vanishing mode is the target vanishing mode, the first vanishing control module generates a vanishing execution signal based on a bias voltage signal, a second chip voltage signal and the vanishing adjustment signal, and the first vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or

When the first and second shadow elimination control signals represent that the shadow elimination function is started, and the second and third shadow elimination control signals received by the first shadow elimination control module represent that the third shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module generates a shadow elimination execution signal based on the shadow elimination adjustment signal, and the first shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal.

4. The display driver chip of claim 3, wherein the first shadow elimination control module comprises:

the first mode control unit is electrically connected with the first shadow elimination execution module and the shadow elimination configuration circuit; and

the first shadow eliminating adjusting unit is electrically connected with the first mode control unit and the shadow eliminating configuration circuit;

wherein the first mode control unit receives the first, second, and third shading control signals to determine the target shading mode,

when the first vanishing mode is the target vanishing mode, the first vanishing adjusting unit generates the vanishing executing signal based on the reference voltage signal, the first chip voltage signal and the vanishing adjusting signal and outputs the vanishing executing signal to the first vanishing executing module through the first mode control unit; or alternatively

When the second vanishing mode is the target vanishing mode, the first vanishing adjusting unit generates the vanishing executing signal based on the bias voltage signal, the second chip voltage signal and the vanishing adjusting signal and outputs the vanishing executing signal to the first vanishing executing module through the first mode control unit; or alternatively

When the third vanishing mode is the target vanishing mode, the first mode control unit generates the vanishing executing signal based on the vanishing adjusting signal and outputs the vanishing executing signal to the first vanishing executing module.

5. The display driver chip of claim 4, wherein the first mode control unit comprises:

the first control selector is connected with the first shadow elimination adjusting unit at a first input end, connected with a first signal source at a second input end, connected with the shadow elimination configuration circuit to receive the first shadow elimination control signal at a selection end, and connected with the first shadow elimination execution module at an output end;

a first input end of the second control selector is connected with the first vanishing adjusting unit, a second input end of the second control selector is connected with the vanishing configuration circuit, and a selection end of the second control selector is connected with the vanishing configuration circuit to receive the third vanishing control signal; and

and the first input end of the third control selector is connected with the output end of the second control selector, the second input end of the third control selector is connected with a second signal source, the selection end of the third control selector is connected with the shadow elimination configuration circuit to receive the second shadow elimination control signal, and the output end of the third control selector is connected with the first shadow elimination execution module.

6. The display driver chip of claim 2, wherein the degaussing circuit comprises:

the second shadow eliminating control module is electrically connected with the shadow eliminating configuration circuit and the shadow eliminating protection circuit;

the second shadow elimination execution module is electrically connected with the second shadow elimination control module;

wherein the plurality of vanishing modes include a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: a first, a second and a third shadow elimination control signals; the second shadow elimination control module receives the shadow elimination enabling signal, the first shadow elimination control signal, the second shadow elimination control signal and the shadow elimination adjusting signal, generates a first shadow elimination configuration signal based on the shadow elimination enabling signal and the first shadow elimination control signal and generates a second shadow elimination configuration signal based on the shadow elimination enabling signal and the second shadow elimination control signal;

when the first and second vanishing configuration signals represent that the vanishing function is turned on and the first vanishing configuration signal represents that the first vanishing mode is the target vanishing mode, the second vanishing control module generates a vanishing execution signal based on a reference voltage signal, a first chip voltage signal and the vanishing adjustment signal, and the second vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or

When the first and second vanishing configuration signals represent that the vanishing function is turned on, and the second vanishing configuration signal and the third vanishing control signal received by the second vanishing control module represent that the second vanishing mode is the target vanishing mode, the second vanishing control module generates a vanishing execution signal based on a bias voltage signal, a second chip voltage signal and the vanishing adjustment signal, and the second vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal; or

When the first and second vanishing configuration signals represent that the vanishing function is turned on, and the second and third vanishing control signals received by the second vanishing control module represent that the third vanishing mode is the target vanishing mode, the second vanishing control module generates a vanishing execution signal based on the vanishing adjustment signal, and the second vanishing execution module generates a vanishing current based on the vanishing execution signal and outputs the vanishing current to the diode electrode terminal.

7. The display driver chip of claim 6, wherein the second shadow control module comprises:

the second mode control unit is electrically connected with the second shadow elimination execution module, the shadow elimination configuration circuit and the shadow elimination protection circuit; and

the second shadow elimination adjusting unit is electrically connected with the second mode control unit and the shadow elimination configuration circuit;

wherein the second mode control unit receives the degaussing enable signal, the first degaussing control signal, the second degaussing control signal and the third degaussing control signal to determine the target degaussing mode,

when the first image elimination mode is the target image elimination mode, the second image elimination adjustment unit generates the image elimination execution signal based on the reference voltage signal, the first chip voltage signal and the image elimination adjustment signal and outputs the image elimination execution signal to the second image elimination execution module through the second mode control unit; or

When the second image-eliminating mode is the target image-eliminating mode, the second image-eliminating adjusting unit generates the image-eliminating executing signal based on the bias voltage signal, the second chip voltage signal and the image-eliminating adjusting signal and outputs the image-eliminating executing signal to the second image-eliminating executing module through the second mode control unit; or

When the third vanishing mode is the target vanishing mode, the second mode control unit generates the vanishing executing signal based on the vanishing adjusting signal and outputs the vanishing executing signal to the second vanishing executing module.

8. The display driver chip of claim 7, wherein the second mode control unit comprises:

the first input end of the first AND gate is connected with the shadow eliminating configuration circuit to receive the first shadow eliminating control signal, and the second input end of the first AND gate is connected with the shadow eliminating protection circuit to receive the shadow eliminating enable signal;

a fourth control selector, a first input end of which is connected with the second vanishing adjusting unit, a second input end of which is connected with the first signal source, a selection end of which is connected with the output end of the first and gate to receive the first vanishing configuration signal, and an output end of which is connected with the second vanishing executing module;

a fifth control selector, a first input end of which is connected with the second vanishing adjusting unit, a second input end of which is connected with the vanishing configuration circuit, and a selection end of which is connected with the vanishing configuration circuit to receive the third vanishing control signal;

the first input end of the second AND gate is connected with the shadow eliminating configuration circuit to receive the second shadow eliminating control signal, and the second input end of the second AND gate is connected with the shadow eliminating protection circuit to receive the shadow eliminating enabling signal;

and a sixth control selector, wherein the first input end of the sixth control selector is connected with the output end of the fifth control selector, the second input end of the sixth control selector is connected with the second signal source, the selection end of the sixth control selector is connected with the output end of the second and gate to receive the second vanishing configuration signal, and the output end of the sixth control selector is connected with the second vanishing executing module.

9. The display driver chip of claim 3, wherein the first shadow-elimination performing module comprises:

the first shadow elimination execution unit is connected with the first shadow elimination control module;

the second shadow elimination execution unit is connected with the first shadow elimination control module;

the first shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal in the first shadow elimination mode and outputs the shadow elimination current to the diode electrode terminal; or the second shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal in the second shadow elimination mode or the third shadow elimination mode.

10. The display driver chip of claim 6, wherein the second shading execution module comprises:

the third shadow elimination execution unit is connected with the second shadow elimination control module;

the fourth shadow elimination execution unit is connected with the second shadow elimination control module;

the third shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal in the first shadow elimination mode and outputs the shadow elimination current to the diode electrode terminal; or the fourth shadow elimination execution unit generates the shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal in the second shadow elimination mode or the third shadow elimination mode.

11. The display driver chip of claim 2, wherein the degaussing protection circuit comprises:

and the voltage comparison unit is electrically connected with the shadow eliminating configuration circuit and the diode electrode end and generates the shadow eliminating enabling signal based on the port voltage signal and the preset voltage signal.

12. The utility model provides a LED lamp plate, its characterized in that includes:

a display unit array including a plurality of display units, each of the display units including a plurality of light emitting diodes; and

the display driver chip of any one of claims 1-11, wherein said shadow elimination circuit of said display driver chip is connected to said diode electrode terminal of said light emitting diode.