CN116189602A - Display driving chip and LED lamp panel - Google Patents

Display driving chip and LED lamp panel Download PDF

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Publication number
CN116189602A
CN116189602A CN202111423926.8A CN202111423926A CN116189602A CN 116189602 A CN116189602 A CN 116189602A CN 202111423926 A CN202111423926 A CN 202111423926A CN 116189602 A CN116189602 A CN 116189602A
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China
Prior art keywords
deghosting
shadow
signal
control
mode
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CN202111423926.8A
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Chinese (zh)
Inventor
李晓
王伙荣
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Xi'an Ti Pt Sr Electronic Technology Co ltd
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Xi'an Ti Pt Sr Electronic Technology Co ltd
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Priority to CN202111423926.8A priority Critical patent/CN116189602A/en
Publication of CN116189602A publication Critical patent/CN116189602A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The embodiment of the invention discloses a display driving chip and an LED lamp panel. The display driving chip includes: a shadow elimination configuration circuit; the shadow eliminating circuit is electrically connected with the shadow eliminating configuration circuit; the shadow eliminating configuration circuit outputs a shadow eliminating adjusting signal and a shadow eliminating control signal; after the shadow eliminating circuit starts the shadow eliminating function, the shadow eliminating circuit determines to work in a target shadow eliminating mode in a plurality of shadow eliminating modes based on the shadow eliminating control signals, and controls the voltage of the diode electrode terminal of the light emitting diode to rise or fall based on the shadow eliminating adjusting signals in the target shadow eliminating mode. The display driving chip disclosed by the embodiment of the invention provides a plurality of shadow eliminating modes and has adjustable shadow eliminating capability.

Description

Display driving chip and LED lamp panel
Technical Field
The invention relates to the technical field of display control, in particular to a display driving chip and an LED lamp panel.
Background
Current LED driving schemes control the switching of the corresponding LEDs by controlling the voltages of the positive and negative electrodes of the LED lamps in the LED array, and control the brightness of the LEDs by controlling the magnitude of the current flowing through the LEDs and the time of turning on. The parasitic capacitance is generated by the PCB wiring of the lamp panel, and is charged in the display process of the LED lamp panel, so that corresponding charges are stored on the two polar plates of the LED lamp panel and cannot disappear along with power failure, namely, the parasitic capacitance can continuously maintain the voltage before the power failure, and the parasitic capacitance can cause the LED to generate ghosts, namely, the LED which is not lighted still emits light, so that the display effect is seriously influenced.
In order to solve the above problems, the positive and negative voltages of the LED lamp are processed by using the shadow elimination technology at present, however, although the related shadow elimination technology can eliminate the ghost, the shadow elimination scheme is single, the shadow elimination scheme cannot be adjusted according to different application requirements, and the shadow elimination capability cannot be adjusted.
Therefore, providing a shadow eliminating scheme with adjustable shadow eliminating capability is a problem to be solved in the prior art.
Disclosure of Invention
In order to solve the defects and shortcomings in the prior art, the embodiment of the invention provides a display driving chip and an LED lamp panel.
In one aspect, an embodiment of the present invention provides a display driving chip, including: a shadow elimination configuration circuit; the shadow eliminating circuit is electrically connected with the shadow eliminating configuration circuit; the shadow eliminating configuration circuit outputs a shadow eliminating adjusting signal and a shadow eliminating control signal; after the shadow eliminating circuit starts the shadow eliminating function, the shadow eliminating circuit determines to work in a target shadow eliminating mode in a plurality of shadow eliminating modes based on the shadow eliminating control signals, and controls the voltage of the diode electrode terminal of the light emitting diode to rise or fall based on the shadow eliminating adjusting signals in the target shadow eliminating mode.
By arranging the shadow eliminating configuration circuit and the shadow eliminating circuit in the display driving chip, after the shadow eliminating circuit starts the shadow eliminating function, the shadow eliminating circuit determines to work in a target shadow eliminating mode in a plurality of shadow eliminating modes based on the shadow eliminating control signals, namely the shadow eliminating circuit can realize a plurality of shadow eliminating modes, so that the condition that the existing shadow eliminating scheme is single and cannot be adjusted according to the application requirements of the failure can be avoided, and the shadow eliminating circuit disclosed by the invention can determine the target shadow eliminating mode in the plurality of shadow eliminating modes based on the shadow eliminating control signals, thereby meeting different application requirements; in addition, the shadow eliminating circuit disclosed by the invention can realize row shadow eliminating and column shadow eliminating by setting the shadow eliminating adjusting signals to control the voltage of the electrode terminal of the diode to rise or fall based on the shadow eliminating adjusting signals, and in addition, the shadow eliminating capability is adjustable by setting the shadow eliminating adjusting signals, namely, a user can flexibly set the shadow eliminating adjusting signals according to the actual working condition of the display driving chip to adjust the shadow eliminating capability, thereby solving the problems that the shadow eliminating capability is too fast to generate EMI and the shadow eliminating capability is too slow to occupy too much display time, and the shadow eliminating circuit can effectively remove the ghost phenomenon in the LED display process and improve the display effect.
In one embodiment of the present invention, the display driving chip further includes: a blanking protection circuit electrically connected to the blanking circuit and the blanking configuration circuit; the blanking protection circuit acquires a port voltage signal of the diode electrode terminal and a preset voltage signal input by the deghosting configuration circuit to generate a deghosting enabling signal, and outputs the deghosting enabling signal to the deghosting circuit to control whether to start the deghosting function.
Through setting up the shadow protection circuit that disappears in display driver chip, can avoid current shadow scheme that disappears when carrying out the shadow with LED be in the condition that the state influences the LED life-span of reverse bias for a long time, realized the automatic opening or closing of shadow function that disappears, adaptability and practicality are better.
In one embodiment of the present invention, the shadow elimination circuit includes: the first shadow elimination control module is electrically connected with the shadow elimination configuration circuit; the first shadow eliminating execution module is electrically connected with the first shadow eliminating control module; wherein, the plurality of vanishing modes includes a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: the first, second and third vanishing control signals; the first shadow elimination control module receives the first shadow elimination control signal, the second shadow elimination control signal and the shadow elimination adjusting signal; when the first shadow elimination control signal and the second shadow elimination control signal represent that the shadow elimination function is started and the first shadow elimination control signal represents that the first shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module generates a shadow elimination execution signal based on a reference voltage signal, a first chip voltage signal and the shadow elimination adjustment signal, and the first shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal; or when the first and second deghosting control signals represent that the deghosting function is started, and the second deghosting control signal and the third deghosting control signal received by the first deghosting control module represent that the second deghosting mode is the target deghosting mode, the first deghosting control module generates a deghosting execution signal based on a bias voltage signal, a second chip voltage signal and the deghosting adjustment signal, and the first deghosting execution module generates a deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal; or when the first shadow elimination control signal and the second shadow elimination control signal represent that the shadow elimination function is started, and the second shadow elimination control signal and the third shadow elimination control signal received by the first shadow elimination control module represent that the third shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module generates a shadow elimination execution signal based on the shadow elimination adjustment signal, and the first shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the electrode end of the diode.
In one embodiment of the present invention, the first shadow control module includes: the first mode control unit is electrically connected with the first shadow elimination execution module and the shadow elimination configuration circuit; the first shadow eliminating adjusting unit is electrically connected with the first mode control unit and the shadow eliminating configuration circuit; the first mode control unit receives the first shadow elimination control signal, the second shadow elimination control signal and the third shadow elimination control signal to determine the target shadow elimination mode, wherein when the first shadow elimination mode is the target shadow elimination mode, the first shadow elimination adjusting unit generates the shadow elimination execution signal based on the reference voltage signal, the first chip voltage signal and the shadow elimination adjusting signal, and outputs the shadow elimination execution signal to the first shadow elimination execution module through the first mode control unit; or when the second deghosting mode is the target deghosting mode, the first deghosting adjusting unit generates the deghosting execution signal based on the bias voltage signal, the second chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the first deghosting execution module through the first mode control unit; or when the third vanishing mode is the target vanishing mode, the first mode control unit generates the vanishing execution signal based on the vanishing adjustment signal and outputs the vanishing execution signal to the first vanishing execution module.
In one embodiment of the present invention, the first mode control unit includes: the first control selector is provided with a first input end connected with the first shadow eliminating adjusting unit, a second input end connected with a first signal source, a selection end connected with the shadow eliminating configuration circuit to receive the first shadow eliminating control signal, and an output end connected with the first shadow eliminating execution module; the first input end of the second control selector is connected with the first shadow eliminating adjusting unit, the second input end of the second control selector is connected with the shadow eliminating configuration circuit, and the selection end of the second control selector is connected with the shadow eliminating configuration circuit to receive the third shadow eliminating control signal; and the first input end of the third control selector is connected with the output end of the second control selector, the second input end of the third control selector is connected with a second signal source, the selection end of the third control selector is connected with the shadow elimination configuration circuit to receive the second shadow elimination control signal, and the output end of the third control selector is connected with the first shadow elimination execution module.
In one embodiment of the present invention, the shadow elimination circuit includes: the second shadow eliminating control module is electrically connected with the shadow eliminating configuration circuit and the shadow eliminating protection circuit; the second shadow eliminating execution module is electrically connected with the second shadow eliminating control module; wherein, the plurality of vanishing modes includes a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: the first, second and third vanishing control signals; the second deghosting control module receives the deghosting enable signal, the first deghosting control signal, the second deghosting control signal and the deghosting adjustment signal, generates a first deghosting configuration signal based on the deghosting enable signal and the first deghosting control signal, and generates a second deghosting configuration signal based on the deghosting enable signal and the second deghosting control signal; when the first and second shadow elimination configuration signals represent that the shadow elimination function is started and the first shadow elimination configuration signal represents that the first shadow elimination mode is the target shadow elimination mode, the second shadow elimination control module generates a shadow elimination execution signal based on a reference voltage signal, a first chip voltage signal and the shadow elimination adjustment signal, and the second shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal; or when the first and second shadow eliminating configuration signals represent that the shadow eliminating function is started and the second shadow eliminating configuration signals and the third shadow eliminating control signals received by the second shadow eliminating control module represent that the second shadow eliminating mode is the target shadow eliminating mode, the second shadow eliminating control module generates a shadow eliminating executing signal based on a bias voltage signal, a second chip voltage signal and the shadow eliminating adjusting signal, and the second shadow eliminating executing module generates a shadow eliminating current based on the shadow eliminating executing signal and outputs the shadow eliminating current to the diode electrode terminal; or when the first shadow elimination configuration signal and the second shadow elimination configuration signal represent that the shadow elimination function is started, and the second shadow elimination configuration signal and the third shadow elimination control signal received by the second shadow elimination control module represent that the third shadow elimination mode is the target shadow elimination mode, the second shadow elimination control module generates a shadow elimination execution signal based on the shadow elimination adjustment signal, and the second shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the electrode terminal of the diode.
In one embodiment of the present invention, the second shadow elimination control module includes: the second mode control unit is electrically connected with the second shadow elimination execution module, the shadow elimination configuration circuit and the shadow elimination protection circuit; and a second deghosting adjusting unit electrically connected with the second mode control unit and the deghosting configuration circuit; the second mode control unit receives the deghosting enabling signal, the first deghosting control signal, the second deghosting control signal and the third deghosting control signal to determine the target deghosting mode, wherein when the first deghosting mode is the target deghosting mode, the second deghosting adjusting unit generates the deghosting executing signal based on the reference voltage signal, the first chip voltage signal and the deghosting adjusting signal, and outputs the deghosting executing signal to the second deghosting executing module through the second mode control unit; or when the second deghosting mode is the target deghosting mode, the second deghosting adjusting unit generates the deghosting execution signal based on the bias voltage signal, the second chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the second deghosting execution module through the second mode control unit; or when the third vanishing mode is the target vanishing mode, the second mode control unit generates the vanishing execution signal based on the vanishing adjustment signal and outputs the vanishing execution signal to the second vanishing execution module.
In one embodiment of the present invention, the second mode control unit includes: the first input end of the first AND gate is connected with the deghosting configuration circuit to receive the first deghosting control signal, and the second input end of the first AND gate is connected with the deghosting protection circuit to receive the deghosting enabling signal; a fourth control selector, wherein a first input end is connected with the second shadow eliminating adjusting unit, a second input end is connected with a first signal source, a selection end is connected with an output end of the first AND gate to receive the first shadow eliminating configuration signal, and an output end is connected with the second shadow eliminating executing module; a fifth control selector, the first input end of which is connected with the second shadow eliminating adjusting unit, the second input end of which is connected with the shadow eliminating configuration circuit, and the selection end of which is connected with the shadow eliminating configuration circuit to receive the third shadow eliminating control signal; the first input end of the second AND gate is connected with the deghosting configuration circuit to receive the second deghosting control signal, and the second input end of the second AND gate is connected with the deghosting protection circuit to receive the deghosting enabling signal; and the sixth control selector is provided with a first input end connected with the output end of the fifth control selector, a second input end connected with a second signal source, a selection end connected with the output end of the second AND gate so as to receive the second shadow eliminating configuration signal, and an output end connected with the second shadow eliminating execution module.
In one embodiment of the present invention, the first shadow adjustment unit includes: the first adjusting selector is characterized in that a first input end is connected with the shadow eliminating configuration circuit, a second input end is connected with a first signal source, a selecting end is connected with the shadow eliminating configuration circuit, and an output end is connected with the first mode control unit; and the second adjusting selector is characterized in that the first input end is connected with the constant current source generating circuit, the second input end is connected with the second signal source, the selecting end is connected with the shadow eliminating configuration circuit, and the output end is connected with the first mode control unit.
In one embodiment of the present invention, the first shadow elimination execution module includes: the first shadow eliminating execution unit is connected with the first shadow eliminating control module; the second shadow eliminating execution unit is connected with the first shadow eliminating control module, wherein the first shadow eliminating execution unit generates the shadow eliminating current based on the shadow eliminating execution signal in the first shadow eliminating mode and outputs the shadow eliminating current to the electrode end of the diode; or the second deghosting execution unit generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the second deghosting mode or the third deghosting mode.
In one embodiment of the present invention, the second shadow elimination execution module includes: the third shadow eliminating execution unit is connected with the second shadow eliminating control module; the fourth shadow eliminating execution unit is connected with the second shadow eliminating control module, wherein the third shadow eliminating execution unit generates the shadow eliminating current based on the shadow eliminating execution signal in the first shadow eliminating mode and outputs the shadow eliminating current to the electrode end of the diode; or the fourth deghosting execution unit generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the second deghosting mode or the third deghosting mode.
In one embodiment of the present invention, the second shadow adjustment unit includes: the first input end of the third adjusting selector is connected with the shadow eliminating configuration circuit, the second input end of the third adjusting selector is connected with the first signal source, the selecting end of the third adjusting selector is connected with the shadow eliminating configuration circuit, and the output end of the third adjusting selector is connected with the second mode control unit; and a fourth adjusting selector, wherein the first input end is connected with the constant current source generating circuit, the second input end is connected with the second signal source, the selecting end is connected with the shadow eliminating configuration circuit, and the output end is connected with the second mode control unit.
In one embodiment of the present invention, the first shadow elimination execution unit includes: the control end of the first switching element is connected with the first shadow elimination control module, the output end of the first switching element is connected with the electrode end of the diode, and the input end of the first switching element is connected with the second signal source; and the second shadow elimination execution unit includes: and the control end of the second switching element is connected with the first shadow elimination control module, the output end of the second switching element is connected with the electrode end of the diode, and the input end of the second switching element is connected with the second signal source.
In one embodiment of the present invention, the third shadow elimination execution unit includes: the control end of the third switching element is connected with the second shadow elimination control module, the output end of the third switching element is connected with the electrode end of the diode, and the input end of the third switching element is connected with the second signal source; and the fourth shadow elimination execution unit includes: and the control end of the fourth switching element is connected with the second shadow elimination control module, the output end of the fourth switching element is connected with the electrode end of the diode, and the input end of the fourth switching element is connected with the second signal source.
In one embodiment of the present invention, the shadow elimination protection circuit includes: and the voltage comparison unit is electrically connected with the shadow elimination configuration circuit and the diode electrode terminal and generates the shadow elimination enabling signal based on the port voltage signal and the preset voltage signal.
In another aspect, an embodiment of the present invention provides an LED lamp panel, including: a display unit array including a plurality of display units, each of the display units including a plurality of light emitting diodes; and any one of the display driving chips, wherein the shadow eliminating circuit of the display driving chip is connected with the diode electrode terminal of the light emitting diode.
The above technical solution may have the following advantages or benefits: by arranging the shadow eliminating configuration circuit and the shadow eliminating circuit in the display driving chip, after the shadow eliminating circuit starts the shadow eliminating function, the shadow eliminating circuit determines to work in a target shadow eliminating mode in a plurality of shadow eliminating modes based on the shadow eliminating control signals, namely the shadow eliminating circuit can realize a plurality of shadow eliminating modes, so that the condition that the existing shadow eliminating scheme is single and cannot be adjusted according to the application requirements of the failure can be avoided, and the shadow eliminating circuit disclosed by the invention can determine the target shadow eliminating mode in the plurality of shadow eliminating modes based on the shadow eliminating control signals, thereby meeting different application requirements; in addition, the shadow eliminating circuit disclosed by the invention can realize row shadow eliminating and column shadow eliminating by setting the shadow eliminating adjusting signals to control the voltage of the electrode terminal of the diode to rise or fall, and in addition, the shadow eliminating capability is adjustable by setting the shadow eliminating adjusting signals, namely, a user can flexibly set the shadow eliminating adjusting signals according to the actual working condition of the display driving chip to adjust the shadow eliminating capability, thereby solving the problems that the shadow eliminating capability is too fast to generate EMI and the shadow eliminating capability is too slow to occupy too much display time, and the shadow eliminating circuit can effectively remove the ghost phenomenon in the LED display process and improve the display effect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display driving chip according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of another structure of a display driving chip according to an embodiment of the invention.
Fig. 3 is a schematic diagram showing a specific structure of the driving chip shown in fig. 1.
Fig. 4 is a schematic diagram showing a specific structure of the driving chip shown in fig. 2.
Fig. 5 is a schematic circuit diagram of a portion of a structure of an LED lamp panel according to an embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of a portion of a structure of an LED lamp panel according to an embodiment of the present invention.
Fig. 7 is a schematic circuit diagram showing a circuit configuration of the shadow elimination circuit in the driving chip shown in fig. 4 applied to perform row shadow elimination under the LED common cathode driving scheme.
Fig. 8 is a schematic diagram of a circuit structure of the circuit for performing column subtraction in the LED common cathode driving scheme in the driving chip shown in fig. 4.
Fig. 9 is a schematic circuit diagram of a circuit configuration of the display driver chip shown in fig. 3 for performing line blanking under the LED common cathode driving scheme.
Fig. 10 is a schematic diagram of a circuit structure of the circuit for performing column subtraction in the LED common cathode driving scheme in the display driving chip shown in fig. 3.
Description of main reference numerals:
100: a display driving chip; 10: a shadow eliminating circuit; 30: a shadow elimination configuration circuit; 11a: a first shadow elimination control module; 11b: the second shadow elimination control module; 13a: a first shadow elimination execution module; 13b: a second shadow elimination execution module; 111a: a first mode control unit; 111b: a second mode control unit; 113a: a first shadow eliminating adjusting unit; 113b: a second shadow eliminating adjusting unit; 131a: a first shadow elimination execution unit; 133a: a second shadow elimination execution unit; 131b: a third shadow elimination execution unit; 133b: a fourth shadow elimination execution unit; 40: a shadow elimination protection circuit; 41: and a voltage comparing unit.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, one embodiment of the present invention discloses a display driving chip 100, for example, including: a deghosting circuit 10 and a deghosting configuration circuit 30.
Wherein the deghosting configuration circuit 30 outputs a deghosting adjustment signal and a deghosting control signal. After the image cancellation circuit 10 starts the image cancellation function, it determines to operate in a target image cancellation mode in a plurality of image cancellation modes based on the image cancellation control signal, and controls the voltage of the diode electrode terminal of the light emitting diode to rise or fall based on the image cancellation adjustment signal in the target image cancellation mode.
The light emitting diodes are, for example, LEDs, and the diode electrode terminals may be understood that the display driving chip 100 disclosed in this embodiment is used to connect the display unit arrays to form an LED lamp panel, each display unit array includes a plurality of display units, each display unit includes a plurality of light emitting diodes, for example, three light emitting diodes corresponding to red light emitting diodes, green light emitting diodes, and blue light emitting diodes, respectively, each light emitting diode has two diode electrode terminals, that is, a positive electrode terminal and a negative electrode terminal, and the shadow eliminating circuit 10 of the display driving chip 100 disclosed in this embodiment may be connected to the positive electrode terminal or the negative electrode terminal of the light emitting diode. In addition, one display driving chip 100 may be provided with a plurality of the image canceling circuits 10, and the present embodiment does not limit the number of the image canceling circuits 10 of a single display driving chip 100, and the positive electrode terminal and the negative electrode terminal of each light emitting diode are connected to the image canceling circuits 10, for example.
The shadow eliminating configuration circuit 30 may be understood as a digital logic circuit in the conventional display driving chip, for example, including a plurality of registers, each of which correspondingly outputs a signal, or for example, including a controller, and directly outputs a plurality of signals, and the specific structure of the shadow eliminating configuration circuit 30 is not described herein.
In one embodiment of the present invention, as shown in fig. 3, the shadow elimination circuit 10 includes, for example: a first deghosting control module 11a and a first deghosting execution module 13a. The first shadow eliminating control module 11a is electrically connected to the shadow eliminating configuration circuit 30, and the first shadow eliminating execution module 13a is electrically connected to the first shadow eliminating control module 11a.
For example, the deghosting circuit 10 has a plurality of deghosting modes, and includes, for example, a first deghosting mode, a second deghosting mode, and a third deghosting mode, the deghosting control signals include, for example: the first, second and third vanishing control signals.
Wherein the first deghosting control module 11a receives the first deghosting control signal, the second deghosting control signal and the deghosting adjustment signal;
when the first and second deghosting control signals represent that the deghosting function is turned on and the first deghosting control signal represents that the first deghosting mode is the target deghosting mode, the first deghosting control module 11a generates a deghosting execution signal based on a reference voltage signal, a first chip voltage signal and the deghosting adjustment signal, and the first deghosting execution module 13a generates a deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal; or alternatively
When the first and second deghosting control signals represent that the deghosting function is turned on and the second deghosting control signal and the third deghosting control signal received by the first deghosting control module 11a represent that the second deghosting mode is the target deghosting mode, the first deghosting control module 11a generates a deghosting execution signal based on a bias voltage signal, a second chip voltage signal and the deghosting adjustment signal, and the first deghosting execution module 13a generates a deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal; or alternatively
When the first and second shadow elimination control signals represent that the shadow elimination function is turned on, and the second shadow elimination control signal and the third shadow elimination control signal received by the first shadow elimination control module 11a represent that the third shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module 11a generates a shadow elimination execution signal based on the shadow elimination adjustment signal, and the first shadow elimination execution module 13a generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal.
In one embodiment of the present invention, referring to fig. 3, the first shadow control module 11a includes, for example: a first mode control unit 111a and a first ghost adjustment unit 113a. Wherein the first mode control unit 111a is electrically connected to the first deghosting execution module 13a and the deghosting configuration circuit 30. The first deghosting unit 113a is electrically connected to the first mode control unit 111a and the deghosting configuration circuit 30.
In one embodiment of the present invention, referring to fig. 3, the first shadow elimination execution module 13a includes, for example: the first and second shadow elimination execution units 131a and 133a. The first vanishing execution unit 131a is connected to the first vanishing control module 11a. The second vanishing execution unit 133a is connected to the first vanishing control module 11a.
Specifically, as shown in fig. 1, the first mode control unit 111a is electrically connected to the first subtraction execution unit 131a, the second subtraction execution unit 133a, the first subtraction adjustment unit 113a, and the subtraction configuration circuit 30.
Wherein the first mode control unit 111a receives the first, second and third vanishing control signals to determine the target vanishing mode;
when the first deghosting mode is the target deghosting mode, the first deghosting adjusting unit 113a generates the deghosting execution signal based on the reference voltage signal, the first chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the first deghosting executing module 13a, for example, to the first deghosting executing unit 131a via the first mode control unit 111a, so that it generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the first deghosting mode; or alternatively
When the second deghosting mode is the target deghosting mode, the first deghosting adjusting unit 113a generates the deghosting execution signal based on the bias voltage signal, the second chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the first deghosting executing module 13a, for example, to a second deghosting executing unit 133a via the first mode control unit 111a, so that it generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the second deghosting mode; or alternatively
When the third deghosting mode is the target deghosting mode, the first mode control unit 111a generates the deghosting execution signal based on the deghosting adjustment signal and outputs the deghosting execution signal to the first deghosting execution module 13a, for example, to the second deghosting execution unit 133a, so that it generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the third deghosting mode.
Specifically, the first mode control unit 111a includes, for example: a first control selector, a second control selector, and a third control selector. The first control selector is characterized in that a first input end is connected with the first shadow eliminating adjusting unit, a second input end is connected with a first signal source, a selection end is connected with the shadow eliminating configuration circuit to receive the first shadow eliminating control signal, and an output end is connected with the first shadow eliminating executing module. And the first input end of the second control selector is connected with the first shadow elimination regulating unit, the second input end of the second control selector is connected with the shadow elimination configuration circuit, and the selection end of the second control selector is connected with the shadow elimination configuration circuit so as to receive the third shadow elimination control signal. And the first input end of the third control selector is connected with the output end of the second control selector, the second input end of the third control selector is connected with a second signal source, the selection end of the third control selector is connected with the shadow elimination configuration circuit to receive the second shadow elimination control signal, and the output end of the third control selector is connected with the first shadow elimination execution module.
Specifically, the first ghost adjustment unit 113a includes, for example: a first tuning selector and a second tuning selector. The first adjusting selector is characterized in that a first input end of the first adjusting selector is connected with the shadow eliminating configuration circuit, a second input end of the first adjusting selector is connected with a first signal source, a selection end of the first adjusting selector is connected with the shadow eliminating configuration circuit, and an output end of the first adjusting selector is connected with the first mode control unit. And the first input end of the second adjusting selector is connected with the constant current source generating circuit, the second input end of the second adjusting selector is connected with the second signal source, the selecting end of the second adjusting selector is connected with the shadow eliminating configuration circuit, and the output end of the second adjusting selector is connected with the first mode control unit.
Specifically, the first shadow elimination execution unit 131a includes, for example: and the control end of the first switching element is connected with the first shadow elimination control module, the output end of the first switching element is connected with the electrode end of the diode, and the input end of the first switching element is connected with the second signal source. The second subtraction execution unit 133a includes, for example: and the control end of the second switching element is connected with the first shadow elimination control module, the output end of the second switching element is connected with the electrode end of the diode, and the input end of the second switching element is connected with the second signal source.
In another embodiment of the present invention, as shown in fig. 2, the display driving chip 100 further includes, for example: the shadow elimination protection circuit 40. The blanking protection circuit 40 is electrically connected to the blanking circuit 10 and the blanking configuration circuit 30, and the blanking protection circuit 40 obtains a port voltage signal of the diode electrode terminal and a preset voltage signal input by the blanking configuration circuit 30 to generate a blanking enable signal, and outputs the blanking enable signal to the blanking circuit 10 to control whether to turn on the blanking function.
In another embodiment of the present invention, as shown in fig. 4, the shadow elimination circuit 10 shown in fig. 2 includes, for example: a second deghosting control module 11b and a second deghosting execution module 13b.
Specifically, the second deghosting control module 11b electrically connects the deghosting configuration circuit 30 and the deghosting protection circuit 40. The second shadow elimination execution module 13b is electrically connected to the second shadow elimination control module 11b.
The deghosting circuit 10 has a plurality of deghosting modes, and includes: a first vanishing mode, a second vanishing mode and a third vanishing mode; the shadow elimination control signal comprises: the first, second and third vanishing control signals. The second deghosting control module 11b receives the deghosting enable signal, the first deghosting control signal, the second deghosting control signal and the deghosting adjustment signal, generates a first deghosting configuration signal based on the deghosting enable signal and the first deghosting control signal and generates a second deghosting configuration signal based on the deghosting enable signal and the second deghosting control signal;
when the first and second deghosting configuration signals represent that the deghosting function is turned on and the first deghosting configuration signal represents that the first deghosting mode is the target deghosting mode, the second deghosting control module 11b generates a deghosting execution signal based on a reference voltage signal, a first chip voltage signal and the deghosting adjustment signal, and the second deghosting execution module 13b generates a deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal; or alternatively
When the first and second deghosting configuration signals represent that the deghosting function is turned on and the second deghosting control signals received by the second and second deghosting control modules 11b represent that the second deghosting mode is the target deghosting mode, the second deghosting control module 11b generates a deghosting execution signal based on a bias voltage signal, a second chip voltage signal and the deghosting adjustment signal, and the second deghosting execution module 13b generates a deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal; or alternatively
When the first and second shadow configuration signals represent that the shadow eliminating function is turned on, and the second shadow eliminating configuration signal and the third shadow eliminating control signal received by the second shadow eliminating control module 11b represent that the third shadow eliminating mode is the target shadow eliminating mode, the second shadow eliminating control module 11b generates a shadow eliminating executing signal based on the shadow eliminating adjusting signal, and the second shadow eliminating executing module 13b generates a shadow eliminating current based on the shadow eliminating executing signal and outputs the shadow eliminating current to the diode electrode terminal.
In one embodiment of the present invention, referring to fig. 4, the second shadow control module 11b includes, for example: a second mode control unit 111b and a second ghost adjustment unit 113b. The second mode control unit 111b is electrically connected to the second deghosting execution module 13b, the deghosting configuration circuit 30, and the deghosting protection circuit 40. The second deghosting adjusting unit 113b electrically connects the second mode control unit 111b and the deghosting configuration circuit 30.
As shown in fig. 4, the second shadow elimination execution module 13b includes, for example: the third and fourth vanishing execution units 131b and 133b.
The third vanishing execution unit 131b is connected to the second vanishing control module 11b. The fourth vanishing execution unit 133b is connected to the second vanishing control module 11b.
Specifically, as shown in fig. 4, the second mode control unit 111b is electrically connected to the third deghosting execution unit 131b, the fourth deghosting execution unit 133b, the second deghosting adjustment unit 113b, the deghosting configuration circuit 30, and the deghosting protection circuit 40.
Wherein the second mode control unit 111b receives the deghosting enable signal, the first deghosting control signal, the second deghosting control signal, and the third deghosting control signal to determine the target deghosting mode;
when the first deghosting mode is the target deghosting mode, the second deghosting adjusting unit 113b generates the deghosting execution signal based on the reference voltage signal, the first chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the second deghosting executing module 13b, for example, to a third deghosting executing unit 131b, via the second mode control unit 111b, so that it generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the first deghosting mode; or alternatively
When the second deghosting mode is the target deghosting mode, the second deghosting adjusting unit 113b generates the deghosting execution signal based on the bias voltage signal, the second chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the second deghosting executing module 13b, for example, to a fourth deghosting executing unit 133b, via the second mode control unit 111b, so that it generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the second deghosting mode; or alternatively
When the third deghosting mode is the target deghosting mode, the second mode control unit 111b generates the deghosting execution signal based on the deghosting adjustment signal and outputs the deghosting execution signal to the second deghosting execution module 13b, for example, to the fourth deghosting execution unit 133b, so that it generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the third deghosting mode.
In one embodiment of the present invention, as shown in fig. 4, the shadow protection circuit 40 includes, for example: and a voltage comparing unit 41.
Wherein the voltage comparing unit 41 is electrically connected to the deghosting configuration circuit 30 and the diode electrode terminal, generates the deghosting enable signal based on the port voltage signal and the preset voltage signal, and outputs the generated deghosting enable signal to the second mode control unit 111b of the second deghosting control module 11b.
Specifically, the second mode control unit 111b includes, for example: the first and gate, the second and gate, the fourth control selector, the fifth control selector, and the sixth control selector. The first AND gate has a first input end connected to the deghosting configuration circuit to receive the first deghosting control signal and a second input end connected to the deghosting protection circuit to receive the deghosting enable signal. And a fourth control selector, wherein a first input end is connected with the second shadow eliminating adjusting unit, a second input end is connected with a first signal source, a selection end is connected with the output end of the first AND gate so as to receive the first shadow eliminating configuration signal, and an output end is connected with the second shadow eliminating executing module. And a fifth control selector, wherein the first input end is connected with the second shadow eliminating adjusting unit, the second input end is connected with the shadow eliminating configuration circuit, and the selection end is connected with the shadow eliminating configuration circuit to receive the third shadow eliminating control signal. And the first input end of the second AND gate is connected with the deghosting configuration circuit to receive the second deghosting control signal, and the second input end of the second AND gate is connected with the deghosting protection circuit to receive the deghosting enabling signal. And the sixth control selector is provided with a first input end connected with the output end of the fifth control selector, a second input end connected with a second signal source, a selection end connected with the output end of the second AND gate so as to receive the second shadow eliminating configuration signal, and an output end connected with the second shadow eliminating execution module.
Specifically, the second ghost adjustment unit 113b includes, for example: a third tuning selector and a fourth tuning selector. The third adjusting selector is characterized in that a first input end of the third adjusting selector is connected with the shadow eliminating configuration circuit, a second input end of the third adjusting selector is connected with a first signal source, a selection end of the third adjusting selector is connected with the shadow eliminating configuration circuit, and an output end of the third adjusting selector is connected with the second mode control unit. And the first input end of the fourth adjusting selector is connected with the constant current source generating circuit, the second input end of the fourth adjusting selector is connected with the second signal source, the selecting end of the fourth adjusting selector is connected with the shadow eliminating configuration circuit, and the output end of the fourth adjusting selector is connected with the second mode control unit.
Specifically, the third shadow elimination execution unit 131b includes, for example: and the control end of the third switching element is connected with the second shadow elimination control module, the output end of the third switching element is connected with the electrode end of the diode, and the input end of the third switching element is connected with the second signal source. The fourth deghosting execution unit 133b includes, for example: and the control end of the fourth switching element is connected with the second shadow elimination control module, the output end of the fourth switching element is connected with the electrode end of the diode, and the input end of the fourth switching element is connected with the second signal source.
It should be noted that, most of the structures of the vanishing circuit in the display driving chip shown in fig. 3 and the vanishing circuit in the display driving chip shown in fig. 4 are the same, including:
1. The first vanishing adjusting unit 113a shown in fig. 3 has the same structure as the second vanishing adjusting unit 113b shown in fig. 4, that is, the first adjusting selector in the first vanishing adjusting unit is the same as the third adjusting selector in the second vanishing adjusting unit, and the second adjusting selector in the first vanishing adjusting unit is the same as the fourth adjusting selector in the second vanishing adjusting unit.
2. The first vanishing execution module 13a shown in fig. 3 is identical to the second vanishing execution module 13b shown in fig. 4 in structure, namely: the first vanishing execution unit 131a shown in fig. 3 has the same structure as the third vanishing execution unit 131b shown in fig. 4, i.e., the first switching element in the first vanishing execution unit is the same as the third switching element in the third vanishing execution unit; and the second deghosting unit 133a shown in fig. 3 has the same structure as the fourth deghosting unit 133b shown in fig. 4, i.e. the second switching element in the second deghosting unit is the same as the fourth switching element in the fourth deghosting unit.
3. The first mode control unit 111a shown in fig. 3 is identical in partial structure to the second mode control unit 111b shown in fig. 4, that is, the first control selector in the first mode control unit 111a is identical in structure to the fourth control selector in the second mode control unit 111b, the second control selector in the first mode control unit 111a is identical in structure to the fifth control selector in the second mode control unit 111b, and the third control selector in the first mode control unit 111a is identical in structure to the sixth control selector in the second mode control unit 111 b.
The main difference between the deghosting circuit 10 shown in fig. 3 and the deghosting circuit 10 shown in fig. 4 is that, compared with the first mode control unit 111a shown in fig. 3, the second mode control unit 111b shown in fig. 4 further includes a first and a second and gate, that is, in the deghosting circuit 10 shown in fig. 3, the first mode control unit 111a controls whether the deghosting function is turned on or off by the first and second deghosting control signals respectively received from the deghosting configuration circuit 30 through the first and second control selectors, so that the non-automatic control of the opening or closing of the deghosting function can be realized. In the deghosting circuit 10 shown in fig. 4, the second mode control unit 111b receives the deghosting enable signal from the deghosting protection circuit 40 and the first and second deghosting control signals from the deghosting configuration circuit 30 through the first and second and gates to output the first and second deghosting configuration signals to the fourth and fifth control selectors, respectively, that is, the third and fourth control selectors in the second mode control unit 111a shown in fig. 4 are the same as the first and second control selectors in the first mode control unit 111a shown in fig. 3, respectively, but the signals received at the selection terminals are different, the selection terminals of the third and fourth control selectors in the second mode control unit 111a shown in fig. 4 receive the first and second deghosting configuration signals outputted by the first and second and gates, respectively, and the first and second control selectors in the first mode control unit 111a shown in fig. 3 are turned on or off to enable the deghosting function to be automatically achieved by the first and second control selectors in the second mode control unit 111a shown in fig. 3.
The display driving chip 100 disclosed in the foregoing embodiment is exemplified below.
As shown in fig. 5, the LED lamp panel includes, for example, a display unit array composed of a plurality of display units 210 arranged, and each display unit 210 includes, for example, a plurality of Light Emitting Diodes (LEDs), for example, 3 LEDs. The channels CHN1-CNH3 in the display driving chip 100 are respectively connected to a constant current source generating circuit, as shown in fig. 5, where the constant current source generating circuit outputs a driving current to light the LEDs in the corresponding channels.
The image removing circuit 10 in the display driving chip 100 is connected to, for example, LED electrode terminals, for example, as shown in fig. 5, two image removing circuits 10 are respectively connected to the positive electrode terminal (point a) and the negative electrode terminal (point B) of the LED11 to perform row image removing and column image removing, that is, the image removing circuit 10 disclosed in the embodiment can implement row image removing and column image removing. It should be noted that fig. 5 shows an LED common-negative driving scheme, that is, the shadow eliminating circuit 10 disclosed in this embodiment is suitable for the LED common-negative driving scheme, and in addition, the shadow eliminating circuit 10 disclosed in this embodiment is also suitable for the LED common-positive driving scheme.
As is apparent from the foregoing description, the image canceling circuit shown in fig. 4 has the same partial structure as the image canceling circuit shown in fig. 3, and for convenience of explanation of the image canceling circuit shown in fig. 3 and 4, the first and third adjustment selectors mentioned above are hereinafter referred to as adjustment selector BT1, the second and fourth adjustment selectors are hereinafter referred to as adjustment selector BT2, the first and third switching elements are hereinafter referred to as switching element M1, the second and fourth switching elements are hereinafter referred to as switching element M2, the first and fourth control selectors are hereinafter referred to as control selector BC1, the second and fifth control selectors are hereinafter referred to as control selector BC2, and the third and sixth control selectors are hereinafter referred to as BC3.
The operation of the display driver chip shown in fig. 4 will be described with reference to fig. 6 to 8.
First, the operation principle of the ghost protection circuit 40 will be described. As shown in fig. 6, the voltage comparing unit 41 of the deghosting protection circuit 40 includes, for example, a comparator C1, the comparator C1 receives the port voltage signal and the preset voltage signal deg_vref from the deghosting configuration circuit 30, and outputs the deghosting enable signal EN to the second mode control unit 111b of the deghosting circuit 10.
Taking the line shadow elimination as an example, for the LED common-negative driving scheme, the point B (line pipe pad) is pulled high during line shadow elimination, that is, the voltage rise of the point B is controlled, the comparator C1 compares the port voltage signal of the point B with the preset voltage signal deg_vref, wherein deg_vref can be adjusted by the shadow elimination configuration circuit 30, and if the port voltage signal, that is, the point B voltage is higher than the preset voltage signal deg_vref, the shadow elimination enable signal EN is low, the shadow elimination circuit 10 is in the off state, and the shadow elimination is stopped. If the B point voltage, namely the port voltage signal is lower than the preset voltage signal DEG_VREF, the deghosting enabling signal EN is high, and at the moment, the deghosting circuit is in an enabling state, and the deghosting is continued; it can be seen that the line blanking can be automatically turned off by the comparator C1 of the blanking protection circuit 40 in conjunction with the deg_vref which can be adjusted.
For the column vanishing, for the LED common-negative driving scheme, the point a (channel pad) is pulled down, i.e. the voltage of the point a is controlled to be reduced, the comparator C1 compares the voltage of the point a, i.e. the port voltage signal, with the preset voltage signal deg_vref, i.e. the preset reference voltage, and if the port voltage signal, i.e. the point a voltage, is higher than the preset voltage signal deg_vref, the vanishing enable signal EN is high, and the vanishing circuit is in an enabled state, so that the vanishing can be continued; if the voltage at the point A is lower than the preset voltage signal DEG_VREF, the deghosting enable signal EN is low, and at the moment, the deghosting circuit is in a closed state, and the deghosting is stopped. Therefore, the row shadow elimination can be automatically cut off by the comparator C1 of the shadow elimination protection circuit 40 in cooperation with the adjustable preset voltage signal deg_vref.
The specific circuit configurations of the second deghosting control module 11b and the second deghosting execution module 13b in the deghosting circuit 10 shown in fig. 4 are exemplified below with reference to fig. 7 and 8. Fig. 7 is a circuit configuration diagram of the image erasing circuit 10 shown in fig. 4 for performing line image erasing under the LED common-cathode driving, and fig. 8 is a circuit configuration diagram of the image erasing circuit 10 shown in fig. 4 for performing line image erasing under the LED common-anode driving.
As shown in fig. 7, the third subtraction execution unit 131b includes, for example: the at least one switching element M1, the at least one switching element M1 is, for example, 3 switching elements M1, so that the shadow elimination adjustment of 8 gears can be realized, and of course, the invention is not limited to the specific number of the switching elements M1, and the setting can be performed according to the actual situation, for example, two switching elements M1 are provided, and the shadow elimination adjustment of 4 gears can be realized. Specifically, when the LED common cathode driving scheme performs the line blanking, as shown in fig. 7, the switching element M1 is an NMOS transistor, the control terminal is connected to the second mode control unit 111B, the output terminal is connected to the diode electrode terminal, i.e., the negative electrode terminal of LED11, abbreviated as B point, and the input terminal is connected to the power supply terminal to receive VDD. When the LED common cathode driving scheme performs column blanking, as shown in fig. 8, the switching element M1 is a PMOS transistor, the control terminal is connected to the second mode control unit 111b, the output terminal is connected to the diode electrode terminal, for example, the positive electrode terminal of LED11, abbreviated as a point, and the input terminal is connected to the ground terminal to receive VSS.
The fourth deghosting execution unit 133b includes, for example: the at least one switching element M2 is, for example, 3 switching elements M2, so that the shadow-eliminating adjusting function of 8 gears can be realized, and the invention is not limited to the specific number of the switching elements M2, and can be set according to practical situations. Specifically, when the LED co-cathode driving scheme performs the line blanking, as shown in fig. 7, the switching element M2 is, for example, a PMOS transistor, the control end thereof is connected to the second mode control unit 111B, the output end thereof is connected to the point B, and the input end thereof is connected to the power supply end. When the LED co-cathode driving scheme performs column blanking, as shown in fig. 8, the switching element M2 is, for example, an NMOS transistor, the control terminal thereof is connected to the second mode control unit 111b, the output terminal thereof is connected to the point a, and the input terminal thereof is connected to the ground terminal.
The second mode control unit 111b includes, for example: a control selector BC1, a control selector BC2, a control selector BC3, a first and gate CY1 and a second and gate CY2. The control selector BC1, the control selector BC2 and the control selector BC3 are two-way selectors.
Specifically, the first input terminal of the first and gate CY1 is connected to the deghosting configuration circuit 30 to receive the first deghosting control signal ENN, the second input terminal is connected to the deghosting protection circuit 40, specifically to the output terminal of the comparator C1 to receive the deghosting enable signal EN, and the output terminal outputs the first deghosting configuration signal ENA.
The first input terminal of the second and gate CY2 is connected to the deghosting configuration circuit 30 to receive the second deghosting control signal ENP, the second input terminal is connected to the deghosting protection circuit 40, specifically connected to the output terminal of the comparator C1 to receive the deghosting enable signal EN, and the output terminal outputs the second deghosting configuration signal ENB.
The first input end of the control selector BC1 is connected to the second shadow-eliminating adjusting unit 113b, the selection end is connected to the output end of the first and gate to receive the first shadow-eliminating configuration signal ENA, and the output end is connected to the control end of the switching element M1. Here, it can be understood that the number of the control selectors BC1 is the same as the number of the switching elements M1, for example, the number of the switching elements M1 is three, and three control selectors BC1 are provided to be connected to the control terminals of the switching elements M1, respectively, and fig. 7 is a simplified illustration of the three control selectors BC 1. When the control selector BC1 performs the line blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the ground terminal to receive VSS; when the control selector BC1 performs column blanking in the LED common cathode driving scheme, as shown in fig. 8, the second input terminal is connected to the power supply terminal to receive VDD. Here, it can be understood that when row blanking is performed in the LED common cathode driving scheme, the first signal source is a ground terminal, the first chip voltage signal is VSS, and when column blanking is performed in the LED common cathode driving scheme, the first signal source is a power terminal, and the first chip voltage signal is VDD.
The first input end of the control selector BC2 is connected to the second subtraction adjusting unit 113b, the second input end is connected to the subtraction configuration circuit 30, and the selection end is connected to the subtraction configuration circuit 30 to receive the third subtraction control signal ENS. It should be noted that, the number of control selectors BC2 is the same as the number of the switching elements M2, for example, the number of the switching elements M2 is three, and three control selectors BC2 are provided to receive three shadow eliminating control signals SR <2:0>, respectively, and fig. 7 is a simplified schematic diagram of three control selectors BC 2. Wherein, when the control selector BC2 performs the line blanking in the LED common cathode driving scheme, as shown in FIG. 7, the second input terminal is connected with the blanking configuration circuit to receive the blanking adjustment signal after the inversion processing, namely-! SR <2:0>; when the control selector BC2 performs column blanking in the LED co-cathode driving scheme, as shown in fig. 8, the second input terminal is connected to the blanking configuration circuit to receive the blanking adjustment signals SR <2:0>.
The first input end of the control selector BC3 is connected to the output end of the control selector BC2, the selection end is connected to the output end of the second and gate to receive the second shadow eliminating configuration signal ENB, and the output end is connected to the control end of the switching element M2. Here, it can be understood that the number of the control selectors BC3 is the same as the number of the switching elements M2, for example, the number of the switching elements M2 is three, and three control selectors BC3 are provided to be connected to the control terminals of the switching elements M2, respectively, and fig. 7 is a simplified illustration of the three control selectors BC 3. Wherein, when the control selector BC3 performs the line blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the power terminal to receive VDD; when the control selector BC3 performs column blanking in the LED common cathode driving scheme, as shown in fig. 8, the second input terminal is connected to the ground terminal to receive VSS. It is understood that the second signal source is a power supply terminal, the second chip voltage signal is VDD when row blanking is performed in the LED common cathode driving scheme, the second signal source is a ground terminal, and the second chip voltage signal is VSS when column blanking is performed in the LED common cathode driving scheme.
The second ghost adjustment unit 113b includes, for example: at least one trim selector BT1 and at least one trim selector BT2. Here, fig. 7 and fig. 8 each illustrate three adjusting selectors BT1 and three adjusting selectors BT2, but the present invention is not limited thereto, and the number of adjusting selectors BT1 may be set based on the switching elements M1, for example, the same as the number of switching elements M1, and the number of adjusting selectors BT2 may be set based on the switching elements M2, for example, the same as the number of switching elements M2. The adjust selector BT1 and the adjust selector BT2 are either one of two selectors.
Specifically, the first input terminal of the adjusting selector BT1 is connected to the deghosting configuration circuit 30 to receive the reference voltage signal vb1_ref, the selecting terminal is connected to the deghosting configuration circuit 30 to receive the deghosting adjusting signal SR, and the output terminal is connected to the first input terminal of the control selector BC 1. When the adjustment selector BT1 performs the line blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the ground terminal to receive VSS; when the column blanking is performed in the LED common cathode driving scheme, the adjust selector BT1, as shown in fig. 8, has a second input terminal connected to the power supply terminal to receive VDD.
The first input end of the adjusting selector BT2 is connected to the constant current source generating circuit to receive the bias voltage signal VBP, the selecting end is connected to the deghosting configuration circuit 30 to receive the deghosting adjusting signal SR, and the output end is connected to the first input end of the control selector BC 2. Wherein, when the adjustment selector BT2 performs the line blanking in the LED common cathode driving scheme, as shown in fig. 7, the second input terminal is connected to the power terminal to receive VDD; when the column blanking is performed in the LED common cathode driving scheme, the adjust selector BT2 has a second input terminal connected to ground for receiving VSS as shown in fig. 8.
The blanking circuit 10 performs a blanking function, whether the row blanking or the column blanking, for example, has three blanking modes: the first vanishing mode, the second vanishing mode, for example, is a constant current source vanishing mode and the third vanishing mode, for example, is a super vanishing mode. The first blanking mode is an NMOS blanking mode when the blanking circuit executes the line blanking in the LED common cathode driving scheme, and is a PMOS blanking mode when the blanking circuit executes the column blanking in the LED common cathode driving scheme. The three modes of image cancellation can be switched by the image cancellation control signal.
The operation principle of the blanking circuit 10 will be described below with reference to fig. 7, taking the blanking circuit 10 shown in fig. 4 as an example of performing the line blanking in the LED common cathode driving scheme.
When the blanking enable signal EN is "1", the first blanking control signal ENN is "1", the second blanking control signal ENP is "0", the first and gate CY1 outputs the first blanking configuration signal ENA as "1", the second and gate CY2 outputs the second blanking configuration signal ENB as "0", at this time, the control selector BC3 inputs VDD to the control terminal of the switching element M2 based on the second blanking configuration signal ENB as "0", the switching element M2 is turned off, and the blanking circuit 10 operates in the first blanking mode, i.e., the NMOS blanking mode.
In the first deghosting mode, the deghosting configuration circuit 30 outputs the deghosting adjustment signals SR <2:0> to the selection terminals of three adjustment selectors BT1, respectively, each adjustment selector BT1 selects to output based on the input deghosting adjustment signals, taking VB1<0> as an example, when SR <0> is 1, the adjustment selector BT1 outputs the reference voltage signal VB1_REF as VB1<0>, and when SR <0> is 0, the adjustment selector BT1 outputs the VSS signal as VB1<0 >. The control selector BC1 outputs the received VB1<2:0> as the deghosting signals V <2:0> to the control terminals of the three switching elements M1, respectively, when the voltage of the control terminal of the switching element M1 is high, the switching element M1 is turned on, and a constant current of a certain magnitude, that is, a deghosting current is generated for deghosting (charging the point B), when the voltage of the control terminal of the switching element M1 is low, the switching element M1 is turned off, and the deghosting current corresponding to the switching element M1 is 0. The three switching elements M1 are controlled to be turned on or off by the deghosting adjusting signals SR <2:0>, so that the adjustment of the deghosting capability in the first deghosting mode is realized, and the conduction of the switching elements M1 with different numbers and different positions corresponds to different deghosting capabilities, i.e. the deghosting circuit 10 shown in fig. 7 has 8 types of deghosting capabilities when operating in the first deghosting mode.
When the blanking enable signal EN is "1", the first blanking control signal ENN is "0", the second blanking control signal ENP is "1", the first and gate CY1 outputs the first blanking configuration signal ENA as "0", the second and gate CY2 outputs the second blanking configuration signal ENB as "1", for example, at this time, the third blanking control signal ENs is "0", the control selector BC1 outputs the signal VSS to the control terminal of the switching element M1 based on the first blanking configuration signal ENA as "0", so that the switching element M1 is turned off, and the control selector BC2 outputs the VB2<2:0> as the signals VC <2:0>, at this time, the blanking circuit 10 operates in the second blanking mode.
In the second deghosting mode, the deghosting configuration circuit 30 outputs the deghosting adjustment signals SR <2:0> to the control terminals of three adjustment selectors BT2, respectively, each adjustment selector BT2 selecting an output based on the input deghosting adjustment signals, taking VB2<0> as an example, when SR <0> is 1, the adjustment selector BT2 outputs the bias voltage signal VBP from the constant current source generating circuit as VB2<0>, and when SR <0> is 0, the adjustment selector BT2 outputs the VDD signal as VB2<0 >. The control selector BC2 inputs VB2<2:0> as VC <2:0> to the control selector BT3, the control selector BT3 outputs VC <2:0> as the deghosting signals V <2:0> to the control terminals of the three switching elements M2, respectively, when the voltage of the control terminal of the switching element M2 is low, the switching element M2 is turned on, and a constant current, that is, a deghosting current, is generated for deghosting (charging the point B), and when the voltage of the control terminal of the switching element M2 is high, the switching element M2 is turned off, and the corresponding deghosting current of the switching element M2 is 0, thereby controlling the three switching elements M2 to be turned on or off by the deghosting adjustment signal SR <2:0>, so as to realize adjustment of the deghosting capability in the second deghosting mode, that the switching elements M2 of different numbers and different positions are turned on, that is, the deghosting circuit 10 shown in fig. 7 works in the second deghosting mode to have 8 kinds of deghosting capability. It is worth mentioning that the second shadow eliminating mode, i.e. the constant current source shadow eliminating mode, is characterized in that the size of the shadow eliminating current can be adjusted, and the constant current is adopted in each gear, i.e. the shadow eliminating currents of all chips in the same gear are identical, so that good consistency is maintained, the overall shadow eliminating speed is slow, and the EMI is good.
When the blanking enable signal EN is "1", the first blanking control signal ENN is "0", the second blanking control signal ENP is "1", the first and gate CY1 outputs the first blanking configuration signal ENA as "0", the second and gate CY2 outputs the second blanking configuration signal ENB as "1", for example, at this time, the third blanking control signal ENs is "1", the control selector BC1 outputs the signal VSS to the control terminal of the switching element M1 based on the first blanking configuration signal ENA as "0", so that the switching element M1 is turned off, and the control selector BC2 outputs-! SR <2:0> is output as signals VC <2:0>, and the deghosting circuit 10 operates in the third deghosting mode.
In the third deghosting mode, the deghosting configuration circuit 30 outputs the deghosting adjustment signal after the inversion process ≡! SR <2:0> to three control selectors BC2, respectively, each control selector BC2 will be based on the third vanishing control signal being "1" ≡! SR <2:0> is output as signals VC <2:0>, taking as an example VC <0>, when SR <0> =1, VC <0> =0, and when SR <0> =0, VC <0> =1. The control selector BT3 outputs VC <2:0> as the deghosting signals V <2:0> to the control ends of the three switching elements M2, respectively, when the voltage of the control end of the switching element M2 is low, the switching element M2 is turned on, and a constant current with a certain magnitude, that is, a deghosting current, is generated for deghosting (charging the point B), when the voltage of the control end of the switching element M2 is high, the switching element M2 is turned off, and the deghosting current corresponding to the switching element M2 is 0, thereby controlling the three switching elements M2 to be turned on or off by the deghosting adjustment signals SR <2:0>, and thus realizing adjustment of the deghosting capability in the third deghosting mode. It should be noted that the third deghosting mode, i.e. the super deghosting mode, is characterized in that the size of the deghosting current can be adjusted, and the gate voltage, i.e. the voltage of the control terminal, is directly 0 when the switching element M2 is turned on, so that the blanking speed is very fast, and for the lamp panel with relatively large row parasitic capacitance, the deghosting time can be greatly reduced, and the real display time is increased.
The operation principle of the blanking circuit 10 shown in fig. 4 for performing column blanking in the LED common cathode driving scheme is similar to that of the LED common cathode driving scheme, and the operation principle of the blanking circuit 10 will be described below with reference to fig. 8 by taking the example that the blanking circuit 10 performs column blanking in the LED common cathode driving scheme.
When the blanking enable signal EN is "1", the first blanking control signal ENN is "1", the second blanking control signal ENP is "0", the first and gate CY1 outputs the first blanking configuration signal ENA as "1", the second and gate CY2 outputs the second blanking configuration signal ENB as "0", the control selector BC3 inputs VSS to the control terminal of the switching element M2 based on the second blanking configuration signal ENB as "0", the switching element M2 is turned off, and the blanking circuit 10 operates in the first blanking mode, i.e., the PMOS blanking mode.
In the first deghosting mode, the deghosting configuration circuit 30 outputs the deghosting adjustment signals SR <2:0> to the selection terminals of three adjustment selectors BT1, respectively, each adjustment selector BT1 selecting an output based on the input deghosting adjustment signals, taking VB1<0> as an example, when SR <0> is 1, the adjustment selector BT1 outputs the reference voltage signal VB1_REF as VB1<0>, and when SR <0> is 0, the adjustment selector BT1 outputs the VDD signal as VB1<0 >. Wherein the reference voltage signal vb1_ref can be adjusted by blanking configuration circuit 30. The control selector BC1 outputs the received VB1<2:0> as the deghosting signals V <2:0> to the control terminals of the three switching elements M1, respectively, when the voltage of the control terminal of the switching element M1 is low, the switching element M1 is turned on, and a constant current of a certain magnitude, that is, a deghosting current is generated for deghosting (discharging the point a), when the voltage of the control terminal of the switching element M1 is high, the switching element M1 is turned off, and the deghosting current corresponding to the switching element M1 is 0. The three switching elements M1 are controlled to be turned on or off by the deghosting adjusting signals SR <2:0>, so that the adjustment of the deghosting capability in the first deghosting mode is realized, and the conduction of the switching elements M1 with different numbers and different positions corresponds to different deghosting capabilities, i.e. the deghosting circuit 10 shown in fig. 8 has 8 types of deghosting capabilities in the first deghosting mode. The PMOS blanking mode can control the channel voltage after the final PMOS shadow elimination is finished (because the source voltage of the PMOS is the lowest equal to the gate voltage of the PMOS), and after the shadow elimination is finished, the PMOS shadow elimination mode can also have certain driving capability on the voltage at the channel pin (LED anode) so as to avoid the output pin to be in a suspended state, thereby being beneficial to the optimization of coupling.
When the deghosting enable signal EN is "1", the first deghosting control signal ENN is "0", the second deghosting control signal ENP is "1", the first and gate CY1 outputs the first deghosting configuration signal ENA as "0", the second and gate CY2 outputs the second deghosting configuration signal ENB as "1", for example, the third deghosting control signal ENs received at this time is "0", the control selector BC1 outputs the signal VDD to the control terminal of the switching element M1 based on the first deghosting configuration signal ENA as "0", so that the switching element M1 is turned off, and the control selector BC2 outputs the VB2<2:0> as the signal VC <2:0>, at this time the deghosting circuit 10 operates in the second deghosting mode.
In the second deghosting mode, the deghosting configuration circuit 30 outputs the deghosting adjustment signals SR <2:0> to the selection terminals of three adjustment selectors BT2, respectively, each adjustment selector BT2 selects to output based on the input deghosting adjustment signals, taking VB2<0> as an example, when SR <0> is 1, the adjustment selector BT2 outputs the bias voltage signal VBP from the constant current source generating circuit as VB2<0>, and when SR <0> is 0, the adjustment selector BT2 outputs the VSS signal as VB2<0 >. It should be noted that, the magnitude of the current bias voltage signal VBP is different from that of the bias voltage signal of the blanking circuit in the LED common cathode driving scheme for performing the line blanking, the current bias voltage signal VBP may be understood as "1", and then the bias voltage signal of the blanking circuit in the LED common cathode driving scheme for performing the line blanking should be understood as "0". The control selector BC2 inputs VB2<2:0> as VC <2:0> to the control selector BT3, the control selector BT3 outputs VC <2:0> as the deghosting signals V <2:0> to the control terminals of the three switching elements M2, respectively, when the voltage of the control terminal of the switching element M2 is high, the switching element M2 is turned on, and a constant current, that is, a deghosting current, is generated for deghosting (discharging the point a), and when the voltage of the control terminal of the switching element M2 is low, the switching element M2 is turned off, and the corresponding deghosting current of the switching element M2 is 0, thereby controlling the three switching elements M2 to be turned on or off by the deghosting adjustment signal SR <2:0>, so as to realize adjustment of the deghosting capability in the second deghosting mode, that is, the deghosting circuit 10 shown in fig. 6 works in the second deghosting mode with 8 types of deghosting capability. It is worth mentioning that the second shadow eliminating mode, i.e. the constant current source shadow eliminating mode, is characterized in that the size of the shadow eliminating current can be adjusted, and the constant current is adopted in each gear, i.e. the shadow eliminating currents of all chips in the same gear are identical, so that good consistency is maintained, the overall shadow eliminating speed is slow, and the EMI is good.
When the deghosting enable signal EN is "1", the first deghosting control signal ENN is "0", the second deghosting control signal ENP is "1", the first and gate CY1 outputs the first deghosting configuration signal ENA as "0", the second and gate CY2 outputs the second deghosting configuration signal ENB as "1", for example, the third deghosting control signal ENs received at this time is "1", the control selector BC1 outputs the signal VDD to the control terminal of the switching element M1 based on the first deghosting configuration signal ENA as "0", so that the switching element M1 is turned off, and the control selector BC2 outputs SR <2:0> as the signals VC <2:0>, at this time the deghosting circuit 10 operates in the third deghosting mode.
In the third deghosting mode, the deghosting configuration circuit 30 outputs the deghosting adjustment signals SR <2:0> to the three control selectors BC2, respectively, the control selector BC2 outputs SR <2:0> as signals VC <2:0> based on the third deghosting control signal being "1", taking VC <0> as an example, when SR <0> = 1, VC <0> = 1, when SR <0> = 0, VC <0> = 0. The control selector BT3 outputs VC <2:0> as the deghosting signals V <2:0> to the control ends of the three switching elements M2, respectively, when the voltage of the control end of the switching element M2 is high, the switching element M2 is turned on, and a constant current with a certain magnitude, that is, a deghosting current, is generated for deghosting (discharging the point a), when the voltage of the control end of the switching element M2 is low, the switching element M2 is turned off, and the deghosting current corresponding to the switching element M2 is 0, thereby controlling the three switching elements M2 to be turned on or off by the deghosting adjustment signals SR <2:0>, and thus realizing adjustment of the deghosting capability in the third deghosting mode. It should be noted that the third deghosting mode, i.e. the super deghosting mode, is characterized in that the size of the deghosting current can be adjusted, and the gate voltage, i.e. the voltage of the control terminal, is VDD when the switching element M2 is turned on, so that the blanking speed is very fast, and for the lamp panel with relatively large row parasitic capacitance, the deghosting time can be greatly reduced, and the real display time is increased.
In addition, the working principle of the display driving chip shown in fig. 3 is basically the same as that of the display driving chip shown in fig. 4, and includes the same three shadow eliminating modes, and the difference is that: the display driving chip shown in fig. 3 does not include the ghost protection circuit, so the ghost circuit 10 shown in fig. 3 does not need to receive the ghost enable signal EN, and thus the structure of the first mode control unit 111a is different from that of the second mode control unit 111 b. Fig. 9 is a circuit configuration diagram of the deghosting circuit 10 shown in fig. 3 performing row deghosting in the LED common-cathode driving scheme, fig. 10 is a circuit configuration diagram of the deghosting circuit 10 shown in fig. 3 performing column deghosting in the LED common-cathode driving scheme, and as shown in fig. 9 and 10, the first mode control unit 111a includes: the control selector BC1, the control selector BC2, and the control selector BC3 do not include the first and second and gates CY1 and CY2 shown in fig. 7 and 8. The difference between the control selector BC1, the control selector BC2, and the control selector BC3 shown in fig. 9 and fig. 10, which are two-way selectors, and the control selector BC1, the control selector BC2, and the control selector BC3 shown in fig. 7 and fig. 8 is that the selection terminal of the control selector BC1 shown in fig. 9 and fig. 10 is connected to the deghosting circuit 30 to receive the first deghosting control signal ENN, and the selection terminal of the control selector BC3 is connected to the deghosting circuit 30 to receive the second deghosting control signal ENP.
Here, it can be understood that, when the display driving chip does not include the deghosting protection circuit 40, whether the deghosting function is turned on or not can be controlled by the first deghosting control signal ENN and the second deghosting control signal ENP output by the deghosting configuration circuit 30. For the deghosting circuit shown in fig. 3, the working principle is the same as that of the deghosting circuit shown in fig. 4 for executing the deghosting according to the first deghosting configuration signal ENA and the second deghosting configuration signal ENB, that is, the working principle of the first deghosting control signal ENN and the second deghosting control signal ENP shown in fig. 9 and fig. 10 in the deghosting circuit is equivalent to that of the first deghosting configuration signal ENA and the second deghosting configuration signal ENB shown in fig. 7 and fig. 8 in the deghosting circuit, so that the specific working process of the deghosting circuit shown in fig. 3, that is, the principle of the structure shown in fig. 9 and fig. 10 can be referred to the related description of fig. 7 and fig. 8, respectively, and will not be repeated here.
In addition, the blanking circuit 10 in the display driving chip 100 disclosed in this embodiment is also applicable to perform blanking under the LED common-positive driving scheme, and is basically the same as the foregoing principle of performing blanking under the LED common-negative driving scheme, except that: the LED common positive driving scheme downlink shadow elimination is that a shadow elimination circuit is required to pull down a point B (LED anode), namely, a downlink parasitic capacitor is discharged to low voltage through a pull-down tube, namely, the voltage drop of the point B is controlled, so that the scheme shown in fig. 8 and 10 is suitable for the downlink shadow elimination under the LED common positive driving scheme; the following vanishing of the LED common-anode driving scheme is that the vanishing circuit is required to pull up the point a (LED cathode), i.e. charge the row parasitic capacitance to a high voltage through the pull-down tube, i.e. control the voltage rise of the point a, so the scheme shown in fig. 7 and 9 is suitable for the column vanishing of the LED common-anode driving scheme. The specific operation of the image cancellation circuit 10 in the display driving chip 100 for performing image cancellation under the LED common-positive driving scheme is not described herein. In addition, it is to be noted that the specific setting of the signal SR <2:0> in the foregoing illustration is to achieve the maximum image cancellation capability of the image cancellation circuit 10 when the signal SR <2:0> is all high, but the invention is not limited thereto, and the signal level can be set according to the actual requirement.
In summary, the display driving chip 100 disclosed in the foregoing embodiment of the invention has the following advantages:
1. by arranging the deghosting configuration circuit 30 and the deghosting circuit 10 in the display driving chip 100, after the deghosting function is started, the deghosting circuit 10 determines to work in a target deghosting mode in a plurality of deghosting modes based on the deghosting control signal, namely the deghosting circuit 10 can realize a plurality of deghosting modes, so that the situation that the existing deghosting scheme is single and scheme adjustment cannot be carried out according to the application requirements is avoided, the deghosting circuit 10 determines the target deghosting mode in a plurality of deghosting modes based on the deghosting control signal, different application requirements can be met, ghost phenomena in the LED display process can be effectively removed, and the display effect is improved;
2. the shadow eliminating circuit 10 controls the voltage of the electrode terminal of the diode to rise or fall by setting the shadow eliminating adjusting signal, so that the adjustability of the shadow eliminating capability is realized, namely, a user can flexibly set the shadow eliminating adjusting signal according to the actual working condition of the display driving chip to adjust the shadow eliminating capability, and the problems that the shadow eliminating capability is too fast to generate EMI and the shadow eliminating capability is too slow to occupy too much display time are solved;
3. By arranging the shadow eliminating protection circuit 40 in the shadow eliminating circuit 10, the situation that the service life of the LED is influenced by the fact that the LED is in a reverse bias state for a long time when the shadow eliminating is carried out in the existing shadow eliminating scheme can be avoided, the shadow eliminating function is automatically turned on or off, the service life of the LED is also considered when the shadow eliminating is carried out, and the adaptability and the practicability are better;
4. the shadow eliminating circuit 10 in the display driving chip 100 can not only execute the shadow eliminating function under the LED common-negative driving scheme, but also execute the shadow eliminating function under the LED common-positive driving scheme, and further, the shadow eliminating circuit 10 is not only suitable for row shadow elimination, but also suitable for column shadow elimination, and has wider application range;
5. the display driving chip 100 can further enhance the shadow eliminating effect and improve the display effect by providing a plurality of shadow eliminating circuits 10 to perform the line blanking and the column shadow eliminating at the same time.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and matched without conflict in technical features, contradiction in structure, and departure from the purpose of the present invention.
In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and/or methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and the division of the units/modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units/modules described as separate units may or may not be physically separate, and units/modules may or may not be physically units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated in one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated in one unit/module. The integrated units/modules may be implemented in hardware or in hardware plus software functional units/modules.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (12)

1. A display driving chip, comprising:
a shadow elimination configuration circuit;
the shadow eliminating circuit is electrically connected with the shadow eliminating configuration circuit;
the shadow eliminating configuration circuit outputs a shadow eliminating adjusting signal and a shadow eliminating control signal; after the shadow eliminating circuit starts the shadow eliminating function, the shadow eliminating circuit determines to work in a target shadow eliminating mode in a plurality of shadow eliminating modes based on the shadow eliminating control signals, and controls the voltage of the diode electrode terminal of the light emitting diode to rise or fall based on the shadow eliminating adjusting signals in the target shadow eliminating mode.
2. The display driver chip of claim 1, further comprising:
a blanking protection circuit electrically connected to the blanking circuit and the blanking configuration circuit; the blanking protection circuit acquires a port voltage signal of the diode electrode terminal and a preset voltage signal input by the deghosting configuration circuit to generate a deghosting enabling signal, and outputs the deghosting enabling signal to the deghosting circuit to control whether to start the deghosting function.
3. The display driver chip of claim 1, wherein the shadow cancellation circuit comprises:
the first shadow elimination control module is electrically connected with the shadow elimination configuration circuit;
The first shadow eliminating execution module is electrically connected with the first shadow eliminating control module;
wherein, the plurality of vanishing modes includes a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: the first, second and third vanishing control signals; the first vanishing control module receives the first vanishing control signal, the second vanishing control signal and the vanishing adjusting signal;
when the first shadow elimination control signal and the second shadow elimination control signal represent that the shadow elimination function is started and the first shadow elimination control signal represents that the first shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module generates a shadow elimination execution signal based on a reference voltage signal, a first chip voltage signal and the shadow elimination adjustment signal, and the first shadow elimination execution module generates a shadow elimination current to the diode electrode terminal based on the shadow elimination execution signal; or alternatively
When the first shadow elimination control signal and the second shadow elimination control signal represent that the shadow elimination function is started, and the second shadow elimination control signal and the third shadow elimination control signal received by the first shadow elimination control module represent that the second shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module generates a shadow elimination executing signal based on a bias voltage signal, a second chip voltage signal and the shadow elimination regulating signal, and the first shadow elimination executing module generates a shadow elimination current based on the shadow elimination executing signal and outputs the shadow elimination current to the diode electrode terminal; or alternatively
When the first shadow elimination control signal and the second shadow elimination control signal represent that the shadow elimination function is started, and the second shadow elimination control signal and the third shadow elimination control signal received by the first shadow elimination control module represent that the third shadow elimination mode is the target shadow elimination mode, the first shadow elimination control module generates a shadow elimination executing signal based on the shadow elimination adjusting signal, and the first shadow elimination executing module generates a shadow elimination current based on the shadow elimination executing signal and outputs the shadow elimination current to the electrode end of the diode.
4. The display driver chip of claim 3, wherein the first shadow elimination control module comprises:
the first mode control unit is electrically connected with the first shadow elimination execution module and the shadow elimination configuration circuit; and
the first shadow eliminating adjusting unit is electrically connected with the first mode control unit and the shadow eliminating configuration circuit;
wherein the first mode control unit receives the first, second and third deghosting control signals to determine the target deghosting mode, wherein,
when the first deghosting mode is the target deghosting mode, the first deghosting adjusting unit generates the deghosting execution signal based on the reference voltage signal, the first chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the first deghosting execution module through the first mode control unit; or alternatively
When the second deghosting mode is the target deghosting mode, the first deghosting adjusting unit generates the deghosting execution signal based on the bias voltage signal, the second chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the first deghosting execution module through the first mode control unit; or alternatively
When the third vanishing mode is the target vanishing mode, the first mode control unit generates the vanishing execution signal based on the vanishing adjustment signal and outputs the vanishing execution signal to the first vanishing execution module.
5. The display driver chip of claim 4, wherein the first mode control unit comprises:
the first control selector is provided with a first input end connected with the first shadow eliminating adjusting unit, a second input end connected with a first signal source, a selection end connected with the shadow eliminating configuration circuit to receive the first shadow eliminating control signal, and an output end connected with the first shadow eliminating execution module;
the first input end of the second control selector is connected with the first shadow eliminating adjusting unit, the second input end of the second control selector is connected with the shadow eliminating configuration circuit, and the selection end of the second control selector is connected with the shadow eliminating configuration circuit to receive the third shadow eliminating control signal; and
And the first input end of the third control selector is connected with the output end of the second control selector, the second input end of the third control selector is connected with a second signal source, the selection end of the third control selector is connected with the shadow elimination configuration circuit to receive the second shadow elimination control signal, and the output end of the third control selector is connected with the first shadow elimination execution module.
6. The display driver chip of claim 2, wherein the shadow cancellation circuit comprises:
the second shadow eliminating control module is electrically connected with the shadow eliminating configuration circuit and the shadow eliminating protection circuit;
the second shadow eliminating execution module is electrically connected with the second shadow eliminating control module;
wherein, the plurality of vanishing modes includes a first vanishing mode, a second vanishing mode and a third vanishing mode, and the vanishing control signal includes: the first, second and third vanishing control signals; the second deghosting control module receives the deghosting enable signal, the first deghosting control signal, the second deghosting control signal and the deghosting adjustment signal, generates a first deghosting configuration signal based on the deghosting enable signal and the first deghosting control signal, and generates a second deghosting configuration signal based on the deghosting enable signal and the second deghosting control signal;
When the first and second shadow elimination configuration signals represent that the shadow elimination function is started and the first shadow elimination configuration signal represents that the first shadow elimination mode is the target shadow elimination mode, the second shadow elimination control module generates a shadow elimination execution signal based on a reference voltage signal, a first chip voltage signal and the shadow elimination adjustment signal, and the second shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the diode electrode terminal; or alternatively
When the first deghosting configuration signal and the second deghosting configuration signal represent that the deghosting function is started, and the second deghosting configuration signal and the third deghosting control signal received by the second deghosting control module represent that the second deghosting mode is the target deghosting mode, the second deghosting control module generates a deghosting execution signal based on a bias voltage signal, a second chip voltage signal and the deghosting adjustment signal, and the second deghosting execution module generates a deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal; or alternatively
When the first shadow elimination configuration signal and the second shadow elimination configuration signal represent that the shadow elimination function is started, and the second shadow elimination configuration signal and the third shadow elimination control signal received by the second shadow elimination control module represent that the third shadow elimination mode is the target shadow elimination mode, the second shadow elimination control module generates a shadow elimination execution signal based on the shadow elimination adjustment signal, and the second shadow elimination execution module generates a shadow elimination current based on the shadow elimination execution signal and outputs the shadow elimination current to the electrode terminal of the diode.
7. The display driver chip of claim 6, wherein the second shadow elimination control module comprises:
the second mode control unit is electrically connected with the second shadow elimination execution module, the shadow elimination configuration circuit and the shadow elimination protection circuit; and
the second shadow eliminating adjusting unit is electrically connected with the second mode control unit and the shadow eliminating configuration circuit;
wherein the second mode control unit receives the deghosting enable signal, the first deghosting control signal, the second deghosting control signal, and the third deghosting control signal to determine the target deghosting mode, wherein,
when the first deghosting mode is the target deghosting mode, the second deghosting adjusting unit generates the deghosting execution signal based on the reference voltage signal, the first chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the second deghosting execution module through the second mode control unit; or alternatively
When the second deghosting mode is the target deghosting mode, the second deghosting adjusting unit generates the deghosting execution signal based on the bias voltage signal, the second chip voltage signal and the deghosting adjusting signal, and outputs the deghosting execution signal to the second deghosting execution module through the second mode control unit; or alternatively
When the third vanishing mode is the target vanishing mode, the second mode control unit generates the vanishing execution signal based on the vanishing adjustment signal and outputs the vanishing execution signal to the second vanishing execution module.
8. The display driving chip according to claim 7, wherein the second mode control unit includes:
the first input end of the first AND gate is connected with the deghosting configuration circuit to receive the first deghosting control signal, and the second input end of the first AND gate is connected with the deghosting protection circuit to receive the deghosting enabling signal;
a fourth control selector, wherein a first input end is connected with the second shadow eliminating adjusting unit, a second input end is connected with a first signal source, a selection end is connected with an output end of the first AND gate to receive the first shadow eliminating configuration signal, and an output end is connected with the second shadow eliminating executing module;
a fifth control selector, the first input end of which is connected with the second shadow eliminating adjusting unit, the second input end of which is connected with the shadow eliminating configuration circuit, and the selection end of which is connected with the shadow eliminating configuration circuit to receive the third shadow eliminating control signal;
the first input end of the second AND gate is connected with the deghosting configuration circuit to receive the second deghosting control signal, and the second input end of the second AND gate is connected with the deghosting protection circuit to receive the deghosting enabling signal;
And the sixth control selector is provided with a first input end connected with the output end of the fifth control selector, a second input end connected with a second signal source, a selection end connected with the output end of the second AND gate so as to receive the second shadow eliminating configuration signal, and an output end connected with the second shadow eliminating execution module.
9. The display driver chip of claim 3, wherein the first shadow elimination execution module comprises:
the first shadow eliminating execution unit is connected with the first shadow eliminating control module;
the second shadow eliminating execution unit is connected with the first shadow eliminating control module;
the first deghosting execution unit generates the deghosting current based on the deghosting execution signal in the first deghosting mode and outputs the deghosting current to the electrode terminal of the diode; or the second deghosting execution unit generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the second deghosting mode or the third deghosting mode.
10. The display driver chip of claim 6, wherein the second shadow elimination execution module comprises:
the third shadow eliminating execution unit is connected with the second shadow eliminating control module;
The fourth shadow eliminating execution unit is connected with the second shadow eliminating control module;
the third shadow eliminating executing unit generates the shadow eliminating current based on the shadow eliminating executing signal in the first shadow eliminating mode and outputs the shadow eliminating current to the electrode end of the diode; or the fourth deghosting execution unit generates the deghosting current based on the deghosting execution signal and outputs the deghosting current to the diode electrode terminal in the second deghosting mode or the third deghosting mode.
11. The display driver chip of claim 2, wherein the shadow elimination protection circuit comprises:
and the voltage comparison unit is electrically connected with the shadow elimination configuration circuit and the diode electrode terminal and generates the shadow elimination enabling signal based on the port voltage signal and the preset voltage signal.
12. An LED lamp panel, comprising:
a display unit array including a plurality of display units, each of the display units including a plurality of light emitting diodes; and
the display driver chip of any one of claims 1-11, wherein the shadow canceling circuit of the display driver chip is connected to the diode electrode terminal of the light emitting diode.
CN202111423926.8A 2021-11-26 2021-11-26 Display driving chip and LED lamp panel Pending CN116189602A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111423926.8A CN116189602A (en) 2021-11-26 2021-11-26 Display driving chip and LED lamp panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111423926.8A CN116189602A (en) 2021-11-26 2021-11-26 Display driving chip and LED lamp panel

Publications (1)

Publication Number Publication Date
CN116189602A true CN116189602A (en) 2023-05-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111423926.8A Pending CN116189602A (en) 2021-11-26 2021-11-26 Display driving chip and LED lamp panel

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Country Link
CN (1) CN116189602A (en)

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