CN115294928A

CN115294928A - Shadow elimination circuit, line driving circuit and display screen

Info

Publication number: CN115294928A
Application number: CN202211229402.XA
Authority: CN
Inventors: 唐永生; 黄立; 申石林; 刘阿强
Original assignee: Chengdu Lipson Microelectronics Co ltd
Current assignee: Chengdu Lipson Microelectronics Co ltd
Priority date: 2022-10-08
Filing date: 2022-10-08
Publication date: 2022-11-04
Anticipated expiration: 2042-10-08
Also published as: CN115294928B

Abstract

The application provides a shadow elimination circuit, a line driving circuit and a display screen, wherein the shadow elimination circuit comprises an amplifier, a first transistor and a reference voltage output module; the output end of the reference voltage output module is electrically connected with the inverting input end of the amplifier and is used for outputting a first reference voltage to the inverting input end when the row driving module is started and outputting a second reference voltage to the inverting input end when the row driving module is closed; the non-inverting input end of the amplifier is electrically connected with the output end of the row driving module, and the amplifier outputs an amplified signal to the driving end of the first transistor; the drain electrode of the first transistor is electrically connected with the output end of the row driving module, and the source electrode of the first transistor is grounded or is supplied with power voltage; when the source of the first transistor is grounded and connected with a power voltage, the first reference voltage is respectively a power voltage and a ground voltage. The technical scheme of this application can effectively eliminate the last ghost phenomenon of LED display screen and avoid short circuit caterpillar phenomenon.

Description

Shadow elimination circuit, line driving circuit and display screen

Technical Field

The application relates to the field of display screens, in particular to a shadow eliminating circuit, a line driving circuit and a display screen.

Background

In an LED (Light Emitting Diode) display screen system, a constant current source driving chip may be used to drive a plurality of LED lamp beads.

Fig. 1 shows a common structure of a common anode (the anodes of 3 RGB beads are connected together, the cathodes are separated) LED display driver in an LED display screen unit board (only beads of one color are shown), and a common cathode (the cathodes of 3 RGB beads are connected together, the anodes are separated) LED display screen unit board is a reverse structure of all the LED beads in fig. 1.

The row driver is usually a switching power transistor, the column driver is usually a constant current source, and usually the constant current source driving chip will include a plurality of constant current output driving channels, and the constant current output channel (OUT) is connected to the column line (1 st/2 nd column 8230; nth column) in fig. 1.

The working principle is as follows:

1. firstly, displaying a line 1, wherein power tubes of the line 1 of the line driving chip are switched on, power tubes of other lines are switched off, and row lines of other lines are high impedance;

2. the column driving (constant current source driving) chip correspondingly outputs constant current sources according to the display data of the 1 st row in columns, lightens the LED display lamp beads of the 1 st row and displays the display image of the 1 st row;

3. in this way, the rows are wrapped in turn (for row 2-m, the operation steps 1-2 are repeated as for row 1), and the image is displayed for all columns and rows.

In fact, due to the presence of lamp panel row line parasitic capacitors C1-Cm, when the ith row is turned off, the voltage held on parasitic capacitor Ci is the voltage when the ith row is turned on, and when switching to the (i + 1) th row, if the column driver lights a certain column of lamp beads on the (i + 1) th row:

for a common-anode display screen, the voltage of a corresponding column line is pulled down, the voltage difference between two electrodes of the lamp bead in the ith row meets the starting condition and is lightened, and only the electric charge stored by the parasitic capacitor Ci in the ith row is discharged through the column driving and cannot be supplemented newly, so that when a certain column of lamp beads in the (i + 1) th row is lightened, the lamp bead in the ith row is dark and bright, namely ghost shadow is formed (the LED display screen is usually scanned line by line from top to bottom).

For a common cathode display screen, the voltage of a corresponding column line is pulled high, the voltage difference between two poles of a lamp bead in the ith row meets the starting condition and can be lightened, and only the electric charge stored by the parasitic capacitor Ci in the ith row does not have a new discharge path after being supplemented by column driving, so that when a certain lamp bead in the (i + 1) th row is lightened, the lamp bead in the ith row can be dark and bright, namely ghost image appears.

Meanwhile, in the prior art, the effects of eliminating ghost images and avoiding short-circuit caterpillars cannot be achieved at the same time. For example, for a common-anode LED display screen, when the ith row is driven to be turned off, the shading circuit pulls the row line to a lower potential VR for shading, and if the ith row and the jth column of lamp beads are short-circuited, the potential of the jth column of column line is pulled down to VR; when the (i + 1) th row is scanned, if the voltage difference between two ends of the lamp bead meets the lamp bead lighting condition, even if the row does not display data, the lamp bead corresponding to the jth column of the row can be lighted; when scanning to other rows, the problem also exists, which is expressed as that the row of the short circuit lamp bead corresponding to the jth column is bright, namely the short circuit caterpillar; therefore, VR may not be clean if set high, and may appear bright if set low.

The above problems become a problem to be solved.

Disclosure of Invention

The application provides a shadow eliminating circuit, a line driving circuit and a display screen aiming at the problems of upper ghost and short-circuit caterpillars in the display of the LED display screen.

In order to achieve the purpose, the following technical scheme is adopted in the application:

in one aspect, the present application provides a shadow elimination circuit, including: the circuit comprises an amplifier, a first transistor and a reference voltage output module;

the output end of the reference voltage output module is electrically connected with the inverting input end of the amplifier and is used for outputting a first reference voltage to the inverting input end of the amplifier when the row driving module is started and outputting a second reference voltage to the inverting input end of the amplifier when the row driving module is closed;

the non-inverting input end of the amplifier is used for being electrically connected with the output end of the row driving module, the output end of the amplifier is electrically connected with the driving end of the first transistor, and an amplified signal of a voltage difference value between the non-inverting input end and the inverting input end of the amplifier is output to the amplifier;

the drain electrode of the first transistor is used for being electrically connected with the output end of the row driving module, and the first transistor is controlled by the amplification signal to be switched on or switched off;

the first transistor is an NMOS, the source electrode of the first transistor is grounded, and the first reference voltage is a power supply voltage;

or the like, or, alternatively,

the first transistor is PMOS, the source electrode of the first transistor is connected with power voltage, and the first reference voltage is ground voltage.

The shadow eliminating circuit aims at a common-anode and common-cathode display screen, different reference voltages are output when a line driving module is started and closed, the purpose of finally controlling the on-off of a first transistor is achieved, the accurate pull-down/pull-up of the voltage of an OUT end at a proper time is finally achieved, the phenomenon of upper ghost shadow appearing in display can be effectively eliminated, and error pull-down/pull-up is avoided.

Further, the reference voltage output module is further configured to output the third reference voltage to an inverting input terminal of the amplifier after the end of the shadow elimination;

when the source electrode of the first transistor is grounded, the third reference voltage is larger than the second reference voltage; when the source electrode of the first transistor is connected with the power voltage, the third reference voltage is smaller than the second reference voltage.

And the third reference voltage is output after the shadow elimination is finished, so that the phenomenon of short-circuit caterpillars can be avoided.

Further, the reference voltage output module comprises a switch module and a voltage source module;

the switch module comprises a first switch, a second switch and a third switch;

the voltage source module comprises a first voltage source, a second voltage source and a third voltage source;

the first end of the first switch, the first end of the second switch and the first end of the third switch are respectively and sequentially electrically connected with the first voltage source, the second voltage source and the third voltage source, and the second end of the first switch, the second end of the second switch and the second end of the third switch are electrically connected with the inverting input end of the amplifier.

According to the control method and the control device, the three switch modules are arranged, and different reference voltages are output to the inverting input end of the amplifier through the on-off of the switch modules, so that the on-off of the first transistor is controlled.

Further, the time for the reference voltage output module to output the second reference voltage to the inverting input terminal of the amplifier is set to be fixed time or adjusted according to a display effect.

Further, the output voltage of the second voltage source is adjustable.

Furthermore, the shadow elimination circuit also comprises a compensation module; the compensation module is used for compensating the input offset of the amplifier.

According to the scheme, the compensation module is arranged, so that the situation that the first transistor is mistakenly started due to the input offset of the amplifier can be avoided, and the normal output of the travelling tube is ensured.

Furthermore, the shadow elimination circuit also comprises a current-limiting protection module; the current-limiting protection module is used for being electrically connected with the output end of the row driving module, the second end of the current-limiting protection module is electrically connected with the drain electrode of the first transistor, and the third end of the current-limiting protection module is electrically connected with the non-inverting input end of the amplifier.

Further, the current-limiting protection module comprises a first resistor and a second resistor; the first resistor is connected in series between a first end of the second resistor and the drain of the first transistor 102, a second end of the second resistor is used for being electrically connected with the output end of the row driving module 200, and a connection point of the first resistor and the second resistor is electrically connected with the non-inverting input end of the amplifier.

In a second aspect, the present application provides a row driving circuit, which includes a row driving module and the shadow eliminating circuit as described in the first aspect.

In a third aspect, the present application proposes a display screen comprising a row driver circuit as described in the second aspect.

Has the advantages that:

the shadow elimination circuit can effectively eliminate the upper ghost in the display of the LED display screen;

the shadow eliminating circuit can avoid the problems of mistaken opening of a first transistor caused by input offset of an amplifier and abnormal output of an OUT end of a row driving chip caused by the input offset of the amplifier;

the short-circuit caterpillar problem can be effectively eliminated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related arts, the drawings used in the description of the embodiments or the related arts will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a general structure of an LED display driver in a common anode LED display screen unit panel according to an embodiment of the present application;

fig. 2 is a schematic diagram of a row driver chip module according to an embodiment of the present disclosure;

FIG. 3 is a block diagram of a shadow elimination circuit according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a row driver chip of a common anode LED display screen according to an embodiment of the present disclosure;

FIG. 5 is a circuit diagram of a row driver chip of a common cathode LED display panel according to an embodiment of the present disclosure;

FIG. 6 is a circuit diagram of a common anode LED display screen row driver chip provided in accordance with another embodiment of the present application;

FIG. 7 is a circuit diagram of a row driver chip of a common cathode LED display panel according to another embodiment of the present application;

reference numerals are as follows: 100-a shadow elimination circuit; 200-row driving module; 101-an amplifier; 102-a first transistor; 103-a reference voltage output module; 104-a compensation module; 105-current limiting protection module.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Hereinafter, the terms "first", "second", and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In addition, the term "electrically connected" may be directly electrically connected or indirectly electrically connected through an intermediate.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Fig. 2 provides a schematic diagram of a row driver chip module according to the present application. The image elimination circuit 100 is electrically connected to the row driving module 200, and is configured to control a potential (through an OUT terminal) on a row line of a certain row when the row driving module 200 of the certain row is turned off, so as to avoid occurrence of an image ghost. The row driver module 200 may optionally include a transistor, such as a PMOS or NMOS. The OUT terminal potential can be controlled by controlling the on-off of the transistor. For example, as shown in fig. 4 to 5, when a certain row needs to be displayed, the OUT terminal voltage is controlled to be VDD (when the row transistor is an ideal switch, in practice, the OUT terminal voltage = VDD — load current switch closing internal resistance) or GND (when the row transistor is an ideal switch, in practice, the OUT terminal voltage = load current switch closing internal resistance) by closing the transistors of the row driving module 200.

For the common-anode LED display screen, when each display line is completed and the line driving module is turned off, the shadow eliminating circuit 100 pulls down the potential of the line (the potential on the row line of the line) to lower the potential on the line, so that the LED lamp of the line is not lighted when the LED lamp of the next line is displayed, thereby avoiding ghost. For a common cathode display screen, when each display line is completed and the line driving module is turned off, the shadow eliminating circuit 100 pulls up the potential of the line to increase the potential of the line, so that the LED lamps of the line cannot be lighted when the next line of LED lamps is displayed.

Referring to fig. 3, the present application provides a shadow elimination circuit 100, which includes: an amplifier 101 (AMP), a first transistor 102, and a reference voltage output module 103. An output terminal of the reference voltage output module 103 is electrically connected to an inverting input terminal (i.e., a negative input terminal) of the amplifier 101 for outputting the reference voltage VREF thereto. The reference voltage output module 103 may output different reference voltages according to the control command. Note that in this application, a outputs C to B (where C may refer to a voltage, current, or other quantity), refers to a inputs C into B or a outputs C into B. For example, it can be referred that the reference voltage output module 103 outputs a reference voltage VREF, and the inverting input terminal of the amplifier 101 receives the reference voltage VREF.

In this application, when the row driver module 200 is turned on, a first reference voltage VREF1 is output to the inverting input terminal of the amplifier 101, and when the row driver module 200 is turned off, a second reference voltage VREF2 is output to the inverting input terminal of the amplifier 101. The magnitude of the second reference voltage can be adjusted with the option of setting, i.e., VREF2 is adjustable.

The non-inverting input terminal (i.e. the positive input terminal) of the amplifier 101 is configured to be electrically connected to the output terminal (OUT) of the row driving module 200, the output terminal of the amplifier 101 is electrically connected to the driving terminal of the first transistor 102, and an amplified signal (VG) of the voltage difference between the non-inverting input terminal and the inverting input terminal of the amplifier 101 is output thereto; the drain of the first transistor 102 is used to be electrically connected to the output terminal (OUT terminal) of the row driving module 200, the source is Grounded (GND) or the power Voltage (VDD), and the first transistor 102 is controlled by the amplifying signal (VG) to be turned on or off. It will be appreciated that the non-inverting input of the amplifier 101 is the port for electrical connection to the OUT terminal of the row driver block, in effect for obtaining a signal representative of the voltage at the output of the row driver block (i.e. the potential of the row line). In practical applications, the non-inverting input terminal may be directly electrically connected to the OUT terminal (or the row line), or may be electrically connected to the OUT terminal (or the row line) through the sampling block or a subsequent protection block. Similarly, the drain of the first transistor 102 is used to electrically connect to the OUT terminal (or row line), in order to pull down/up the potential of the OUT terminal (or row line) when appropriate, and in practical applications, it may be directly connected to the OUT terminal (or row line), or electrically connected to the OUT terminal (or row line) after passing through the aforementioned sampling module or protection module.

As shown in fig. 4, the first transistor 102 is an NMOS (Negative-Metal-Oxide-Semiconductor), the source of the first transistor 102 is Grounded (GND), the first reference voltage VREF1 is a power Voltage (VDD), and corresponds to the common anode LED display screen at this time; as shown in fig. 5, the first transistor 102 is a PMOS (P-type Metal-Oxide-Semiconductor), the source of the first transistor 102 is connected to a power Voltage (VDD), and the first reference voltage VREF1 is a ground voltage (GND), which corresponds to the common cathode LED display panel.

The technical scheme that this application provided proposes respectively to sharing positive LED display screen and sharing negative LED display screen, and the ghost can be realized effectually getting rid of to export different reference voltages respectively when going drive module and opening, closing through reference voltage output module 103.

Fig. 4-5 show schematic diagrams of the shadow elimination circuit 100 applied to the common anode and common cathode LED display screens, respectively.

In the column driver chip of the common anode LED display panel in fig. 4, the column driver module 200 includes a P-type transistor PM1, which may be a PMOS transistor. The first transistor 102 is an NMOS transistor NM1, and has a grounded source (GND) and a drain electrically connected to the output terminal (OUT) of the row driving module 200. The power supply voltage VDD is connected to the source electrode of the PM1, the drain electrode of the PM1 is used as an OUT end and is electrically connected with the row line, and the potential of the row line is controlled through a control signal VGATEP.

When a certain line needs to be controlled to display, firstly, VGATEP is at a low level, PM1 is turned on, the OUT terminal is at a high level, then the constant current source driving module (column driving) is controlled to correspondingly output constant currents in columns according to the display data of the line, the LED display lamp beads of the line are lightened, and the display image of the line is displayed.

While PM1 is turned on, the reference voltage output module 103 starts outputting the first reference voltage VREF1. The amplifier 101 compares the OUT terminal voltage (specifically, the sampling voltage VDET thereof) with a first reference voltage, and outputs an amplified signal VGN of a difference between the two voltages to the driving terminal of the first transistor NM 1. Since VGN = k (VDET-VREF 1) = k (VDET-VDD) at this time, k is the amplification factor of the amplifier 101, and VDET is the voltage at the non-inverting input terminal of the amplifier 101, that is, the signal representing the voltage at the OUT terminal, that is, the sampled voltage at the OUT terminal. Since VDD is larger than or equal to VDET, NM1 does not pull down OUT voltage at the moment. Through the arrangement, the OUT end potential can not be pulled down when the row tube (such as PM 1) is started.

And after the display of the row is finished, the control signal VGATEP is high, and the PM1 is controlled to be disconnected. The reference voltage output module 103 stops outputting VREF1 (i.e., VDD) and starts outputting the second reference voltage VREF2, VGN = k (VDET — VREF 2), and when VGN > Von _ NM1, i.e., VGN is greater than the NMOS (NM 1) turn-on voltage, NM1 will turn on to pull down the OUT terminal potential to VREF2. At this time, the potential on the row line is pulled down, and no ghost image appears. Note that in the present application, VREF2< VDD, and VREF2< VREF3 (VREF 3 is described later) for the common anode case. The ideal amplification k of the amplifier 101 is infinite, VREF2< VDET, and the turn-on condition is generally satisfied.

In the common cathode LED display panel row driver chip of fig. 5, the row driver module 200 includes an N-type transistor NM2, which may be an NMOS. The first transistor 102 corresponds to a PMOS transistor PM2. The source electrode of the PM2 is connected with a power supply voltage VDD, and the drain electrode of the PM2 is electrically connected with the output end (OUT) of the row driving module 200. The source electrode of the NM2 is grounded, and the drain electrode is used as an output end and is electrically connected with the column line, the PM2 drain electrode and the equidirectional input end of the amplifier.

When a certain row needs to be controlled to display, firstly VGATEN is in a high level, NM2 is conducted, the potential of an OUT end is low, then the constant current source driving module is controlled to correspondingly output constant currents according to the display data of the row in a row, the LED display lamp beads of the row are lightened, and the display image of the row is displayed.

While NM2 is turned on, the reference voltage output module 103 starts outputting the first reference voltage VREF1. The amplifier 101 compares the OUT terminal potential (specifically, the sampling voltage VDET thereof) with the first reference voltage VREF1, and outputs an amplified signal VGP of a difference between the two to the driving terminal of the first transistor PM2.

At this time, VGP = k (VDET-VREF 1) = k (VDET-GND), and GND ≦ VDET, at which PM2 does not pull up the OUT voltage.

After the display of the row is completed, control signal VGATEN is low, NM2 is turned off. The reference voltage output module 103 stops outputting VREF1 and starts outputting the second reference voltage VREF2, VGP = k (VDET — VREF 2), and when VGP < Von _ PM2, i.e., VGP is less than PMOS (NM 1) turn-on voltage, PM2 will turn on, pulling OUT up to VREF2. Note that in this application, for the case of common cathode, VREF2> GND, and VREF2> VREF3 (VREF 3 is described later). Similarly, if the ideal amplification factor k of amplifier 101 is infinite, and VREF2> VDET, then the turn-on condition is generally satisfied.

Therefore, in the application, the OUT end potential is pulled down when the line driving module is closed for the common-anode LED display screen, and the OUT end potential is pulled up when the line driving module is closed for the common-cathode LED display screen, so that the ghost phenomenon in the display process is eliminated.

For the common-anode LED display screen shown in fig. 4, when a lamp bead is short-circuited, after the shadow elimination is finished, the potential of the column line of the column where the lamp bead is located is the second reference voltage VREF2 (VR _ DIS1 in fig. 4), if VREF2 is set to be lower, if the voltage difference between two ends of the lamp bead reaches the lamp bead on condition, each row is scanned, and the lamp bead is bright, that is, the column is normally bright. At this time, the short-circuit caterpillar phenomenon occurs.

For example, for a common-anode LED display screen, when the ith row driver is turned off, the shadow elimination circuit will pull the row line to a lower potential VR (for example, VREF 2) for shadow elimination, and if the ith row and jth column lamp beads are short-circuited, the jth column line potential will be pulled down to VR; when the (i + 1) th row is scanned, if the voltage difference between two ends of the lamp bead meets the lamp bead lighting condition, even if the row does not display data, the lamp bead corresponding to the jth column of the row can be lighted; when scanning to other rows, the problem also exists, which is represented by that the column of the short circuit lamp bead corresponding to the jth column is bright, namely, the short circuit caterpillar. Therefore, VR may not be clean if set high, and may appear bright if set low.

In some embodiments, the following method is used to eliminate short-circuit caterpillars. For example, for the case of common anode, when the ith row driving is turned off, the shadow elimination circuit will pull the row line to a lower potential VR _ DIS1 for shadow elimination, and after the upper ghost is eliminated, the shadow elimination circuit is turned off; if the lamp beads in the ith row and the jth column are short-circuited, the potential of the column line in the jth column is pulled down to VR _ DIS1; when the (i + 1) th row is scanned, the potential of the ith row line is pulled up to VRC through the parasitic capacitance coupling of the row lines when the row is opened, because the ith row shadow eliminating circuit is closed, the ith row line is pulled up and then cannot be pulled back to VR _ DIS1 by the shadow eliminating circuit, the voltage difference between two ends of the lamp bead does not meet the lamp bead lighting condition, and if the (i + 1) th row does not display data, the row corresponding to the jth column lamp bead cannot be lighted. However, this approach may introduce new ghosting if the VRC is too large.

In view of the above problem, in some embodiments of the present application, the reference voltage output module 103 of the present application is further configured to output a third reference voltage VREF3 to the inverting input terminal of the amplifier 101 after the end of the shadow elimination;

when the source of the first transistor 102 is grounded (common anode, the first transistor is NMOS), the third reference voltage VREF3 is greater than the second reference voltage VREF2; when the source of the first transistor 102 is connected to the power voltage (common cathode, the first transistor is PMOS), the third reference voltage is less than the second reference voltage VREF2.

For the common-anode condition, after the shadow elimination is finished, the reference voltage output module 103 is controlled to output a third reference voltage VREF3, and since VREF3> VREF2, NM1 does not pull down the OUT voltage; when other rows are turned on to pull the row voltage above VREF3 through capacitive coupling, NM1 will turn on, pulling OUT down to VREF3.

Specifically, when the ith row drive is closed, the shadow elimination circuit pulls the row line to a lower potential VR _ DIS1 for shadow elimination, and after the upper ghost is eliminated, the shadow elimination potential is adjusted to VR _ DIS2; if the lamp beads in the ith row and the jth column are short-circuited, the potential of the jth column line is pulled down to VR _ DIS1; when an (i + 1) th row is scanned, the potential of the ith row line is pulled up to VRC through the parasitic capacitance coupling of the row lines when the row is opened, the potential of the ith row line is pulled up, and then the ith row line is pulled back to VR _ DIS2 by the shadow elimination circuit, the voltage difference between two ends of a lamp bead does not meet the lamp bead lighting condition, and if no display data exists in the (i + 1) th row, the lamp bead corresponding to the jth column of the row cannot be lighted; setting VR _ DIS1< VR _ DIS2 (i.e., VREF3> VREF 2), no new upper ghosting is introduced when VR _ DIS2< VRC.

For the common cathode LED display screen shown in fig. 5, after the shadow is removed, the voltage at the inverting input terminal of AMP is switched to VREF3, and since VREF3< VREF2, PM2 does not pull up the OUT voltage; when other rows are started, the voltage of the row is pulled down to be lower than VREF3 through capacitive coupling, PM2 is started, and the voltage of the OUT end is pulled up to be VREF3. Therefore, the phenomenon of short-circuit caterpillar on the common-cathode LED display screen can be avoided.

In some embodiments, as shown in fig. 4-5, the reference voltage output module 103 includes a switch module and a voltage source module;

the switch module comprises a first switch S0, a second switch S1 and a third switch S2;

the voltage source module comprises a first voltage source (VDD, GND), a second voltage source (VR DIS1, the value of which can be adjusted according to the setting option, namely is adjustable), and a third voltage source (VR DIS2, the value of which is adjustable);

the first end of the first switch, the first end of the second switch, and the first end of the third switch are electrically connected to the first voltage source, the second voltage source, and the third voltage source in sequence, respectively, and the second end of the first switch, the second end of the second switch, and the second end of the third switch are electrically connected to the inverting input terminal of the amplifier 101.

Controlling S0 to be closed, other switches to be opened, and outputting the first reference voltage to the inverting input end of the amplifier 101 by the reference voltage output module 103; controlling S1 to be closed, other switches to be opened, and outputting the second reference voltage to the inverting input end of the amplifier 101 by the reference voltage output module 103; the control S2 is closed, the other switches are opened, and the reference voltage output module 103 outputs the third reference voltage to the inverting input terminal of the amplifier 101.

In some embodiments, the time for outputting the second reference voltage to the inverting input terminal of the amplifier 101 by the reference voltage output module 103 of the present application is set to be a fixed time or adjusted according to a display effect.

The closing time of the switch s1, i.e. the blanking time tdis, can be set to a fixed value or adjusted according to the display effect. The time can be controlled by delaying the closing signal (for example, when the line pipe (line driving module) is closed, a delay of 1 to 2us is made, and then tdis is1 to 2us), and can also be adjusted by adjusting the pulse width of a certain input signal.

In some embodiments, as shown in fig. 6-7, the degaussing circuit 100 further includes a compensation module 104; the compensation module 104 is used for compensating the input offset of the amplifier 101.

Referring to FIG. 4, when the row transistor is turned on, the switch s0 is closed, s1 and s2 are opened, the voltage at the negative input terminal of AMP is switched to VDD, and since VDD ≧ VDET, the OUT voltage is not pulled down by NM 1.

However, since AMP is not an ideal operational amplifier, there are input offsets VOS _ IN, VIN = VDD-VOS _ IN practice, and if VOS _ IN causes VIN = VDET, NM1 may be turned on erroneously, pulling down the OUT voltage, and disturbing the normal output of the transistors.

IN contrast, referring to fig. 6, for the line driving of the common-anode LED display screen, IN the present application, for the input offset of the operational amplifier AMP, a compensation voltage is designed IN the circuit to compensate the input offset, that is, VIN = VDD + (VOS-VOS _ IN), which ensures that VIN ≧ VDET, so that the output voltage of AMP will not erroneously start NM1, and the voltage of the line tube OUT can be normally output.

Similarly, referring to FIG. 5, for a common cathode LED display panel, theoretically, when the row tube is turned on, the switch s0 is closed, s1 and s2 are opened, the voltage at the inverting input terminal of AMP is switched to GND, and since GND is less than or equal to VDET, the OUT voltage is not pulled up by PM2.

However, since AMP is not an ideal operational amplifier, there are input offsets VOS _ IN, VIN = GND + VOS _ IN practice, and if VOS _ IN causes VIN = VDET, PM2 may be turned on by mistake, pulling up the OUT voltage, and disturbing the normal output of the transistor NM 2.

IN contrast, referring to fig. 7, IN the present application, for the offset voltage, a compensation voltage is designed IN the circuit, so that VIN = GND + (VOS _ IN-VOS), and VIN ≦ VDET is ensured, so that PM2 is not turned on by mistake by the output voltage of AMP, and the output voltage of the column transistor OUT can be output normally.

It should be noted that, IN the present application, VOS _ IN is a voltage equivalent to the input terminal of the circuit itself due to design and process reasons; by setting the compensation module 104, a compensation voltage VOS is artificially introduced to compensate the influence of VOS _ IN. VOS is essentially a voltage equivalent to the input. Which may be located at the inverting input or at the non-inverting input of the amplifier.

In some embodiments, the image erasing circuit 100 further includes a current limiting protection module 105; the current-limiting protection module 105 has a first terminal electrically connected to the output terminal of the row driving module 200, a second terminal electrically connected to the drain of the first transistor 102, and a third terminal electrically connected to the non-inverting input terminal of the amplifier 101.

Referring to fig. 4-7, the current limiting protection module 105 includes a first resistor and a second resistor; the first resistor is connected in series between a first end of the second resistor and the drain of the first transistor 102, a second end of the second resistor is used for being electrically connected with the output end (also can be considered as a row line) of the row driving module 200, and a connection point of the first resistor and the second resistor is electrically connected with the non-inverting input end of the amplifier 101 (in fig. 4 and 6, R1 is the first resistor, R2 is the second resistor; in fig. 5 and 7, R2 is the first resistor, and R1 is the second resistor).

The operation of the shadow elimination circuit of the present application is explained in detail below with reference to fig. 4 to 7.

Referring to fig. 4 and 6, fig. 4 and 6 are schematic diagrams illustrating a shadow eliminating circuit of a common-anode LED display screen. The working principle is as follows:

when the row driving transistor PM1 (row driving module) is turned on, the switch s0 is closed, the switches s1 and s2 are disconnected, the voltage of the negative input end of the AMP is switched to VDD, and the OUT voltage cannot be pulled down by the NM1 at the moment because the VDD is larger than or equal to VDET;

when the row driving transistor PM1 (row driving module) is turned off, the switch s1 is closed, s0 and s2 are opened, the voltage at the inverting input terminal of AMP is switched to VR _ DIS1, when VGN > Von _ NM1, i.e., VGN is greater than the NMOS (NM 1) turn-on voltage, NM1 is turned on, and OUT is pulled down to VR _ DIS1, where VR _ DIS1 can be adjusted by setting options.

After the shadow elimination is finished (the shadow elimination time tids can be fixed or adjusted according to the display effect), the switch s2 is closed, s0 and s1 are disconnected, the voltage of the negative input end of the AMP is switched to VR _ DIS2, and the OUT voltage cannot be pulled down by NM1 because VR _ DIS2> VR _ DIS1; when other rows are turned on to pull the row voltage above VR _ DIS2 through capacitive coupling, NM1 will turn on to pull OUT down to VR _ DIS2.

Please refer to fig. 5 and fig. 7, and fig. 5 and fig. 7 show the shadow elimination circuit of the common cathode LED display panel. The working principle is as follows:

when the flyback is started, the switch s0 is closed, the s1 and the s2 are disconnected, the voltage of the negative input end of the AMP is switched to GND, and the voltage of the OUT cannot be pulled up by the PM2 at the moment because the GND is less than or equal to VDET;

when the travelling tube is closed, the switch s1 is closed, the switch s0 and the switch s2 are opened, the voltage of the negative input end of the AMP is switched to VR _ DIS1, when VGP < Von _ PM2, namely VGP (negative value) is smaller than the opening voltage of PMOS (NM 1), PM2 is opened, the voltage of the OUT end is pulled up to VR _ DIS1, and VR _ DIS1 can be set with options for adjustment;

after the shadow elimination is finished, the switch s2 is closed, the s0 and the s1 are disconnected, the voltage of the negative input end of the AMP is switched to VR _ DIS2, and the OUT voltage cannot be pulled up by PM2 because VR _ DIS2< VR _ DIS1; when other rows are turned on to pull the row voltage down below VR _ DIS2 through capacitive coupling, PM2 will turn on, pulling OUT up to VR _ DIS2.

In a second aspect, the present application further provides a row driving circuit, which includes a row driving module 200 and the shadow eliminating circuit 100 according to the first aspect.

The non-inverting input terminal of the amplifier 101 of the image elimination circuit 100 is electrically connected to the output terminal (OUT) of the row driving module 200, and may be directly connected to the output terminal, or may be connected to the output terminal through the sampling module or the current-limiting protection module 105; similarly, the drain of the first transistor 102 is electrically connected to the output terminal (OUT) of the row driving module 200, which may be directly connected, or connected through the sampling module or the aforementioned current-limiting protection module 105. In the case that the current-limiting protection module 105 includes the aforementioned first resistor and second resistor, the first resistor and the second resistor are connected in series between the output terminal of the row driving module 200 and the drain of the first transistor 102.

In a third aspect, the present application also provides a display screen comprising a row driver circuit as described in the second aspect.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A shadow elimination circuit (100), comprising: an amplifier (101), a first transistor (102), and a reference voltage output module (103);

the output end of the reference voltage output module (103) is electrically connected with the inverting input end of the amplifier (101) and is used for outputting a first reference voltage to the inverting input end of the amplifier (101) when the row driving module (200) is turned on and outputting a second reference voltage to the inverting input end of the amplifier (101) when the row driving module (200) is turned off;

the non-inverting input end of the amplifier (101) is used for being electrically connected with the output end of the row driving module (200), the output end of the amplifier (101) is electrically connected with the driving end of the first transistor (102), and an amplified signal of a voltage difference value of the non-inverting input end and the inverting input end of the amplifier (101) is output to the amplifier;

the drain electrode of the first transistor (102) is used for being electrically connected with the output end of the row driving module (200), and the first transistor (102) is controlled by the amplifying signal to be switched on or switched off;

the first transistor (102) is an NMOS, the source electrode of the first transistor (102) is grounded, and the first reference voltage is a power supply voltage;

or the like, or a combination thereof,

the first transistor (102) is PMOS, the source electrode of the first transistor (102) is connected with a power voltage, and the first reference voltage is a ground voltage.

2. A deghosting circuit (100) according to claim 1, wherein the reference voltage output module (103) is further configured to output a third reference voltage to the inverting input of the amplifier (101) after deghosting is finished;

wherein the third reference voltage is greater than the second reference voltage when the source of the first transistor (102) is grounded; when the source of the first transistor (102) is connected with a power supply voltage, the third reference voltage is smaller than the second reference voltage.

3. A deghosting circuit (100) according to claim 2, wherein the reference voltage output module (103) comprises a switching module and a voltage source module;

the switch module comprises a first switch, a second switch and a third switch;

the first end of the first switch, the first end of the second switch and the first end of the third switch are respectively and sequentially electrically connected with the first voltage source, the second voltage source and the third voltage source, and the second end of the first switch, the second end of the second switch and the second end of the third switch are electrically connected with the inverting input end of the amplifier (101).

4. A deghosting circuit (100) according to claim 1, wherein the time for which the reference voltage output module (103) outputs the second reference voltage to the inverting input of the amplifier (101) is set to a fixed time or adjusted according to display effects.

5. A deghosting circuit (100) according to claim 3, characterized in that the output voltage of the second voltage source is adjustable.

6. A degaussing circuit (100) according to any one of claims 1-5, characterized in that the degaussing circuit (100) further comprises a compensation module (104); the compensation module (104) is used for compensating the input offset of the amplifier (101).

7. The image cancellation circuit (100) of claim 6, wherein the image cancellation circuit (100) further comprises a current limiting protection module (105); the current-limiting protection module (105) is used for being electrically connected with the output end of the row driving module (200), the second end of the current-limiting protection module is electrically connected with the drain electrode of the first transistor (102), and the third end of the current-limiting protection module is electrically connected with the non-inverting input end of the amplifier (101).

8. A deghosting circuit (100) according to claim 7, characterized in that the current limiting protection module (105) comprises a first resistor, a second resistor; the first resistor is connected in series between a first end of the second resistor and the drain electrode of the first transistor (102), a second end of the second resistor is used for being electrically connected with the output end of the row driving module (200), and a connecting point of the first resistor and the second resistor is electrically connected with the non-inverting input end of the amplifier (101).

9. A row driver circuit, characterized in that the row driver circuit comprises a row driver module (200) and a blanking circuit (100) as claimed in any one of claims 1 to 8.

10. A display screen characterized in that it comprises a row driver circuit as claimed in claim 9.