CN216979501U - Array substrate, color film substrate and liquid crystal display panel - Google Patents

Abstract

The application relates to an array substrate, a color film substrate and a liquid crystal display panel. The array substrate comprises a display area and a non-display area located on the periphery of the display area, wherein a plurality of conductive bonding pads distributed at intervals are arranged in the non-display area, each conductive bonding pad comprises a first metal layer, an insulating layer and a conductive layer which are sequentially formed on a first substrate, the first metal layer and a first public electrode located in the display area are in the same layer and are electrically connected, and a first through hole is formed between the first metal layer and the first public electrode in an area between the outer edge of the display area and at least one side of each conductive bonding pad, so that the array substrate forms a groove at the first through hole. The array substrate can prevent the alignment film liquid from being blocked in the groove before the alignment film liquid is diffused to the conductive bonding pad, so that conductive particles in the frame glue cannot penetrate the alignment film and are not well conducted with the first common electrode due to the fact that the alignment film liquid is diffused to the frame glue of the conductive bonding pad, and the problem of abnormal display is solved.

Description

Array substrate, color film substrate and liquid crystal display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a color film substrate and a liquid crystal display panel.

Background

The Liquid Crystal Display panel (LCD for short) includes an array substrate, a color filter substrate and a Liquid Crystal layer between the array substrate and the color filter substrate, which are oppositely disposed. Alignment films are respectively formed on the inner sides of the array substrate and the color film substrate and used for guiding the arrangement direction of liquid crystal molecules. In addition, the array substrate and the color film substrate are mechanically and electrically connected through the frame glue positioned in the frame area.

In order to realize the narrow frame, the distance between the display area of the liquid crystal display panel and the frame adhesive area needs to be designed to be very close, so that when the alignment film is formed by coating alignment liquid on the display area, the alignment liquid has fluidity, and the stop line of the alignment liquid is not easy to control, so that the alignment film is easy to flow into the frame adhesive area, and conductive particles in frame adhesive hardly penetrate through an alignment film layer and cannot conduct an array substrate and a color film substrate, thereby causing the problems of poor conduction of the frame adhesive and abnormal display of the liquid crystal display panel.

Disclosure of Invention

The array substrate can enable alignment film liquid to be blocked in the groove before the alignment film liquid is diffused to the conductive bonding pad, so that the alignment film liquid is prevented from being diffused to frame glue of the conductive bonding pad, conductive particles in the frame glue cannot penetrate the alignment film and are not well conducted with the first common electrode, and the problem of abnormal display is solved.

In a first aspect, an embodiment of the present application provides an array substrate, including a display area and a non-display area located at a periphery of the display area, where a plurality of conductive pads are disposed in the non-display area, where the conductive pads include a first metal layer, an insulating layer, and a conductive layer that are sequentially formed on a first substrate, the first metal layer is electrically connected to a first common electrode located in the display area on the same layer, and a first via hole is formed between the first metal layer and the first common electrode in an area between an outer edge of the display area and at least one side of the conductive pad, so that the array substrate forms a groove at the first via hole.

In one possible embodiment, the maximum outer diameter dimension of the first via is 30 μm to 100 μm.

In one possible implementation, the number of the first vias is multiple, and the multiple first vias are distributed at intervals along at least one side of the conductive pad.

In one possible embodiment, the insulating layer includes a gate insulating layer on the first metal layer and a passivation layer on the gate insulating layer, and the gate insulating layer and/or the passivation layer has a thickness corresponding to the first via hole that is smaller than that of the remaining positions.

In one possible embodiment, the gate insulating layer and/or the passivation layer is formed with a second via hole corresponding to the first via hole.

In one possible embodiment, the insulating layer includes a gate insulating layer on the first metal layer and a passivation layer on the gate insulating layer, and the passivation layer is gradually thinned in a direction of the non-display region toward the display region corresponding to the thickness of the first via hole.

In one possible embodiment, the gate insulating layer and/or the passivation layer is formed with a stepped hole corresponding to the first via hole.

In a possible implementation manner, the array substrate further includes a first alignment film and a sealant, the first alignment film is located on a side of the conductive layer away from the first substrate, conductive particles are formed in the sealant, one end of each conductive particle is electrically connected to the first common electrode through the first alignment film, and the other end of each conductive particle is electrically connected to the second common electrode through a second alignment film on the side of the color film of the liquid crystal display panel.

In a second aspect, an embodiment of the present application provides a color filter substrate, which includes a second substrate and a second common electrode located on the second substrate, where a spacer protruding toward the array substrate and matching with a groove of the array substrate is disposed on the second substrate.

In a third aspect, an embodiment of the present application further provides a liquid crystal display panel, including the array substrate as described above; the color film substrate is arranged opposite to the array substrate; and the liquid crystal layer is arranged between the array substrate and the color film substrate.

According to the array substrate, the color film substrate and the liquid crystal display panel provided by the embodiment of the application, the first via hole is formed between the first metal layer and the first common electrode in the area between the outer edge of the display area and at least one side of the conductive bonding pad, so that the array substrate forms the groove at the first via hole, the alignment film liquid can be blocked in the groove before being diffused to the conductive bonding pad, the alignment film liquid is prevented from being diffused to the frame glue of the conductive bonding pad, conductive particles in the frame glue cannot penetrate the alignment film and are not well conducted with the first common electrode, and the problem of abnormal display is solved.

Drawings

Features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are given like reference numerals. The drawings are not necessarily to scale, they are merely intended to illustrate the relative positions of the layers, and the thicknesses of some portions are exaggerated for ease of understanding, and the thicknesses in the drawings do not represent the proportional relationship of the actual thicknesses.

Fig. 1 is a schematic diagram illustrating a top view structure of a liquid crystal display panel according to an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view of the liquid crystal display panel of FIG. 1 taken along the direction B-B;

fig. 3 is a schematic structural diagram of a first array substrate according to a first embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a second array substrate according to the first embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a third array substrate according to the first embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a fourth array substrate according to the first embodiment of the present application;

fig. 7 is a schematic structural diagram illustrating an array substrate according to a second embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another array substrate according to a second embodiment of the present disclosure.

Description of reference numerals:

1. an array substrate; AA. A display area; NA, non-display area;

10. a conductive pad; 11. a first substrate base plate; G. a groove; h1, a first via; h2, a second via; h3, stepped bore;

12. a first metal layer; 121. a first common electrode;

13. an insulating layer; 13a, a gate insulating layer; 13b, a passivation layer;

14. a conductive layer; 15. a first alignment film;

16. frame glue; 161. conductive particles;

2. a color film substrate; 21. a second substrate base plate; s, a spacer; 22. a second common electrode; 23. a second alignment film; 3. and a liquid crystal layer.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a schematic top view of a liquid crystal display panel according to an embodiment of the present disclosure, and fig. 2 is a cross-sectional view of the liquid crystal display panel in fig. 1 along a direction B-B.

Referring to fig. 1 and 2, an embodiment of the present application provides a liquid crystal display panel, including: the liquid crystal display panel comprises an array substrate 1, a color film substrate 2 arranged opposite to the array substrate 1 and a liquid crystal layer 3 arranged between the array substrate 1 and the color film substrate 2. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, which are typically rod-shaped and both fluid like a liquid and have certain crystalline characteristics. When liquid crystal molecules are placed in an electric field, their alignment direction changes according to the change of the electric field.

The liquid crystal display panel comprises a display area AA and a non-display area NA positioned at the periphery of the display area AA, wherein the non-display area NA of the array substrate 1 is provided with a plurality of conductive bonding pads 10 distributed at intervals. Optionally, the array substrate 1 and the color film substrate 2 are both of a rectangular structure, the length of the array substrate 1 is equal to the length of the color film substrate 2, the width of the array substrate 1 is greater than the width of the color film substrate 2, and a driving circuit and a flexible circuit board are disposed on a portion of the array substrate 1 in the width direction, which is greater than the color film substrate 2. A plurality of conductive pads 10 are spaced apart in the long side direction of the array substrate 1 in the non-display area NA.

In a box-forming process of a liquid crystal display panel, a first alignment film 15 and a second alignment film 23 are generally prepared on the opposite surfaces of an array substrate 1 and a color film substrate 2, respectively, the first alignment film 15 and the second alignment film 23 are used for limiting the orientation of liquid crystal molecules in a liquid crystal layer 3, then a plurality of conductive pads 10 of the array substrate 1 are coated with a sealed frame glue 16 and liquid crystal is dripped in, then the array substrate 1 and the color film substrate 2 are attached in a vacuum state, and finally the frame glue 16 is cured through ultraviolet irradiation, so that the packaging of the array substrate 1 and the color film substrate 2 is completed.

The first alignment film 15 and the second alignment film 23 have fluidity, and the viscosity is reduced by adding a solvent to a resin material such as polyimide. Taking the manufacturing process of the first alignment film 15 as an example, there are two main manufacturing methods of the first alignment film 15, one is to transfer the first alignment film 15 by using a Printing plate, and the other is to manufacture the first alignment film 15 by an Inkjet Printing (Inkjet Printing) coating method. Taking the inkjet printing method as an example, firstly, the pattern of the first alignment film 15 is inputted into a computer, then the first alignment film 15 solution is sprayed onto the array substrate 1 through a nozzle, and the first alignment film 15 is formed after curing.

As shown in fig. 2, the color filter substrate 2 includes a second common electrode 22 and a second alignment film 23 sequentially formed on the second substrate 21, conductive particles 161 are formed in the sealant 16, the conductive particles 161 are accommodated in the via holes of the conductive pads 10, one end of each conductive particle 161 is electrically connected to the first common electrode 121 through the first alignment film 15, and the other end of each conductive particle 161 is electrically connected to the second common electrode 22 through the second alignment film 23 on one side of the color filter substrate 2.

In order to realize a narrow frame, the distance between the display area AA of the array substrate 1 and the sealant 16 needs to be designed to be very close. In order to overcome the problems of poor film forming property and uneven film thickness of the first alignment film 15 at the edge of the display area AA, the first alignment film 15 liquid may be respectively coated on the display area AA and the non-display area NA. Since the first alignment film 15 liquid has fluidity, the stop line thereof is not well controlled and easily flows to the non-display area NA, resulting in a thick first alignment film 15 being accumulated on the conductive pad 10. The conductive particles 161 in the sealant 16 are difficult to penetrate the film layer of the first alignment film 15 and cannot conduct the array substrate 1 and the color film substrate 2, so that the problems of poor conduction of the sealant 16 and abnormal display of the display panel occur.

Therefore, the embodiment of the application provides an array substrate 1, which can block the liquid in the first alignment film 15 in the groove before the liquid is diffused to the conductive pad 10, so as to prevent the conductive particles 161 in the sealant 16 from failing to penetrate the first alignment film 15 and being poorly conducted with the first common electrode 121 during the accumulation of the liquid in the first alignment film 15 in the conductive pad 10, thereby improving the problem of abnormal display.

The following describes in detail a specific structure of an array substrate provided in embodiments of the present application with reference to the accompanying drawings.

First embodiment

Fig. 3 shows a schematic structural diagram of a first array substrate provided in the first embodiment of the present application, fig. 4 shows a schematic structural diagram of a second array substrate provided in the first embodiment of the present application, fig. 5 shows a schematic structural diagram of a third array substrate provided in the first embodiment of the present application, and fig. 6 shows a schematic structural diagram of a fourth array substrate provided in the first embodiment of the present application.

As shown in fig. 2 and fig. 3, a first embodiment of the present application provides an array substrate 1, including a display area AA and a non-display area NA located at a periphery of the display area AA, wherein a plurality of conductive pads 10 are disposed in the non-display area NA at intervals, the conductive pads 10 include a first metal layer 12, an insulating layer 13 and a conductive layer 14 sequentially formed on a first substrate 11, and the first metal layer 12 is in the same layer as and electrically connected to a first common electrode 121 located in the display area AA.

Wherein, a first via hole H1 is formed between the first metal layer 12 and the first common electrode 121 in an area between an outer edge of the display area AA and at least one side of the conductive pad 10, so that the array substrate 1 forms a groove G at the first via hole H1.

In the display area AA, the array substrate 1 includes a first metal layer 12, a gate insulating layer, a semiconductor layer, a second metal layer, an interlayer insulating layer, a conductive layer 14 and a first alignment film 15 sequentially formed on a first substrate 11, wherein the first metal layer 12 is formed with a scan line, a gate electrode of a thin film transistor and a first common electrode 121, and the second metal layer is formed with a data line, a source electrode of the thin film transistor and a drain electrode of the thin film transistor. The conductive layer 14 may include Indium Tin Oxide (ITO), the conductive layer 14 is formed with a pixel electrode, one of the source electrode and the drain electrode is electrically connected to the data line, and the other of the source electrode and the drain electrode is electrically connected to the pixel electrode.

In order to simplify the manufacturing process, the film layers of the conductive pads 10 in the non-display area NA of the array substrate 1 are simultaneously manufactured with the display area AA. The first metal layer 12 of the conductive pad 10 is in the same layer as and electrically connected to the first common electrode 121, the insulating layer 13 of the conductive pad 10 may include a gate insulating layer 13a and an interlayer insulating layer 13b, and the conductive layer 14 may be electrically connected to the first common electrode 121 by providing a via 13 on the insulating layer 13.

Alternatively, the material of the first metal layer 12 of the conductive pad 10 and the first common electrode 121 may be titanium aluminum titanium (TiAlTi), for example, a titanium film with a thickness of 100nm, an aluminum film with a thickness of 300nm, and a titanium film with a thickness of 50nm are sequentially stacked. A first via H1 is formed between the first metal layer 12 of the conductive pad 10 and the first common electrode 121 on the outer edge of the display area AA, so as to reduce electrostatic charges in the circuit and prevent large current from being generated due to discharge of a large amount of electrostatic charges to damage the circuit; on the other hand, the insulating layer 13 on the first metal layer 12 may be formed with a groove G at the first via H1.

Therefore, the liquid of the first alignment film 15 on the conductive layer 14 can be blocked in the groove G before diffusing from the outer edge of the display area AA to the conductive pad 10, so as to avoid accumulation of the liquid of the first alignment film 15 at the conductive pad 10, which results in poor conduction between the conductive particles 161 in the sealant 16 and the first common electrode 121 because the conductive particles 161 cannot penetrate the first alignment film 15, thereby improving the problem of abnormal display.

In the array substrate 1 provided in the embodiment of the present application, the first via hole H1 is disposed between the first metal layer 12 and the first common electrode 121 in the region between the outer edge of the display area AA and at least one side of the conductive pad 10, so that the array substrate 1 forms the groove G at the first via hole H1, and thus the liquid of the first alignment film 15 is blocked in the groove G before diffusing to the conductive pad 10, and the liquid of the first alignment film 15 is prevented from diffusing to the sealant 16 of the conductive pad 10, so that the conductive particles 161 in the sealant 16 cannot penetrate the first alignment film 15 and are poorly conducted with the first common electrode 121, thereby improving the problem of abnormal display.

In some embodiments, the maximum outer diameter dimension D of the first via H1 is between 30 μm and 100 μm. The shape of the first via H1 may be a circle, a rectangle, or any other shape, and the diameter of the circumscribed circle is the maximum outer diameter D of the first via H1. On the premise of not affecting the electrical connection between the first metal layer 12 of the conductive pad 10 and the first common electrode 121, the larger the size of the first via hole H1 is, the larger the groove G formed at the first via hole H1 by the insulating layer 13 is, the more the liquid of the first alignment film 15 can be contained, and the overflow of the liquid of the first alignment film 15 in the groove G is prevented.

Further, the number of the first vias H1 is multiple, and a plurality of the first vias H1 are spaced along at least one side of the conductive pad 10. Alternatively, the conductive pads 10 have a rectangular structure, and one side of the conductive pads facing the display area AA and two sides between adjacent conductive pads 10 are provided with the first via holes H1, so that the liquid of the first alignment film 15 diffusing from the outer edge of the display area AA and the liquid of the first alignment film 15 entering the non-display area NA can be blocked in the groove G, and the liquid of the first alignment film 15 is prevented from accumulating at the conductive pads 10.

In some embodiments, the insulating layer 13 includes a gate insulating layer 13a on the first metal layer 12 and a passivation layer 13b on the gate insulating layer 13a, and the thickness of the gate insulating layer 13a or the passivation layer 13b corresponding to the first via H1 is less than that of the remaining positions.

Alternatively, the material of the gate insulating layer 13a includes, for example, SiO₂Etc., and the material of the passivation layer 13b includes, for example, an inorganic film such as SiN. In one example, as shown in fig. 4, the passivation layer 13b has a thickness corresponding to the first via H1 that is less than the thickness at the remaining positions. In another example, the thickness of the gate insulating layer 13a corresponding to the first via hole H1 is smaller than that at the remaining position, so that the depth of the groove G can be increased, the groove G can accommodate more liquid of the first alignment film 15, and the liquid of the first alignment film 15 is prevented from overflowing in the groove G.

In other embodiments, as shown in fig. 5, the thickness of the gate insulating layer 13a and the passivation layer 13b corresponding to the first via hole H1 may be smaller than that of the rest positions, so as to further increase the depth of the groove G, prevent the liquid in the first alignment film 15 from overflowing in the groove G, and prevent the liquid in the first alignment film 15 from accumulating at the conductive pad 10.

In some embodiments, the gate insulating layer 13a and/or the passivation layer 13b are formed with a second via H2 corresponding to the first via H1.

In one example, as shown in fig. 6, the passivation layer 13b is formed with a second via hole H2 corresponding to the first via hole H1, i.e., the passivation layer 13b is broken at the first via hole H1, so that the depth of the groove G may be further increased and the first alignment film 15 liquid entering the groove G is in direct contact with the gate insulating layer 13 a. In this way, the first alignment film 15 liquid diffused from the outer edge of the display area AA and the first alignment film 15 liquid entering the non-display area NA are blocked in the groove G, preventing the first alignment film 15 liquid from accumulating at the conductive pad 10.

In another example, the gate insulating layer 13a is formed with a second via hole H2 corresponding to the first via hole H1, and the first alignment film 15 liquid entering the groove G is in direct contact with the passivation layer 13 b. In another example, the gate insulating layer 13a and the passivation layer 13b are formed with a second via hole H2 corresponding to the first via hole H1, and the first alignment film 15 liquid entering the groove G is in direct contact with the first substrate 11. Since the depth of the groove G is increased, the first alignment film 15 liquid diffused from the outer edge of the display area AA and the first alignment film 15 liquid entering the non-display area NA are blocked in the groove G, preventing the first alignment film 15 liquid from being accumulated at the conductive pad 10.

Second embodiment

Fig. 7 shows a schematic structural diagram of an array substrate provided in the second embodiment of the present application, and fig. 8 shows a schematic structural diagram of another array substrate provided in the second embodiment of the present application.

The second embodiment of the present application also provides an array substrate 1, which has a similar structure to the array substrate 1 provided in the first embodiment, except that the shape of the groove G is different.

Specifically, the insulating layer 13 includes a gate insulating layer 13a on the first metal layer 12 and a passivation layer 13b on the gate insulating layer 13a, and the passivation layer 13b is gradually thinned in a direction in which the non-display area NA points to the display area AA in correspondence with the thickness of the first via hole H1.

The passivation layer 13b may form a tapered groove or an arc-shaped groove corresponding to the first via hole H1, so that the depth of the groove G is gradually deepened along a direction from the non-display area NA to the display area AA, thereby increasing climbing resistance of the liquid in the groove G of the first alignment film 15, preventing the liquid in the first alignment film 15 from overflowing from the groove G, and avoiding the liquid in the first alignment film 15 from accumulating at the conductive pad 10.

In one example, as shown in fig. 7, the passivation layer 13b is formed with a stepped hole H3 corresponding to the first via H1. The design of the step hole H3 makes the groove G of the array substrate 1 be in a step shape, so as to increase the climbing resistance of the first alignment film 15 liquid on the inner side wall of the groove G, and the more the steps are, the greater the climbing resistance is, preventing the first alignment film 15 liquid from overflowing from the groove G, and avoiding the first alignment film 15 liquid from accumulating at the conductive pad 10. In addition, compared with the tapered surface groove or the arc-shaped groove, the stepped hole H3 can simplify the manufacturing process and facilitate the preparation and processing.

In another example, as shown in fig. 8, a stepped hole H3 is formed in the gate insulating layer 13a corresponding to the first via hole H1, so that the groove G of the array substrate 1 is stepped, and thus the climbing resistance of the liquid in the first alignment film 15 on the inner side wall of the groove G can be increased, and the larger the number of steps, the larger the climbing resistance, the liquid in the first alignment film 15 is prevented from overflowing from the groove G, and the liquid in the first alignment film 15 is prevented from accumulating at the conductive pad 10. In addition, compared with the tapered surface groove or the arc-shaped groove, the stepped hole H3 can simplify the manufacturing process and facilitate the manufacturing process. .

On the other hand, as shown in fig. 2, an embodiment of the present application further provides a color filter substrate 2, which includes a second substrate 21, a second common electrode 22 located on the second substrate 21, and a second alignment film 23 located on the second common electrode 22, where the second substrate 21 is provided with a spacer S protruding toward the array substrate 1 and matching with the groove G of the array substrate 1.

The number of the spacers S is equal to that of the grooves G, and the spacers S correspond to and are mutually nested and matched with each other, so that the spacers S can be used for blocking the liquid of the second alignment film 23 coated on one side of the color film substrate 2 from flowing to the sealant 16 of the non-display area NA, and the situation that the sealing property between the array substrate 1 and the color film substrate 2 is damaged, and further, the color of the periphery of the liquid crystal display panel is uneven or speckles appear is avoided.

It can be understood that the technical solution of the array substrate 1 provided In the embodiments of the present application can be widely applied to various liquid crystal display panels, such as TN (Twisted Nematic) display panel, IPS (In-plane switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel.

It should be readily understood that "on … …", "above … …" and "above … …" in this application should be interpreted in the broadest sense such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above … …" or "above … …" includes not only the meaning of "above something" or "above", but also includes the meaning of "above" or "above" with no intervening features or layers in between (i.e., directly on something).

The term "substrate base" as used herein refers to a material upon which subsequent layers of material are added. The substrate base plate itself may be patterned. The material added atop the substrate base may be patterned or may remain unpatterned. Further, the base substrate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically, and/or along a tapered surface. The base substrate may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. An array substrate comprises a display area and a non-display area positioned at the periphery of the display area, wherein a plurality of conductive bonding pads are arranged in the non-display area at intervals, each conductive bonding pad comprises a first metal layer, an insulating layer and a conductive layer which are sequentially formed on a first substrate, the first metal layer and a first common electrode positioned in the display area are in the same layer and are electrically connected, and the array substrate is characterized in that,

and a first through hole is formed between the first metal layer and the first common electrode in an area between the outer edge of the display area and at least one side of the conductive pad, so that the array substrate forms a groove at the first through hole.

2. The array substrate of claim 1, wherein the first via has a maximum outer diameter dimension of 30 μm to 100 μm.

3. The array substrate of claim 1, wherein the number of the first vias is multiple, and the multiple first vias are distributed at intervals along at least one side of the conductive pad.

4. The array substrate of claim 1, wherein the insulating layer comprises a gate insulating layer on the first metal layer and a passivation layer on the gate insulating layer, and the thickness of the gate insulating layer and/or the passivation layer corresponding to the first via hole is smaller than that of the rest positions.

5. The array substrate of claim 4, wherein the gate insulating layer and/or the passivation layer is formed with a second via hole corresponding to the first via hole.

6. The array substrate of claim 1, wherein the insulating layer comprises a gate insulating layer on the first metal layer and a passivation layer on the gate insulating layer, and the passivation layer is gradually thinned along a direction of the non-display region toward the display region corresponding to the thickness of the first via hole.

7. The array substrate of claim 6, wherein the gate insulating layer and/or the passivation layer are formed with a stepped hole corresponding to the first via hole.

8. The array substrate of claim 1, further comprising a first alignment film and a sealant, wherein the first alignment film is located on a side of the conductive layer away from the first substrate, conductive particles are formed in the sealant, one end of each conductive particle is electrically connected to the first common electrode through the first alignment film, and the other end of each conductive particle is electrically connected to the second common electrode through a second alignment film on a side of the color film substrate.

9. A color filter substrate arranged opposite to the array substrate according to any one of claims 1 to 8, wherein the color filter substrate comprises a second substrate and a second common electrode on the second substrate, and the second substrate is provided with a spacer protruding toward the array substrate and engaged with the groove of the array substrate.

10. A liquid crystal display panel, comprising:

an array substrate according to any one of claims 1 to 8;

the color filter substrate according to claim 9, disposed opposite to the array substrate;

and the liquid crystal layer is arranged between the array substrate and the color film substrate.

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