CN216873174U - Self-power-off reset circuit - Google Patents

Abstract

The utility model relates to a self-power-off reset circuit, which comprises a power supply module, a delay control module and a controller, wherein the delay control module is electrically connected with the power supply module; the power supply module is used for providing starting voltage for a rear-stage circuit, the delay control circuit is used for controlling the power supply module to be turned on or turned off, and the controller is used for outputting a corresponding power-off reset signal or power-on signal to the delay control circuit. The power-off reset circuit is simple in structure, can perform power-off reset on the system per se without human intervention, is controllable in power-off time, ensures the reliability of the reset function, and meets the actual application requirements.

Description

Self-power-off reset circuit

Technical Field

The utility model relates to the technical field of embedded electronic circuit design, in particular to a self-power-off reset circuit.

Background

As is well known, the current electronic products are usually provided with a reset circuit, and when a problem occurs in a circuit system of the product or the circuit needs to be reset under certain conditions, the reset circuit can be reset to restart the operation of the product after the reset circuit is reset. The general reset circuit can reset by using a key, a PMIC and a watchdog chip, and the input power supply of the product is directly disconnected and then turned on, so that the whole circuit system of the product is powered on again for resetting.

However, when the key is used for resetting, a hole needs to be formed in the shell of the product to reserve the key position, and the product needs to be placed in a place touched by the extending hand; when the PMIC is used to manage the reset circuit, a key or another controller (such as an MCU) is also required to perform the reset operation; for products without a power-off switch, such as a 360-degree panoramic controller, the operation that the input power supply of the product is directly disconnected to reset the whole circuit system of the product can only be realized by pulling out a power line, the 360-degree panoramic controller arranged at a hidden part of an automobile is very inconvenient, and the use experience of the product is not good.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems, an object of the present invention is to provide a self-power-off reset circuit, which has a simple structure, can perform power-off reset on itself without human intervention, has controllable power-off time, and ensures the reliability of the reset function.

A self-power-off reset circuit comprises a power supply module, a delay control module electrically connected with the power supply module and a controller electrically connected with the delay control module; the power supply module is used for providing starting voltage for a rear-stage circuit, the delay control circuit is used for controlling the power supply module to be turned on or turned off, and the controller is used for outputting a corresponding power-off reset signal or power-on signal to the delay control circuit.

In addition, the self-power-off reset circuit provided by the utility model can also have the following additional technical characteristics:

furthermore, the power supply module comprises a power supply chip, and a voltage division circuit and a bootstrap circuit which are respectively electrically connected with the power supply chip; the power chip comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin.

Further, the voltage division circuit comprises a first resistor and a second resistor; the first end of the first resistor is electrically connected with a power interface, a node formed by the second end of the first resistor and the first end of the second resistor is electrically connected with the third pin of the power chip, and the second end of the second resistor is grounded.

Further, the bootstrap circuit includes a third resistor and a first capacitor, a first end of the third resistor is electrically connected to the fourth pin of the power chip, a second end of the third resistor is electrically connected to the left electrode plate of the first capacitor, and the right electrode plate of the first capacitor is electrically connected to a power inductor.

Furthermore, the delay control module comprises a switch circuit, a first delay switch circuit electrically connected with the switch circuit, and a second delay switch circuit electrically connected with the first delay switch circuit; the switch circuit is used for receiving the power-off reset signal or the power-on signal output by the controller and transmitting the power-off reset signal or the power-on signal to the first delay switch circuit, the first delay switch circuit is used for transmitting the received power-off reset signal or the power-on signal to the second delay switch circuit after delaying, and the second delay switch circuit is used for transmitting the delayed power-off reset signal or the delayed power-on signal to the power supply module.

Further, the switch circuit comprises an eighth resistor, a ninth resistor and a third triode; a node formed by the second end of the eighth resistor and the first end of the ninth resistor is electrically connected to the first end of the third triode, the first end of the eighth resistor is electrically connected to the controller, and a node formed by the second end of the ninth resistor and the second end of the third triode is grounded.

Further, the first delay switch circuit comprises a fourth resistor, a second capacitor, a fifth resistor and a first triode; the fourth resistor is connected in parallel with the second capacitor, an upper pole plate of the second capacitor is electrically connected with a second end of the first triode, a lower pole plate of the second capacitor is electrically connected with a node formed by a third end of the third triode and a second end of the fifth resistor, and a first end of the fifth resistor is electrically connected with a first end of the first triode.

Further, the second delay switch circuit comprises a third capacitor, a sixth resistor, a seventh resistor and a second MOS transistor; a node formed by the second end of the sixth resistor and the first end of the seventh resistor is electrically connected with the first end of the second MOS transistor, the second end of the seventh resistor is grounded, the first end of the sixth resistor is electrically connected with a node formed by the first triode and the upper electrode plate of the third capacitor, the lower electrode plate of the third capacitor is grounded, the second end of the second MOS transistor is grounded, and the third end of the second MOS transistor is electrically connected with the third pin of the power chip.

Further, the delay time of the first delay circuit and the second delay circuit is:

wherein t is the time required for the voltage on the capacitor in the first delay circuit or the second delay circuit to discharge to Vt, R is the total resistance value in the first delay circuit or the second delay circuit, C is the total capacitance value in the first delay circuit or the second delay circuit, VCC is the initial voltage on the capacitor in the first delay circuit or the second delay circuit, and Vt is the voltage value on the capacitor in the first delay circuit or the second delay circuit after t time.

Furthermore, when the power supply is powered on, the controller outputs a low level to control the third end and the second end of the second MOS tube to be not conducted, the third pin of the power supply chip is not grounded, and the first resistor and the second resistor are connected with the third pin of the power supply chip after voltage division to provide starting voltage for a rear-stage circuit;

when the power is off and reset, the controller outputs a high level to the eighth resistor, the third end and the second end of the second MOS tube are controlled to be conducted and grounded through the third triode, the fifth resistor, the first triode, the third capacitor and the sixth resistor, the third end of the second MOS tube is connected with the third pin of the power chip, and the starting voltage provided for the rear-stage circuit is turned off in a delayed mode.

The self-power-off reset circuit provided by the utility model comprises a power supply module, a delay control module electrically connected with the power supply module and a controller electrically connected with the delay control module; the power supply module is used for providing starting voltage for a rear-stage circuit, the delay control circuit is used for controlling the power supply module to be turned on or turned off, and the controller is used for outputting a corresponding power-off reset signal or power-on signal to the delay control circuit. The power-off reset circuit is simple in structure, can perform power-off reset on the system per se without human intervention, is controllable in power-off time, ensures the reliability of the reset function, and meets the actual application requirements.

Drawings

Fig. 1 is a block diagram of a self-power-off reset circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a detailed structure of the delay control module shown in FIG. 1;

fig. 3 is a circuit diagram of a self-power-off reset circuit according to an embodiment of the present invention.

The following detailed description will further illustrate the utility model in conjunction with the above-described figures.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the utility model are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and similar expressions are used for the purpose of illustration only and do not indicate or imply that the apparatus or components referred to must be oriented, constructed and operated in a particular orientation and are not to be construed as limiting the utility model.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1 to fig. 3, based on the above problems, an embodiment of the present invention discloses a self-power-off reset circuit, which includes a power supply module 10, a delay control module 20 electrically connected to the power supply module 10, and a controller 30 electrically connected to the delay control module 20.

Specifically, the power supply module 10 is configured to provide a start voltage to a post-stage circuit, the delay control circuit 20 is configured to control the power supply module 10 to be turned on or off, and the controller 30 is configured to output a corresponding power-off reset signal or a power-on signal to the delay control circuit 20. Wherein the controller 30 is an MCU controller.

Further, the power supply module 10 includes a power chip U1, and a voltage divider circuit and a bootstrap circuit electrically connected to the power chip U1, respectively. The power chip U1 includes a first pin 1, a second pin 2, a third pin 3, a fourth pin 4, a fifth pin 5, a sixth pin 6, a seventh pin 7, and an eighth pin 8. The seventh pin 7 of the power chip U1 is electrically connected to the power interface (12V). The power supply comprises a power supply chip, a power supply chip and a power supply chip, wherein a first pin of the power supply chip is FB, a second pin of the power supply chip is VCC, a third pin of the power supply chip is EN, a fourth pin of the power supply chip is BST, a fifth pin of the power supply chip is GND, a sixth pin of the power supply chip is SW, a seventh pin of the power supply chip is VIN, and an eighth pin of the power supply chip is PG.

The voltage divider circuit comprises a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is electrically connected with a power interface (12V), a node formed by the second end of the first resistor R1 and the first end of the second resistor R2 is electrically connected with the third pin 3 of the power chip U1, and the second end of the second resistor R2 is grounded. In this embodiment, the first end and the second end of the resistor are defined from top to bottom and from left to right.

The bootstrap circuit includes a third resistor R3 and a first capacitor C1. The first end of the third resistor R3 is electrically connected with the fourth pin 4 of the power chip U1, the second end of the third resistor R3 is electrically connected with the left pole plate of the first capacitor C1, the right pole plate of the first capacitor C1 is electrically connected with a power inductor, and the start voltage AVM-VDD is provided for the rear-stage circuit.

It can be understood that, when the self-power-off reset circuit product is connected to a 12V power supply, the 12V power supply divides the voltage by resistors R1 and R2 and turns on the power chip U1 (the 3-pin EN function of the U1 is to turn on/off the power chip, the output of the power chip is turned off when the 3-pin voltage is 0V, and the output voltage of the power chip is turned on when the 3-pin voltage is greater than 2V), and the U1 can output the voltage AVM-VDD with a corresponding value to be supplied to the product rear-stage circuit.

Specifically, the delay control module 20 includes a switch circuit 21, a first delay switch circuit 22 electrically connected to the switch circuit 21, and a second delay switch circuit 23 electrically connected to the first delay switch circuit 22. The switch circuit 21 is configured to receive a power-off reset signal or a power-on signal output by the controller 30 and transmit the power-off reset signal or the power-on signal to the first delay switch circuit 22, the first delay switch circuit 22 is configured to transmit the received power-off reset signal or the power-on signal to the second delay switch circuit 23 after delaying the power-off reset signal or the power-on signal, and the second delay switch circuit 23 is configured to transmit the delayed power-off reset signal or the power-on signal to the power supply module 10.

Further, the switch circuit 21 includes an eighth resistor R8, a ninth resistor R9, and a third transistor Q3. A node formed by the second end of the eighth resistor R8 and the first end of the ninth resistor R9 is electrically connected to the first end 1 of the third transistor Q3, the first end of the eighth resistor R8 is electrically connected to the controller 10, and a node formed by the second end of the ninth resistor R9 and the second end 2 of the third transistor Q3 is grounded.

Further, the first delay switch circuit 22 includes a fourth resistor R4, a second capacitor C2, a fifth resistor R5, and a first transistor Q1. The fourth resistor R4 is connected in parallel to the second capacitor C2, an upper plate of the second capacitor C2 is electrically connected to the second end 2 of the first transistor Q1, a lower plate of the second capacitor C2 is electrically connected to a node formed by the third end 3 of the third transistor Q3 and the second end of the fifth resistor R5, and a first end of the fifth resistor R5 is electrically connected to the first end 1 of the first transistor Q1.

Further, the second delay switch circuit 23 includes a third capacitor C3, a sixth resistor R6, a seventh resistor R7, and a second MOS transistor Q2. A node formed by the second end of the sixth resistor R6 and the first end of the seventh resistor R7 is electrically connected to the first end of the second MOS transistor Q2, the second end of the seventh resistor R7 is grounded, the first end of the sixth resistor R6 is electrically connected to a node formed by the first triode Q1 and the upper plate of the third capacitor C3, the lower plate of the third capacitor C3 is grounded, the second end 2 of the second MOS transistor Q2 is grounded, and the third end 3 of the second MOS transistor Q2 is electrically connected to the third pin 3 of the power chip U1.

Specifically, during power-on, the controller 10 outputs a low level to the eighth resistor R8, the third terminal 3 and the second terminal 2 of the second MOS transistor Q2 are controlled to be non-conductive by the third triode Q3, the fifth resistor R5, the first triode Q1, the third capacitor C3, and the sixth resistor R6, and the third terminal 3 of the second MOS transistor Q2 is connected to the third pin 3 of the power chip U1, so that the pin 3 voltage of the U1 is kept greater than 2V, so that the U1 outputs the AVM-VDD voltage, and provides the start voltage to the rear-stage circuit. When the power is off and reset, the controller 10 outputs a high level to the eighth resistor R8, the third transistor Q3, the fifth resistor R5, the first transistor Q1, the third capacitor C3, and the sixth resistor R6 control the third terminal 3 and the second terminal 2 of the second MOS transistor Q2 to be conducted and grounded, and the third terminal 3 of the second MOS transistor Q2 is connected to the third pin 3 of the power chip U1, so that the pin voltage of the power chip U1 becomes 0V, that is, the AVM-VDD voltage is turned off, that is, the start voltage provided to the rear-stage circuit is delayed to be turned off. Since the 1 end of the grid control end of the second MOS tube Q2 is connected with the delay switch circuit, the conduction time of the 3 end and the 2 end can be prolonged so as to ensure that the voltage of the AVM-VDD and the subsequent stage circuit can be completely and reliably dropped to 0V.

It can be understood that the resistor R8 and the resistor R9 are connected to the base of the pin 1 of the transistor Q3 after voltage division, and the collector of the pin 3 of the transistor Q3 is connected to the base of the pin 1 of the transistor Q1 through the resistor R5. The resistor R4 is connected in parallel with the capacitor C2, one end of the resistor R4 is connected with the 2-pin emitter of the transistor Q1 together with 12V, and the other end is connected with the 3-pin collector of the transistor Q3. One end of the capacitor C3 is grounded, and the other end of the capacitor C3 and one end of the resistor R6 are connected together with the 3-pin collector of the transistor Q1. The resistor R6 and the resistor R7 are connected with the 1 pin grid of the MOS transistor Q2 after voltage division, and the grid of the Q2 is used as a control end to control the connection/disconnection of the 3 pin and the 2 pin of the Q2. The delay time of the first delay circuit and the second delay circuit is as follows:

wherein t is the time required for the voltage on the capacitor in the first delay circuit or the second delay circuit to discharge to Vt, R is the total resistance value in the first delay circuit or the second delay circuit, C is the total capacitance value in the first delay circuit or the second delay circuit, VCC is the initial voltage on the capacitor in the first delay circuit or the second delay circuit, and Vt is the voltage value on the capacitor in the first delay circuit or the second delay circuit after t time.

When the MCU outputs a high level to the resistor R8, the pin 3 and the pin 2 of the triode Q3 are conducted and grounded, so that the pin 2 and the pin 3 of the triode Q1 are conducted quickly, the input voltage 12V can be divided by the resistor R6 and the resistor R7 quickly, the voltage of the pin 1 of the MOS transistor Q2 reaches the starting voltage of the Q2 quickly, the pin 2 and the pin 3 of the Q2 are conducted and grounded quickly, and the purpose of quickly turning off the output voltage of the U1 is achieved. When the output voltage AVM-VDD of the U1 is turned off, the AVM-VDD is powered down to 0V after a short period of time, the MCU stops working, an IO port connected with the resistor R8 of the MCU and the resistor R8 is also changed into low level, and therefore a pin 3 and a pin 2 of the triode Q3 are immediately turned off and cut off. Due to the existence of the resistor R5 and the capacitor C2, charges at two ends of the capacitor C2 are discharged continuously through the pin 2 and the pin 1 of the transistor Q1 and the resistor R5, so that the pin 2 and the pin 3 of the transistor Q1 are not turned off immediately, the pin 2 and the pin 3 of the transistor Q1 can be kept on for a period of time, the pin 1 voltage of the MOS transistor Q2 can be kept high, and the pin 2 and the pin 3 of the transistor Q2 can be kept on and grounded. When the charges at the two ends of the capacitor C2 are discharged and balanced, the pin 2 and the pin 3 of the Q1 are turned off, and at this time, the gate voltage of the pin 1 of the MOS transistor Q2 does not immediately change to 0V due to the existence of the capacitor C3, the resistor R6 and the resistor R7, and the pin 3 and the pin 2 of the Q2 continue to be turned on and grounded. The charges at the two ends of the C3 are slowly discharged through the R6 and the R7, the voltage of the pin 1 of the Q2 is reduced to 0V after the charges at the two ends of the C3 are discharged and balanced, and the pin 3 and the pin 2 of the Q2 are turned off again, so that the U1 outputs the voltage AVM-VDD again, and the power-on reset of the system is completed.

It can be understood that the delay control of the present invention is divided into two stages, the first delay switch circuit formed by C2, R4 and R5 is the first stage, the first delay switch circuit formed by C3, R6 and R7 is the second stage, the discharge of the first stage reaches the turn-off and turn-off of the transistor Q1, the discharge of the second stage starts, and when the discharge reaches the turn-off voltage of the MOS transistor Q2, the turn-off and turn-on of the transistor Q2 can be realized, so as to achieve the delay effect. The parameter values of C2, R4, R5, C3, R6 and R7 can be adjusted according to actual requirements, the parameters of the triode and the MOS tube have little influence on the delay time, and the resistor and the capacitor which play a role in delay are mainly used, because the equivalent resistance and the equivalent capacitance of the triode are very small, the equivalent resistance and the equivalent capacitance can be ignored.

The utility model provides a self-power-off reset circuit which comprises a power supply module, a time delay control module and a controller, wherein the time delay control module is electrically connected with the power supply module; the power supply module is used for providing starting voltage for a rear-stage circuit, the delay control circuit is used for controlling the power supply module to be turned on or turned off, and the controller is used for outputting a corresponding power-off reset signal or power-on signal to the delay control circuit. The power-off reset circuit is simple in structure, can perform power-off reset on the system per se without human intervention, is controllable in power-off time, ensures the reliability of the reset function, and meets the actual application requirements.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A self-power-off reset circuit is characterized by comprising a power supply module, a delay control module electrically connected with the power supply module and a controller electrically connected with the delay control module; the power supply module is used for providing starting voltage for a rear-stage circuit, the delay control module is used for controlling the power supply module to be turned on or turned off, and the controller is used for outputting a corresponding power-off reset signal or power-on signal to the delay control module.

2. The self-power-off reset circuit according to claim 1, wherein the power supply module comprises a power chip, and a voltage divider circuit and a bootstrap circuit electrically connected to the power chip respectively; the power supply chip comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin.

3. The self-power-off reset circuit of claim 2, wherein the voltage divider circuit comprises a first resistor and a second resistor; the first end of the first resistor is electrically connected with a power interface, a node formed by the second end of the first resistor and the first end of the second resistor is electrically connected with the third pin of the power chip, and the second end of the second resistor is grounded.

4. The self-power-off reset circuit according to claim 2, wherein the bootstrap circuit comprises a third resistor and a first capacitor, a first end of the third resistor is electrically connected to the fourth pin of the power chip, a second end of the third resistor is electrically connected to the left plate of the first capacitor, and the right plate of the first capacitor provides a start-up voltage to the subsequent circuit through an inductor.

5. The self-power-off reset circuit of claim 3, wherein the delay control module comprises a switching circuit, a first delay switching circuit electrically connected to the switching circuit, and a second delay switching circuit electrically connected to the first delay switching circuit; the switch circuit is used for receiving the power-off reset signal or the power-on signal output by the controller and transmitting the power-off reset signal or the power-on signal to the first delay switch circuit, the first delay switch circuit is used for transmitting the received power-off reset signal or the power-on signal to the second delay switch circuit after delaying, and the second delay switch circuit is used for transmitting the delayed power-off reset signal or the delayed power-on signal to the power supply module.

6. The self-power-off reset circuit of claim 5, wherein the switching circuit comprises an eighth resistor, a ninth resistor, and a third transistor; a node formed by the second end of the eighth resistor and the first end of the ninth resistor is electrically connected to the first end of the third triode, the first end of the eighth resistor is electrically connected to the controller, and a node formed by the second end of the ninth resistor and the second end of the third triode is grounded.

7. The self-power-off reset circuit of claim 6, wherein the first delay switch circuit comprises a fourth resistor, a second capacitor, a fifth resistor and a first transistor; the fourth resistor is connected in parallel with the second capacitor, an upper pole plate of the second capacitor is electrically connected with a second end of the first triode, a lower pole plate of the second capacitor is electrically connected with a node formed by a third end of the third triode and a second end of the fifth resistor, and a first end of the fifth resistor is electrically connected with a first end of the first triode.

8. The self-power-off reset circuit according to claim 7, wherein the second delay switch circuit comprises a third capacitor, a sixth resistor, a seventh resistor and a second MOS transistor; a node formed by the second end of the sixth resistor and the first end of the seventh resistor is electrically connected with the first end of the second MOS transistor, the second end of the seventh resistor is grounded, the first end of the sixth resistor is electrically connected with a node formed by the first triode and the upper electrode plate of the third capacitor, the lower electrode plate of the third capacitor is grounded, the second end of the second MOS transistor is grounded, and the third end of the second MOS transistor is electrically connected with the third pin of the power chip.

9. The self-power-off reset circuit of claim 8, wherein the delay times of the first and second delay circuits are:

wherein t is the time required for the voltage on the capacitor in the first delay circuit or the second delay circuit to discharge to Vt, R is the total resistance value in the first delay circuit or the second delay circuit, C is the total capacitance value in the first delay circuit or the second delay circuit, VCC is the initial voltage on the capacitor in the first delay circuit or the second delay circuit, and Vt is the voltage value on the capacitor in the first delay circuit or the second delay circuit after t time.

10. The self power-off reset circuit of claim 9,

when the power supply is powered on, the controller outputs a low level to control the third end and the second end of the second MOS tube to be not conducted, the third pin of the power supply chip is not grounded, and the first resistor and the second resistor are connected with the third pin of the power supply chip after voltage division to provide starting voltage for a rear-stage circuit;

when the power is off and reset, the controller outputs a high level to the eighth resistor, the third end and the second end of the second MOS tube are controlled to be conducted and grounded through the third triode, the fifth resistor, the first triode, the third capacitor and the sixth resistor, the third end of the second MOS tube is connected with the third pin of the power chip, and the starting voltage provided for the rear-stage circuit is turned off in a delayed mode.

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