CN218335989U - Starting-up control circuit and communication module - Google Patents
Starting-up control circuit and communication module Download PDFInfo
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- CN218335989U CN218335989U CN202222081001.6U CN202222081001U CN218335989U CN 218335989 U CN218335989 U CN 218335989U CN 202222081001 U CN202222081001 U CN 202222081001U CN 218335989 U CN218335989 U CN 218335989U
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Abstract
The application provides a power-on control circuit and a communication module, which can be used for pulling down the level of a power-key pin to control the power-on. The startup control circuit comprises a pull-down unit and a delay control unit; the pull-down unit is connected with the power-key pin and the ground and is used for pulling down the level of the power-key pin; the delay control unit is connected with the pull-down unit and the power voltage VDD pin, and is used for controlling the on and off of the pull-down unit according to the level applied to the power voltage VDD pin. According to the power-key control circuit, pull-down control of the power-key pin is achieved through the power supply voltage VDD, automatic power-on starting can be achieved, the starting control circuit is simple in design and low in cost, and therefore the circuit design is simple, and the cost is low.
Description
Technical Field
The application relates to the technical field of starting control, in particular to a starting control circuit and a communication module.
Background
Power-up and power-on are two very important operations in the manufacture and use of electronic devices such as communication modules. The power-key pin of the electronic device is in a high level state when being powered on, so that the power-key pin needs to be pulled down in level to start the electronic device.
The current circuit design mainly controls the level of pulling down a power-key pin through a physical button switch, an Open Collector (OC) drive circuit, a Micro Controller Unit (MCU) or a voltage monitoring chip. However, the control mode of the physical button switch is substantially a manual control mode, which cannot realize automatic power-on and automatic power-off, and it is difficult to accurately control the time of pulling down the power-key pin, so that it is difficult to control the timing of power-on and power-off. For example, if the duration of pulling down the power-key pin is longer than 550ms, the power-on device is normally turned on, and if the duration of pulling down the power-key pin is between 3500ms and 7000ms, the power-off device is turned off. In other methods, chips with various specifications need to be adopted, which additionally increases the chip cost, and the circuit design is complex and the maintenance cost is high.
SUMMERY OF THE UTILITY MODEL
In view of this, the present application provides a power-on control circuit and a communication module, which can solve the problems that the physical button switch control mode cannot realize power-on automatic power-on and the pull-down time is difficult to be accurately controlled, and the problems that the chip control mode causes the circuit design to be complicated and the cost to be increased.
The power-on control circuit is used for pulling down the level of a power-key pin and comprises a pull-down unit and a delay control unit; the pull-down unit is connected with the power-key pin and the ground and is used for pulling down the level of the power-key pin; the delay control unit is connected with the pull-down unit and connected with a power supply voltage VDD pin, and is used for controlling the on and off of the pull-down unit according to the level applied to the power supply voltage VDD pin.
Optionally, the pull-down unit includes a first MOS transistor, the delay control unit includes a second MOS transistor, and the first MOS transistor and the second MOS transistor form an inverter.
Optionally, a base of the second MOS transistor is connected to the power supply voltage VDD pin, an emitter of the second MOS transistor is grounded, a collector of the second MOS transistor is connected to the base of the first MOS transistor, and the collector of the second MOS transistor is further connected to the battery voltage VBAT pin.
Optionally, a base of the first MOS transistor is connected to the battery voltage VBAT pin, a collector of the first MOS transistor is connected to the power-key pin, and an emitter of the first MOS transistor is grounded.
Optionally, the pull-down unit further includes a first charging circuit, the first charging circuit is connected to the collector of the first MOS transistor, and the first charging circuit is further grounded.
Optionally, the first charging circuit includes a first resistor and a first capacitor, two ends of the first resistor are respectively connected to the power-key pin and the collector of the first MOS transistor, an electrode of the first capacitor is connected in parallel between the power-key pin and the first resistor, and another electrode of the first capacitor is grounded.
Optionally, the delay control unit further includes a second charging circuit, the second charging circuit is connected to a collector of the second MOS transistor, and the second charging circuit is further grounded.
Optionally, the second charging circuit includes a second resistor and a second capacitor, two ends of the second resistor are respectively connected to the power supply voltage VDD pin and the base of the second MOS transistor, one electrode of the second capacitor is connected in parallel between the power supply voltage VDD and the second resistor, and the other electrode of the second capacitor is grounded.
Optionally, the battery voltage VBAT pin has a first output voltage to trigger the first MOS transistor to conduct, the power voltage VDD pin has a second output voltage to trigger the second MOS transistor to conduct, and the second output voltage is smaller than the first output voltage.
Optionally, the first output voltage is 4V, and the second output voltage is 1.8V.
The application provides a communication module, includes as aforementioned any one the start control circuit.
As described above, the power-on control circuit of the present application includes the pull-down unit and the delay control unit, and the delay control unit controls the pull-down unit to be turned on and off according to the level applied to the power voltage VDD pin, so as to control the pull-down unit to pull down the level of the power-key pin.
Drawings
Fig. 1 is an equivalent schematic diagram of a power-on control circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described below in detail with reference to specific embodiments and accompanying drawings. It should be apparent that the embodiments described below are only a part of the embodiments of the present application, and not all embodiments. In case of conflict, the following embodiments and their technical features may be combined with each other and also belong to the technical solutions of the present application.
It should be understood that in the description of the embodiments of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only used for convenience of describing technical solutions and simplifying the description of the respective embodiments of the present application, but do not indicate or imply that a device or an element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Referring to fig. 1, a power-on control circuit 1 according to an embodiment of the present invention is provided for pulling down a power-key pin level (also referred to as pull-down), for example, controlling a duration of the power-key pin being pulled down, and on the other hand, controlling a duration of the power-key pin not being pulled down. The power-key pin is a pin of the device, and the device may be woken up through an interrupt mechanism, where the specific representation type of the device includes, but is not limited to, various communication terminals such as a mobile phone, and the embodiment of the present application is not limited thereto.
The power-on control circuit 1 includes a pull-down unit 10 and a delay control unit 20.
The pull-down unit 10 is connected to the power-key pin, and the pull-down unit 10 is further grounded, and is configured to pull down the level of the power-key pin, that is, pull down the high level of the power-key pin after power-on to a low level.
The delay control unit 20 is connected to the pull-down unit 10 and also connected to a pin of a power supply voltage VDD. The delay control unit 20 is used for controlling the pull-down unit 10 to be turned on and off according to a level applied to the power voltage VDD pin. When the pull-down unit 10 is turned on, the pull-down unit 10 performs the pull-down operation, and the power-key pin is in a low level state; when the pull-down unit 10 is turned off, the pull-down unit 10 does not perform the pull-down operation, and the power-key pin is in a high state.
Based on the above, the power-on control circuit 1 of the present application implements pull-down control of the power-key pin through the power supply voltage VDD, and the power supply voltage VDD can be synchronously set through the power-on and power-off timing sequence after the device is powered on, i.e., can be controlled through the device main chip, so as to implement power-on automatic power-on, which is beneficial to accurately controlling the power-on and power-off timing sequence. Compared with a traditional OC drive circuit, an MCU or a voltage monitoring chip, the startup control circuit 1 does not need to introduce an I/O (input/output) control mechanism, and is simple in design and low in cost, so that the whole circuit is simple in design, and the production and maintenance cost is reduced.
Based on the foregoing description of the embodiments, the embodiments of the present application exemplarily provide a circuit representation of the pull-down unit 10 and the delay control unit 20, but are not limited thereto.
Referring to fig. 1, the pull-down unit 10 includes a first MOS transistor M 1 The delay control unit 20 includes a second MOS transistor M 2 First MOS transistor M 1 And a second MOS transistor M 2 Constituting an inverter. In one scenario, the first MOS transistor M 1 And a second MOS transistor M 2 May be of the same type, e.g. a uniform NPN transistor, whereThe two inverters can be regarded as CMOS inverters. The operation of the inverter can be seen from the following description of the operation principle and process of the power-on control circuit 1.
First MOS transistor M 1 Base electrode B of 10 Connected with a battery voltage VBAT pin, a first MOS tube M 1 Collector electrode C of 10 Connected with power-key pin, a first MOS transistor M 1 Emitter electrode E of 10 And is grounded.
Second MOS transistor M 2 Base electrode B of 20 A second MOS transistor M connected to power supply voltage VDD pin 2 Emitter electrode E of 20 Grounded, second MOS transistor M 2 Collector electrode C of 20 And a first MOS transistor M 1 Base electrode B of 10 Connected, second MOS transistor M 2 Collector electrode C of 20 A battery voltage VBAT pin is also connected.
Optionally, the pull-down unit 10 further includes a first charging circuit 11, and the first charging circuit 11 is connected to the first MOS transistor M 1 Collector electrode C of 10 The first charging circuit 11 is also connected to ground. The first charging circuit 11 can control the first MOS transistor M by charging or not 1 On and off.
The delay control unit 20 may also include a second charging circuit 21, and the second charging circuit 21 is connected to the second MOS transistor M 2 Collector electrode C of 20 The second charging circuit 21 is also connected to ground. The second charging circuit 21 can control the second MOS transistor M by charging or not 2 Collector electrode C of 20 The voltage of (c).
Alternatively, the specific type of the first charging circuit 11 and the second charging circuit 21 may be the same, for example, both may be RC (resistance-capacitance) circuits.
For example, referring to fig. 1, the first charging circuit 11 includes a first resistor R connected in parallel 1 And a first capacitor C 1 . A first resistor R 1 The two ends of the first MOS tube are respectively connected with a power-key pin and a first MOS tube M 1 Collector electrode C of 10 First capacitor C 1 Is connected in parallel with R between the power-key pin and the first resistor 1 First capacitor C 1 The other electrode (e.g., the negative electrode) of (a) is grounded.
Similarly, the second charging circuit 21 may include a second resistor R connected in parallel 2 And a second capacitor C 2 . A second resistor R 2 Both ends of the first MOS tube are respectively connected with a power voltage VDD pin and a second MOS tube M 2 Base electrode B of 20 Second capacitance C 2 Is connected in parallel to a supply voltage VDD and a second resistor R 2 Between, a second capacitance C 2 The other electrode (e.g., the negative electrode) of (a) is grounded.
When the device is powered on, the VBAT pin outputs a voltage (hereinafter referred to as a first output voltage), so that the first MOS transistor M 1 Base electrode B of 10 In a high level state, the first MOS transistor M is at this time 1 And when the power-key pin is conducted, the power-key pin is grounded and pulled down, so that the equipment is automatically started to work.
After the device is automatically turned on, a voltage (hereinafter referred to as a second output voltage) may be output by controlling the VDD pin, so that the second MOS transistor M 2 Base electrode B of 20 In a high state, the second MOS transistor M is in a high state 2 And conducting. Wherein the second output voltage is less than the first output voltage. For example, in one scenario, the first output voltage may be 4V and the second output voltage may be 1.8V. The first MOS transistor M can be controlled due to the action of the phase inverter 1 Base electrode B of 10 At the low level state, the MOS transistor M 1 And when the power-key pin is cut off, the power-key pin is cut off to the ground, and the power-key pin is in a high level state, so that the equipment is in a power-off state.
In the delay control unit 20 of the present application, the second resistor R 2 A second capacitor C 2 And a second MOS transistor M 2 Forming a delay control circuit, wherein the calculation formula of the delay time is as follows:
T＝-RC*ln[(E-V)/V]
wherein R represents a second resistance R 2 C represents a second capacitance C 2 E is the second capacitance C 2 The highest voltage obtainable at no load, V being the second capacitance C 2 The highest voltage actually reached in the start-up control circuit 1, T, represents the delay time of the delay control unit 20, which may representThe pull-down time of the power-key pin, i.e., the power-on duration.
When the second charging circuit 21 is not charged to the second MOS transistor M 2 When the voltage is on, the second MOS transistor M 2 Cut-off, second MOS transistor M 2 Emitter electrode E of 20 Outputting a high level; when the second charging circuit 21 is charged to reach the second MOS transistor M 2 At the turn-on voltage of the second MOS transistor M 2 Is conducted, then the second MOS transistor M 2 Of the emitter E 20 Is low. Through the first MOS transistor M 1 In cooperation, the pull-down time of the power-key pin can be indirectly controlled, so that the startup time sequence is controlled.
In addition, by adjusting the second resistor R in the second charging circuit 21 2 Resistance value of (2) and second capacitance C 2 The capacitance value of (2) can meet different time sequence control scene requirements, and the expansibility is strong.
The embodiment of the present application further provides a communication module, which includes an adaptive communication electronic component and the power-on control circuit 1 according to any of the above embodiments, where the power-on control circuit 1 may be disposed on a corresponding circuit board, or may be disposed in the communication module in a module or unit manner. Therefore, the communication module can generate the beneficial effects of the power-on control circuit 1 according to the embodiment.
The communication module may be applied to various communication terminals, including mobile terminals such as mobile phones, tablet computers, notebook computers, palmtop computers, personal Digital Assistants (PDAs), portable Media Players (PMPs), navigation devices, wearable devices, smart bands, pedometers, and fixed terminals such as Digital TVs, broadcasting, desktop computers, and the like.
It should be understood that the above-mentioned embodiments are only some examples of the present application, and not intended to limit the scope of the present application, and all equivalent structural changes made by those skilled in the art using the contents of the present specification and the attached drawings are all included in the scope of the present application.
Although the terms "first, second, etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. In addition, the singular forms "a", "an" and "the" are intended to include the plural forms as well. The terms "or" and/or "are to be construed as inclusive or meaning any one or any combination. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.
Claims (10)
1. A starting-up control circuit is used for pulling down the level of a power-key pin and is characterized by comprising a pull-down unit and a delay control unit; the pull-down unit is connected with the power-key pin and the ground and is used for pulling down the level of the power-key pin; the delay control unit is connected with the pull-down unit and is connected with a power supply voltage VDD pin, and the delay control unit is used for controlling the on and off of the pull-down unit according to the level applied to the power supply voltage VDD pin.
2. The power-on control circuit according to claim 1, wherein the pull-down unit comprises a first MOS transistor, the delay control unit comprises a second MOS transistor, and the first MOS transistor and the second MOS transistor form an inverter.
3. The power-on control circuit of claim 2,
the base electrode of the second MOS tube is connected with the power supply voltage VDD pin, the emitter electrode of the second MOS tube is grounded, the collector electrode of the second MOS tube is connected with the base electrode of the first MOS tube, and the collector electrode of the second MOS tube is also connected with the battery voltage VBAT pin;
the base electrode of the first MOS tube is connected with the VBAT pin of the battery voltage, the collector electrode of the first MOS tube is connected with the power-key pin, and the emitter electrode of the first MOS tube is grounded.
4. The power-on control circuit according to claim 2 or 3, wherein the pull-down unit further comprises a first charging circuit, the first charging circuit is connected to a collector of the first MOS transistor, and the first charging circuit is further connected to ground.
5. The power-on control circuit of claim 4, wherein the first charging circuit comprises a first resistor and a first capacitor, two ends of the first resistor are respectively connected to the power-key pin and the collector of the first MOS transistor, one electrode of the first capacitor is connected in parallel between the power-key pin and the first resistor, and the other electrode of the first capacitor is grounded.
6. The power-on control circuit according to claim 2 or 3, wherein the delay control unit further comprises a second charging circuit, the second charging circuit is connected to a collector of the second MOS transistor, and the second charging circuit is further connected to ground.
7. The power-on control circuit according to claim 6, wherein the second charging circuit comprises a second resistor and a second capacitor, two ends of the second resistor are respectively connected to the power supply voltage VDD pin and the base of the second MOS transistor, one electrode of the second capacitor is connected in parallel between the power supply voltage VDD and the second resistor, and the other electrode of the second capacitor is grounded.
8. The power-on control circuit of claim 3, wherein the battery voltage VBAT pin has a first output voltage to trigger the first MOS transistor to conduct, the power voltage VDD pin has a second output voltage to trigger the second MOS transistor to conduct, and the second output voltage is less than the first output voltage.
9. The power-on control circuit of claim 8, wherein the first output voltage is 4V and the second output voltage is 1.8V.
10. A communication module comprising the power-on control circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222081001.6U CN218335989U (en) | 2022-08-05 | 2022-08-05 | Starting-up control circuit and communication module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222081001.6U CN218335989U (en) | 2022-08-05 | 2022-08-05 | Starting-up control circuit and communication module |
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| Publication Number | Publication Date |
|---|---|
| CN218335989U true CN218335989U (en) | 2023-01-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222081001.6U Active CN218335989U (en) | 2022-08-05 | 2022-08-05 | Starting-up control circuit and communication module |
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| CN (1) | CN218335989U (en) |
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- 2022-08-05 CN CN202222081001.6U patent/CN218335989U/en active Active
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