CN216873088U

CN216873088U - Full-bridge rectifier chip and power converter

Info

Publication number: CN216873088U
Application number: CN202220361448.6U
Authority: CN
Inventors: 唐盛斌
Original assignee: Suzhou Yuante Semiconductor Technology Co ltd
Current assignee: Suzhou Yuante Semiconductor Technology Co ltd
Priority date: 2022-02-22
Filing date: 2022-02-22
Publication date: 2022-07-01
Anticipated expiration: 2032-02-22

Abstract

The utility model discloses a full-bridge rectifier chip and a power converter, wherein the full-bridge rectifier chip comprises a first rectifier pin, a second rectifier pin, a low potential pin, a high potential pin, a first diode, a second diode, a first rectifier MOS (metal oxide semiconductor) tube and a second rectifier MOS tube; the anode of the first diode, the drain of the first rectifying MOS tube and the gate of the second rectifying MOS tube are connected with a first rectifying pin; the anode of the second diode, the drain of the second rectifying MOS tube and the gate of the first rectifying MOS tube are connected with a second rectifying pin; the cathode of the first diode and the cathode of the second diode are connected with a high-potential pin; the source electrode of the first rectifying MOS tube and the source electrode of the second rectifying MOS tube are connected with a low potential pin. The secondary side of the power converter only needs one winding, and each bridge arm of the full-bridge rectifier chip is provided with one NMOS tube, so that the efficiency is improved, and the load regulation rate is relatively low.

Description

Full-bridge rectifier chip and power converter

Technical Field

The utility model relates to the technical field of integrated circuit design, in particular to a full-bridge rectifier chip and a power converter.

Background

The push-pull converter was originally invented in 1957 by the united states research (JenSen) as a self-excited push-pull converter, also called as a self-oscillating JenSen circuit, and with the rapid development of BCD semiconductor technology in recent years, other-excited push-pull converter control chips and full-bridge converter control chips of integrated control circuits and power tubes are introduced by various companies at home and abroad, so that the number of devices is less, and the reliability is higher. The push-pull converter and the full-bridge converter belong to forward converters, and are widely applied to a DCDC (direct current-direct current) isolation converter of a micro-power module in the field of global industrial control due to the characteristics of simple structure, high magnetic flux utilization rate and small size.

The operating principle of the push-pull converter is shown in fig. 1 and 2. The push-pull converter comprises two isolated transmission paths, wherein FIG. 1 is a schematic diagram of a first isolated transmission loop of the push-pull converter, a thick solid line is a current path of isolated transmission, a switch Q1 is turned on, and current is input from a positive end V of a power supply of the converter_INStarting from the transformer main transformer winding N_P1Then flows to the negative end of the input power supply of the converter through the Q1, and the current flows from the secondary winding N due to the coupling action of the isolation converter_S1The current flows out from the same name terminal, the rectifier diode D1 is conducted to supply power for the output capacitor and the resistance load, and thus the energy is supplied from the power supply V on the primary side of the converter_INSecondary side V for transmission to converter_OUT. In the first isolated transmission loop, Q2 is off, transformer winding N_P2Without passing current, secondary winding N_S2The end of the rectifier diode D2 with a negative voltage at its anode, the diode is turned off in the reverse direction, and the winding N is connected to the power supply_S2And the rectifier diode D2 pass no current. FIG. 2 is a schematic diagram of a second isolated transmission loop of the push-pull converter, wherein the current transmission path is shown by a thick solid line, and in contrast to the first transmission loop, the switch Q1 is open, the switch Q2 is closed, and the primary current is from V_INBy winding N_P2The secondary side passing through winding N_S2And the rectifier diode D2 to the output terminal V_OUTWinding N_P1、N_S1And the rectifier diode D1 pass no current. It can be seen that when the first loop transmits energy, the device on the second loop is cut off, whereas when the second loop transmits energy, the device on the first loop is cut off, and the first loop and the second loop alternately transmit energy to the output terminal V at the same time_OUTThe process is thus known as a push-pull, "push-pull" converter.

The operating principle of the full-bridge inverter is shown in fig. 3 and 4. In contrast to push-pull converters, voltage transformationThe primary side of the transformer has only one winding N_PThe transmission direction of the current is controlled by four switches of Q1, Q2, Q3 and Q4. The thick solid lines and their arrows in fig. 3 show the first isolated transmission loop, Q1 and Q3 form one leg, which is on at the same time, Q2 and Q4 form the other leg, which is off at the same time, so that current flows from transformer N_PThe homonymous terminal of (A) flows into the heteronymous terminal and flows out. Conversely, in the second transmission loop, the leg formed by Q1 and Q3 is closed, the leg formed by Q2 and Q4 is open, and current flows from transformer N_PThe synonym end of (A) flows into the homonym end and flows out. The two bridge arms are alternately switched on and off at the same time, and the same effect as that of push-pull can be achieved. One more winding is added to a circuit topology structure transformer of the push-pull converter, the transformer is relatively complex, but only two power tubes are needed to drive the transformer; the circuit topology transformer of the full-bridge converter is simpler, but four switches are needed to drive the transformer, so that the two topologies are different in thousands of autumn.

The full-bridge converter and the push-pull converter belong to forward converters, and are named according to whether the primary winding of the isolation transformer is in push-pull driving or full-bridge driving. The secondary rectifier circuits in fig. 1-4 are the same, only one winding is conducted with the rectifier diode at a time, and the other winding is not conducted with the rectifier diode, so that the secondary rectifier circuit is often called half-bridge rectification. In fact, the secondary side of the transformer may also use a winding to perform the rectification function, as shown in fig. 5 and 6, which are paths of the first and second isolated transmission loops, respectively, and the primary side of the transformer may use a push-pull driving method, or may use a full-bridge driving method as shown in fig. 3 and 4. The current transmission path of the first loop is shown by the thick solid line and its arrow in fig. 5, and the primary current passes through the winding N_P1And a switch Q1, the secondary current from winding N_SThe different name end of the voltage transformer flows into the same name end of the voltage transformer and flows out of the same name end of the voltage transformer, and the energy is transmitted to the V through two rectifier diodes D1 and D3_OUTThe primary switch Q2 and the secondary D2 and D4 rectifier diodes are both off. The current transmission path of the second loop is shown by the thick solid line and its arrows in fig. 6, and the primary current passes through the winding N_P2And a switch Q2, the secondary current from winding N_SThe homonymous terminal of the D-bridge rectifier flows into the heteronymous terminal of the D-bridge rectifier and flows out of the heteronymous terminal of the D-bridge rectifier, and energy is transmitted to the V through two rectifier diodes of D2 and D4_OUTThe primary switch Q1 and the secondary D1 and D3 rectifier diodes are both off. It can be seen that Q1 and Q3 form one leg and Q2 and Q4 form the other leg, and the two legs are alternately switched on and off to form a common full-bridge rectifier circuit. Because the secondary side of the transformer only needs one winding, the production cost is reduced. But it requires four diodes and each bridge arm will have two diode drops when conducting, resulting in low efficiency and poor load regulation. Therefore, the patent of application No. 201811463425.0 proposes a full-bridge synchronous rectification controller, which realizes a synchronous rectification function while completing a full-bridge rectification function, and solves the problems of low load regulation rate and low efficiency, but the adoption of synchronous rectification has its inherent defects.

In most application scenarios, the split diode rectification scheme in the prior art, namely the half-bridge rectification and the full-bridge rectification, is adopted, and the common disadvantage is that the number of devices is large, and the current tends to flow to one way of the diode with lower voltage drop and internal resistance due to the deviation of device parameters, so that the current bias phenomenon is often called, and further the transformer is biased. In addition, the transformer of half-bridge rectification has one more winding, and full-bridge rectification saves one winding, but causes the problems of low efficiency and low load regulation rate. Although the patent of application No. 201811463425.0 solves these problems, synchronous rectification needs to be accurately detected and timely turned off, otherwise current backflow is easy to occur, reliability is inevitably inferior to that of a diode, and rapid turning off of a synchronous rectifier tube also inevitably causes large switching noise.

SUMMERY OF THE UTILITY MODEL

The utility model provides a full-bridge rectification chip and a power converter, which can solve the problems that a separated diode rectification scheme in the prior art has more devices, can generate a bias current phenomenon and cause magnetic biasing of a transformer, and the full-bridge rectification in the prior art saves one winding, but causes low efficiency, low load regulation rate and the like.

The purpose of the utility model is realized by the following technical scheme:

in a first aspect, the utility model provides a full-bridge rectifier chip, which comprises a first rectifier pin, a second rectifier pin, a low potential pin, a high potential pin, a first diode, a second diode, a first rectifier MOS transistor and a second rectifier MOS transistor; the anode of the first diode, the drain of the first rectifying MOS tube and the gate of the second rectifying MOS tube are connected with the first rectifying pin; the anode of the second diode, the drain of the second rectifying MOS tube and the gate of the first rectifying MOS tube are connected with the second rectifying pin; the cathode of the first diode and the cathode of the second diode are connected with the high-potential pin; and the source electrode of the first rectifying MOS tube and the source electrode of the second rectifying MOS tube are connected with the low potential pin.

Furthermore, the first diode, the second diode, the first rectifying MOS tube and the second rectifying MOS tube are manufactured on the same wafer.

Furthermore, the full-bridge rectifier chip also comprises a first self-driving circuit and a second self-driving circuit; the first self-driving circuit is connected between the grid electrode of the first rectifying MOS tube and the second rectifying pin, and the second self-driving circuit is connected between the grid electrode of the second rectifying MOS tube and the first rectifying pin.

Further, the first self-driving circuit and the second self-driving circuit are first driving resistors.

Further, the first self-driving circuit comprises a first driving MOS transistor, and the second self-driving circuit comprises a second driving MOS transistor; the grid electrode of the first driving MOS tube and the grid electrode of the second driving MOS tube are connected with a bias voltage source, the source electrode of the first driving MOS tube is connected with the grid electrode of the first rectifying MOS tube, and the drain electrode of the first driving MOS tube is connected with the second rectifying pin; the source electrode of the second driving MOS tube is connected with the grid electrode of the second rectifying MOS tube, and the drain electrode of the second driving MOS tube is connected with the first rectifying pin.

Furthermore, the full-bridge rectifier chip also comprises two other driving circuits, wherein the input port of the first other driving circuit is connected with the second rectifier pin, and the input port of the second other driving circuit is connected with the first rectifier pin; the output port of the first driving circuit is connected with the grid electrode of the first rectifying MOS tube; the output port of the second driving circuit is connected with the grid electrode of the second rectifying MOS tube; the power supply positive port of the first other driving circuit and the power supply positive port of the second other driving circuit are connected with the high-potential pin; and the power supply negative port of the first other driving circuit and the power supply negative port of the second other driving circuit are connected with the low-potential pin.

Furthermore, the driving circuit comprises a Schmidt rectifier, at least one NOT gate and a second driving resistor which are sequentially connected in series; the input end of the Schmitt rectifier is used as the input end of the driving circuit, the output end of the Schmitt rectifier is connected with the input end of the at least one NOT gate which is sequentially connected in series, the output end of the at least one NOT gate which is sequentially connected in series is connected with one end of the second driving resistor, and the other end of the second driving resistor is used as the output end of the driving circuit; the power source positive port of the at least one NOT gate sequentially connected in series is used as the power source positive port of the driving circuit of the NOT gate, and the power source negative port of the at least one NOT gate sequentially connected in series is used as the power source negative port of the driving circuit of the NOT gate.

Further, the driving circuit further comprises a linear voltage regulator connected between the positive power port of the at least one not gate and the positive power port of the driving circuit.

In a second aspect, the utility model provides a power converter, which mainly includes a transformer and the full-bridge rectifier chip, wherein a first rectifier pin of the full-bridge rectifier chip is connected to a homonymous end of a secondary winding of the transformer, a second rectifier pin of the full-bridge rectifier chip is connected to a heteronymous end of the secondary winding of the transformer, a high potential pin of the full-bridge rectifier chip is used as an output positive of the power converter, and a low potential pin of the full-bridge rectifier chip is used as an output negative ground of the power converter.

Further, the power converter is a push-pull converter or a full-bridge converter.

Compared with the prior art, the full-bridge rectifier chip and the converter have the following beneficial effects:

1. the secondary side of the transformer only needs one winding by adopting a full-bridge rectification mode, and compared with the traditional full-bridge rectification consisting of 4 diodes, each bridge arm is provided with an NMOS (N-channel metal oxide semiconductor) tube, so that the conduction voltage drop is very small, and the efficiency and the smaller load regulation rate are improved;

2. two rectifier diodes and two rectifier NMOS tubes are integrated into a small chip, so that four-in-one is realized, and the occupied area of the four-in-one rectifier is far smaller than that of a half-bridge rectifier circuit and a full-bridge rectifier circuit built by the existing separation device;

3. because the devices are integrated on the same wafer, the devices are close to each other, and the matching performance is good, namely the performance parameters of the diodes D1 and D2 are basically the same as the performance parameters of the NMOS transistors NM1 and NM2, so that the bias current phenomenon of the converter can be effectively avoided;

4. the utility model selects the on and off of the two bridge arms through the natural characteristics of forward conduction and reverse cut-off of the diode, has no current back-flow mechanism of synchronous rectification, has high reliability, and does not have large noise caused by rapidly closing the synchronous rectification tube.

Drawings

FIG. 1 is a schematic diagram of a first isolated transmission loop of a prior art push-pull converter;

FIG. 2 is a schematic diagram of a second isolated transmission loop of a prior art push-pull converter;

FIG. 3 is a schematic diagram of a first isolated transmission loop of a prior art full bridge inverter;

FIG. 4 is a schematic diagram of a second isolated transmission loop of a prior art full bridge inverter;

FIG. 5 is a schematic diagram of a prior art full bridge rectified first isolated transmission loop;

FIG. 6 is a schematic diagram of a prior art full bridge rectified second isolated transmission loop;

fig. 7 is a full bridge control chip according to a first embodiment of the present invention;

FIG. 8 is a schematic diagram of a full bridge rectifier chip in a first isolation loop according to an embodiment;

FIG. 9 is a schematic diagram of a full bridge rectifier chip in a second isolation loop according to an embodiment;

fig. 10 is a full bridge control chip according to a second embodiment of the present invention;

fig. 11 is a full bridge control chip according to a third embodiment of the present invention;

fig. 12 is a full bridge control chip according to a fourth embodiment of the present invention;

FIG. 13 is a first embodiment of a driving circuit according to a fourth embodiment of the present invention;

fig. 14 is a second embodiment of a driving circuit according to a fourth embodiment of the present invention.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without inventive step, are intended to be within the scope of the present disclosure.

Example one

In view of the defects of the existing rectifying circuit of the push-pull and full-bridge converter, the utility model provides a full-bridge rectifying chip, as shown by a dotted line frame in fig. 7, which comprises: the first rectifying pin VD1, the second rectifying pin VD2, the low potential pin GND and the high potential pin VCC. The full-bridge rectifying chip of the present embodiment is a self-driving chip, and includes a first diode D1, a second diode D2, a first rectifying MOS transistor NM1, and a second rectifying MOS transistor NM 2. The first diode D1 and the second diode D2 are schottky diodes, the first rectifying MOS transistor NM1 and the second rectifying MOS transistor NM2 are N-channel insulated gate transistors, and the four rectifying transistors are fabricated on the same wafer by an integrated circuit semiconductor process. The anode of the first diode D1, the drain of the first rectifying MOS transistor NM1 and the gate of the second rectifying MOS transistor NM2 are connected to the first rectifying pin VD1 of the full-bridge rectifying chip; the anode of the second diode D2, the drain of the second rectifying MOS transistor NM2 and the gate of the first rectifying MOS transistor NM1 are connected to a second rectifying pin VD2 of the full-bridge rectifying chip; the cathode of the first diode D1 and the cathode of the second diode D2 are connected with a high-potential pin VCC of the full-bridge rectifying chip; the source of the first rectifying MOS transistor NM1 and the source of the second rectifying MOS transistor NM2 are connected to a low potential pin GND of the full-bridge rectifying chip.

The first diode D1 and the second diode D2 function as rectifying diodes, also referred to below as rectifying diodes.

The full-bridge rectifier chip provided by the utility model can be used for a push-pull converter and a full-bridge converter, so the utility model also provides a power converter, which mainly comprises a transformer and the full-bridge rectifier chip, wherein a first rectifier pin VD1 of the full-bridge rectifier chip is connected with the homonymous end of a secondary winding of the transformer, a second rectifier pin VD2 of the full-bridge rectifier chip is connected with the synonym end of the secondary winding of the transformer, a high potential pin VCC of the full-bridge rectifier chip is used as the positive output of the power converter, and a low potential pin GND of the full-bridge rectifier chip is used as the negative output ground of the power converter.

In order to more clearly illustrate the working principle of the full-bridge rectifier chip of the present invention, fig. 8 and 9 show the rectification process of the full-bridge rectifier chip in the first isolated transmission loop and the second isolated transmission loop of the push-pull converter, respectively, but this is not intended to limit the application range of the full-bridge rectifier chip. The full-bridge rectifier chip is also suitable for a full-bridge converter, and the full-bridge converter is formed as long as the primary side of the transformer adopts one winding and the winding is driven according to a bridge type. Since the working principle of the full-bridge rectifier chip in the push-pull converter is the same as that in the full-bridge converter, the working principle of the full-bridge rectifier chip in the full-bridge converter is not described in detail.

As shown by the thick solid line and the current arrow in fig. 8, the first isolated transmission loop is formed, the switch Q2 is closed, the switch Q1 is opened, and the current is input from the converter to the positive end V of the power supply_INStarting from the transformer winding N_P1The same name end of the converter is flowed into the different name end and is flowed out, and then is flowed into negative end of input power supply of converter by means of switch Q1. Current flows from the secondary winding N according to the polarity of the transformer_SThe voltage of the second rectifying pin VD2 of the full-bridge rectifying chip is reduced, the rectifying diode D2 is naturally cut off in the reverse direction, the voltage at the VD2 is smaller than the turn-on voltage of the NMOS tube NM1, NM1 is closed, then the voltage at the first rectifying pin VD1 is increased, when the voltage at the position exceeds the turn-on voltage of the NM2, NM2 is conducted, and the rectifying diode D1 is conducted along with the increase of the voltage at the VD 1. It can be seen that in the first transmission loop, D1 and NM2 are on, D2 and NM1 are off, and the formed rectifying loop is: current secondary winding N_SThe same name end of the full-bridge chip flows out, enters a first rectification pin VD1 of the full-bridge chip, flows out from a VCC pin after passing through a diode D1, and is transmitted to the positive output end V of the converter_OUTThen flows out from the output negative terminal, enters the GND pin of the full-bridge chip, flows out from VD2 after passing through NM2, and finally flows back to the N of the secondary winding_STo form a closed loop.

As shown by the thick solid line and the current arrow in fig. 9, the second isolated transmission loop is formed, the switch Q1 is turned off, the switch Q2 is turned on, and the current is input from the converter to the positive terminal V of the power supply_INStarting from the transformer winding N_P2The synonym end of the inverter flows into the homonym end and flows out, and then flows into the negative end of the input power supply of the inverter through the switch Q2. Current flows from the secondary winding N according to the polarity of the transformer_SThe same name end of the full-bridge rectifier chip flows into the different name end of the full-bridge rectifier chip and flows out, so that the voltage of the first rectifier pin VD1 of the full-bridge rectifier chip is reduced, the rectifier diode D1 is naturally cut off in the reverse direction, the voltage at the second rectifier pin VD2 is increased as the voltage at the VD1 is smaller than the turn-on voltage of NM2 and NM2 is closed, when the voltage at the position exceeds the turn-on voltage of NM1, NM1 is conducted, and as the voltage at the VD2 is increased, the rectifier diode D2 is conducted. It can be seen that in the second transmission loop, D2 and NM1 are on, D1 and NM2 are off,the formed rectifying loop is as follows: current secondary winding N_SThe current flows out to the second rectification pin VD2 of the full-bridge chip, flows out from the VCC pin after passing through D2, and is transmitted to the positive output end V of the converter_OUTThen flows out from the output negative terminal, enters the GND pin of the full-bridge chip, flows out from VD1 after passing through NM1, and finally flows back to the N of the secondary winding_SThe homonymous end of (c) to form a closed loop.

The secondary side of the transformer of the full-bridge rectification chip only needs one winding, and is different from the traditional full-bridge rectification consisting of 4 diodes in that each bridge arm is provided with an NMOS tube, so that the conduction voltage drop is small, and the efficiency and the small load regulation rate are improved.

Two rectifier diodes and two rectifier NMOS tubes are integrated into a small chip, four unifications are realized, and the area of a occupied plate is far smaller than that of a half-bridge and full-bridge rectifier circuit built by the existing separation device.

Because the two rectifying diodes and the two rectifying NMOS tubes are integrated on the same wafer, the devices are close to each other, and the matching performance is good, namely the performance parameters of the diodes D1 and D2 are basically the same as the performance parameters of the NMOS tubes NM1 and NM2, so that the bias current phenomenon of the converter is avoided.

According to the embodiment, the two bridge arms are switched on and off through the forward conduction and reverse cut-off natural characteristics of the diode, a current backflow mechanism of synchronous rectification does not exist, the reliability is high, and large noise caused by rapid closing of the synchronous rectification tube does not exist.

Example two

According to the principle, the full-bridge rectifier chip selects the on and off of a bridge arm through the natural characteristics of the diodes, and the driving speed and the driving current of the rectifier NMOS tube are controlled by the secondary winding N_SThis is determined, in effect, by the switching speeds of the primary switches Q1 and Q2. In the full-bridge rectification chip provided by the second embodiment, two self-driving circuits are added, and the rectification NMOS tube is changed into a secondary side to limit the switching speed. The first self-driving circuit is connected between the grid of the first rectification MOS tube NM1 and the second rectification pin VD2 of the full-bridge rectification chip, and the second self-driving circuit is connected between the second rectification MOS tube NM2And the first rectifying pin VD1 of the full-bridge rectifying chip.

Further, the first self-driving circuit and the second self-driving circuit are driving resistors, such as R shown in FIG. 10_G1And R_G2。

As shown by the dashed line frame in fig. 10, the full-bridge rectifier chip provided in the second embodiment is added with the first driving resistor R based on the first embodiment_G1And a second driving resistor R_G2First driving resistor R_G1One end of the first rectifying MOS transistor is connected with the grid electrode of the first rectifying MOS transistor NM1, and the first driving resistor R_G1And the other end of the second rectifying pin VD2 of the full-bridge rectifying chip is connected. Second driving resistor R_G2One end of the second rectifying MOS transistor is connected with the grid electrode of a second rectifying MOS transistor NM2, and a second driving resistor R_G2The other end of the first rectifying pin VD1 is connected to the full-bridge rectifying chip. The connection relationship and the operation principle of other components in fig. 10 are the same as those in the first embodiment, and are not described herein again.

In this embodiment, because the NMOS transistors NM1 and NM2 each have an increased driving resistance, the switching noise can be further reduced, and the method is suitable for applications requiring high noise, such as high-precision analog-to-digital converters. Of course, the switching speed of NMOS transistors NM1 and NM2 is reduced due to the driving resistance, but the diodes D1 and D2 are naturally turned off in the reverse direction, and the current is not caused to flow from V_OUTAnd (4) pouring the water back. The full-bridge rectifier chip and the operating principle thereof in the power converter of this embodiment are the same as those in the first embodiment, and are not described again.

EXAMPLE III

As shown by the dotted line frame in fig. 11, the full bridge rectifier chip provided in the third embodiment is different from the second embodiment in that the first self-driving circuit and the second self-driving circuit of the present embodiment are driving MOS transistors, such as the first driving MOS transistor NM3 and the second driving MOS transistor NM4 shown in fig. 10.

The first drive MOS transistor NM3 and the second drive MOS transistor NM4 are N-channel insulated gate transistors, and the grid of the first drive MOS transistor NM3 and the grid of the second drive MOS transistor NM4 are connected with a bias voltage source V_BThe source of the first driving MOS transistor NM3 is connected to the gate of the first rectifying MOS transistor NM1, and the first driving MOS transistor NM1The drain of NM3 is connected to a second rectifying pin VD 2. The source of the second driving MOS transistor NM4 is connected to the gate of the second rectifying MOS transistor NM2, and the drain of the second driving MOS transistor NM4 is connected to the first rectifying pin VD 1. The connection relationship and the operation principle of other components in fig. 11 are the same as those in the first embodiment and the second embodiment, and are not described herein again.

Gate driving voltages of the rectifiers NM1 and NM2 in the first and second embodiments are about V_OUT+V_BEIn which V is_BEThe conduction voltage drop of the diode D1 or D2 is generally 0.2V-0.5V. In the integrated circuit process, in order to make the turn-on voltage of the NMOS transistor lower, a thinner gate oxide layer is often used, so that the withstand voltage of the gate is lower, the rated operating voltage of the gate is generally only a few volts, and therefore, for V, V is measured_OUTThe application exceeding 10V is not suitable for the driving method as in the first embodiment and the second embodiment, and the voltage may exceed the operating voltage of the gate of the NMOS transistor and be damaged.

The third embodiment provides a full-bridge rectifier chip for solving the problem of V_OUTAt high output voltage, the gate of NM1 and NM2 has a problem of overvoltage. The working principle is as follows: the gates of the rectifying NMOS transistors NM1 and NM2 are connected with a bias power supply V_BIt is a stable voltage source, and it is easy to generate such bias voltage by Zener clamp or linear voltage regulator in the integrated circuit design. At low voltage at VD1 and VD2 pins, V_BThe NM3 and NM4 are turned on, so that the gate voltages of NM1 and NM2 are equal to the voltages at VD2 and VD1 respectively, namely low voltage, and the turning-off of NM1 and NM2 is not influenced; when the voltage at the VD1 and VD2 pins is high voltage, the voltage is V_OUT+V_BEHowever, the gate voltages of NM1 and NM2 do not reach such high, and the maximum value is limited to V_B-V_THIn which V is_THAre threshold voltages of NM1 and NM 2. It can be seen that only the appropriate V is selected_BWhen the high voltage is applied to the pins VD1 and VD2, NM2 and NM1 are fully turned on, and the gate voltages thereof are ensured to be within the rated range.

From the above principles, it can be seen that there are NM3, NM4 and V_BLimit the maximum driving voltage of NM1 and NM2, andthe effective on and off of NM1 and NM2 during the rectification process is not affected, and the working principle of the full-bridge rectification chip and its power converter is the same as that of the first and second embodiments, and is not described again.

Example four

The three previous embodiments have a common feature that the charging and discharging of the gates of the rectifying NMOS transistors NM1 and NM2 are all energy from the secondary winding N of the transformer_SDriven autonomously by the winding, this mode of driving is often referred to as self-driving. There is another driving method, which is to control the driving circuit to turn on or off the rectifying NMOS transistors NM1 and NM2 when the detected signal reaches a predetermined value, and this embodiment is implemented by using another driving method.

As shown by the dashed line in fig. 12, the full-bridge rectifier chip provided in the fourth embodiment includes: the first rectifying pin VD1, the second rectifying pin VD2, the low potential pin GND and the high potential pin VCC. The chip comprises a first diode D1, a second diode D2, a first rectifying MOS tube NM1, a second rectifying MOS tube NM2, a first other driving circuit and a second other driving circuit. The anode of the first diode D1, the drain of the first rectifying MOS tube NM1 and the input port of the second rectifying MOS tube drive circuit are connected with a first rectifying pin VD1 of the full-bridge rectifying chip; the anode of the second diode D2, the drain of the second rectifying MOS transistor NM2 and the input port of the first other driving circuit are connected to the second rectifying pin VD2 of the full-bridge rectifying chip. The output port of the first other driving circuit is connected with the gate of the first rectifying MOS transistor NM 1. The output port of the second other driving circuit is connected with the gate of the second rectifying MOS transistor NM 2. The cathode of the first diode D1, the cathode of the second diode D2, the positive power supply port of the first other driving circuit and the positive power supply port of the second other driving circuit are connected with a high-potential pin VCC of the full-bridge rectification chip; the source electrode of the first rectifying MOS tube NM1, the source electrode of the second rectifying MOS tube NM2, the power supply negative port of the first other driving circuit and the power supply negative port of the second other driving circuit are connected with a low potential pin GND of the full-bridge rectifying chip.

In this embodiment, the first other driving circuit and the second other driving circuit are the same, and the operating principle is that when the voltage of the input port of the other driving circuit is high potential voltage, the voltage source provided by the positive power port of the other driving circuit is used for generating starting voltage at the output port to turn on the rectifying NMOS tube connected with the other driving circuit; when the voltage of the input port of the driving circuit is low-potential voltage, the output port of the driving circuit also generates low voltage, and the rectifying NMOS tube connected with the output port of the driving circuit is closed. In order to meet the rated working voltage of the grid electrode of the rectifying NMOS tube, the starting voltage generated by the output port of the driving circuit does not exceed the maximum rated value of the grid electrode of the rectifying NMOS tube.

Fig. 13 is a specific implementation circuit of the driving circuit of the present invention, which uses a schmitt rectifier to detect the voltage of the input port, wherein when the voltage of the input port is high, the schmitt rectifier outputs high level, and conversely, outputs low level. Because the transformer winding N is crossed in the crossing period of the first isolated transmission loop and the second isolated transmission loop_SThe voltage may generate resonance, so that interference of resonance signals can be avoided by using the return difference characteristic of schmidt. The output end of the Schmitt rectifier is connected with a group of NOT gates with driving capability gradually amplified, which is a common method for improving the driving capability, and then passes through a driving resistor R_GAnd then provides a driving voltage for the rectifying NMOS tube. Drive resistor R_GAnd designing the switching speed according to the size of the rectifying NMOS tube. The NOT gates with the driving capability being amplified step by step comprise at least one NOT gate which is connected in series in sequence.

Its driving circuit of the present embodiment is not limited to the manner shown in fig. 13, and it may be applied to the present invention in the related art.

The turn-on voltage at the output port of the driving circuit of FIG. 13 is equal to VCC, i.e., the output voltage V of the converter_OUTAs described in the second embodiment, it may exceed the rated voltage of the gate of the rectifying NMOS transistor, so that the output turn-on voltage needs to be reduced, and there are many ways in the integrated circuit design, and the simplest and most straightforward way is to step down its driving circuit power supply through the linear regulator and then supply the schmitt and nor gates in fig. 13, as shown in fig. 14.

According to the working principle of the driving circuit in the fourth embodiment, the rectifier NM1 is turned on when the VD2 pin of the full-bridge rectifier chip is at a high potential, and the rectifier NM1 is turned off when the VD2 pin is at a low potential; when the pin VD1 is at high potential, the rectifier tube NM2 is turned on, and when the pin VD1 is at low potential, the rectifier tube NM2 is turned off. It can be seen that the on and off principle of the two rectifying NMOS transistors is still the same as that of the previous three embodiments, and the difference is only that an additional driving circuit is used to implement the on and off, which is the driving manner, so the rectifying process of the full-bridge rectifying chip is the same.

The above description is for the purpose of illustrating embodiments of the utility model and is not intended to limit the utility model, and it will be apparent to those skilled in the art that any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the utility model shall fall within the protection scope of the utility model.

Claims

1. A full-bridge rectifier chip is characterized by comprising a first rectifier pin, a second rectifier pin, a low potential pin, a high potential pin, a first diode, a second diode, a first rectifier MOS tube and a second rectifier MOS tube; the anode of the first diode, the drain of the first rectifying MOS tube and the gate of the second rectifying MOS tube are connected with the first rectifying pin; the anode of the second diode, the drain of the second rectifying MOS tube and the gate of the first rectifying MOS tube are connected with the second rectifying pin; the cathode of the first diode and the cathode of the second diode are connected with the high-potential pin; and the source electrode of the first rectifying MOS tube and the source electrode of the second rectifying MOS tube are connected with the low potential pin.

2. The full-bridge rectification chip according to claim 1, wherein the first diode, the second diode, the first rectification MOS transistor and the second rectification MOS transistor are fabricated on a same wafer.

3. The full-bridge rectification chip according to claim 1 or 2, further comprising a first self-driving circuit and a second self-driving circuit; the first self-driving circuit is connected between the grid electrode of the first rectifying MOS tube and the second rectifying pin, and the second self-driving circuit is connected between the grid electrode of the second rectifying MOS tube and the first rectifying pin.

4. The full-bridge rectification chip according to claim 3, wherein the first self-driving circuit and the second self-driving circuit are first driving resistors.

5. The full-bridge rectification chip according to claim 3, wherein the first self-driving circuit comprises a first driving MOS transistor, and the second self-driving circuit comprises a second driving MOS transistor; the grid electrode of the first driving MOS tube and the grid electrode of the second driving MOS tube are connected with a bias voltage source, the source electrode of the first driving MOS tube is connected with the grid electrode of the first rectifying MOS tube, and the drain electrode of the first driving MOS tube is connected with the second rectifying pin; the source electrode of the second driving MOS tube is connected with the grid electrode of the second rectifying MOS tube, and the drain electrode of the second driving MOS tube is connected with the first rectifying pin.

6. The full-bridge rectification chip according to claim 1 or 2, further comprising two other driving circuits, wherein the input port of the first other driving circuit is connected to the second rectification pin, and the input port of the second other driving circuit is connected to the first rectification pin; the output port of the first driving circuit is connected with the grid electrode of the first rectifying MOS tube; the output port of the second driving circuit is connected with the grid electrode of the second rectifying MOS tube; the power supply positive port of the first other driving circuit and the power supply positive port of the second other driving circuit are connected with the high-potential pin; and the power supply negative port of the first other driving circuit and the power supply negative port of the second other driving circuit are connected with the low-potential pin.

7. The full-bridge rectification chip according to claim 6, wherein the driving circuit comprises a Schmidt rectifier, at least one NOT gate and a second driving resistor which are connected in series in sequence; the input end of the Schmitt rectifier is used as the input end of the driving circuit, the output end of the Schmitt rectifier is connected with the input end of the at least one NOT gate which is sequentially connected in series, the output end of the at least one NOT gate which is sequentially connected in series is connected with one end of the second driving resistor, and the other end of the second driving resistor is used as the output end of the driving circuit; the power source positive port of the at least one NOT gate sequentially connected in series is used as the power source positive port of the driving circuit of the NOT gate, and the power source negative port of the at least one NOT gate sequentially connected in series is used as the power source negative port of the driving circuit of the NOT gate.

8. The full-bridge rectification chip according to claim 7, wherein the driving circuit further comprises a linear voltage regulator connected between the positive power port of the at least one not gate and the positive power port of the driving circuit.

9. A power converter is characterized by mainly comprising a transformer and the full-bridge rectifier chip of any one of claims 1 to 8, wherein a first rectifier pin of the full-bridge rectifier chip is connected with a homonymous end of a secondary winding of the transformer, a second rectifier pin of the full-bridge rectifier chip is connected with a heteronymous end of the secondary winding of the transformer, a high potential pin of the full-bridge rectifier chip is used as an output positive of the power converter, and a low potential pin of the full-bridge rectifier chip is used as an output negative ground of the power converter.

10. The power converter according to claim 9, wherein the power converter is a push-pull converter or a full-bridge converter.