CN216849870U - Silicon wafer bearing device - Google Patents

Abstract

The application discloses silicon chip bears device belongs to silicon chip processing equipment technical field. A silicon wafer bearing device comprises a base and a bracket arranged on the base; along a first direction, the support comprises a first support and a second support, a first elevation angle structure and a second elevation angle structure are arranged between the first support and the second support, and a containing space used for enabling the silicon wafer to vertically stand on the first elevation angle structure and the second elevation angle structure is formed between the first support and the second support; along the second direction, first support is equipped with first half surrounding structure and first half surrounding structure under, and the second support is equipped with first half surrounding structure of second and second half surrounding structure under, first half surrounding structure and second first half surrounding structure symmetrical arrangement, first half surrounding structure and second half surrounding structure symmetrical arrangement under. The silicon wafer bearing device can guarantee the production capacity of half silicon wafers and can improve the transmission stability of the half silicon wafers.

Description

Silicon wafer bearing device

Technical Field

The application belongs to the technical field of silicon wafer processing equipment, and particularly relates to a silicon wafer bearing device.

Background

With the rapid development of the photovoltaic industry, competition in the industry is increasingly stronger, and the requirements of related photovoltaic enterprises on improving transmission stability and capacity are higher and higher. Meanwhile, in order to improve the utilization rate of silicon raw materials, on the basis of the original square original piece blanking, a half-piece silicon piece blanking process has been developed, namely the size of the original square silicon piece is halved to be changed into a half-piece rectangular silicon piece, and vertical arrangement multi-rail transmission is adopted, so that the length of equipment is reduced, and the capacity is improved.

At present, for the automatic production equipment of the half silicon wafer battery, the rectangular half silicon wafers are mostly transmitted in the vertical long edge direction, so that the transverse direction space of the multi-rail structure cavity of the equipment is large, and the capacity is low. In addition, some equipment also adopts the minor face to transport from top to bottom to half silicon chip of rectangle structure, however this kind of device structure that adopts the minor face to transport from top to bottom in the market easily causes the silicon chip to empty about, influences transmission stability.

Therefore, how to improve the transmission stability of silicon wafer, especially half silicon wafer cell transmission, is a technical problem that needs to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned problems, the present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the utility model provides a silicon chip bears device can adapt to whole piece or half silicon chip size, can improve the silicon chip like the transmission stability of half silicon chip, and can keep the production productivity of half silicon chip, can overcome not enough among the prior art.

In order to solve the technical problem, the present application is implemented as follows:

the embodiment of the application provides a silicon chip bears device, and this silicon chip bears device includes: the device comprises a base and a bracket mounted on the base;

along a first direction, the bracket comprises a first bracket and a second bracket which are arranged at intervals, a first elevation angle structure and a second elevation angle structure which are arranged on the base and used for supporting the silicon chip are arranged between the first bracket and the second bracket, and a containing space used for enabling the silicon chip to vertically stand on the first elevation angle structure and the second elevation angle structure is formed between the first bracket and the second bracket;

along a second direction, the first bracket is provided with a first upper semi-surrounding structure and a first lower semi-surrounding structure which are arranged at intervals, the second bracket is provided with a second upper semi-surrounding structure and a second lower semi-surrounding structure which are arranged at intervals, the first upper semi-surrounding structure and the second upper semi-surrounding structure are symmetrically arranged, and the first lower semi-surrounding structure and the second lower semi-surrounding structure are symmetrically arranged;

the first direction is the extending direction of the base, and the second direction is the extending direction of the support.

In some embodiments, the first elevation structure and the second elevation structure are in contact with the silicon wafer in a point contact manner.

In some embodiments, the surfaces of the first elevation structure and the second elevation structure for contacting the silicon wafer are cambered surfaces or flat surfaces.

In some embodiments, the first elevation structure and the second elevation structure are made of a metal material or a non-metal material.

In some embodiments, the first upper semi-surrounding structure, the first lower semi-surrounding structure, the second upper semi-surrounding structure and the second lower semi-surrounding structure are all in point contact with a silicon wafer.

In some of these embodiments, the first upper semi-surrounding structure, the first lower semi-surrounding structure, the second upper semi-surrounding structure, and the second lower semi-surrounding structure are each independently U-shaped, semi-circular, or trapezoidal in shape.

In some of these embodiments, the first and second upper semi-surrounding structures are located at the top ends of the first and second brackets, respectively;

the first lower semi-surrounding structure and the second lower semi-surrounding structure are respectively positioned at the bottom, the middle or any position between the bottom and the middle of the first support and the second support.

In some embodiments, the first and second supports each comprise a front support strut and a rear support strut arranged in parallel, and the distance between the front support strut and the rear support strut is greater than 1mm and greater than the thickness of a silicon wafer;

and/or the silicon wafer is a whole silicon wafer or a half silicon wafer.

In some of these embodiments, the first and second brackets are disposed vertically on the base;

or the first support and the second support are obliquely arranged on the base at an angle.

In some embodiments, the base is provided with a plurality of first brackets and a plurality of second brackets along the first direction.

Implement the technical scheme of the utility model, following beneficial effect has at least:

in the embodiment of the application, the provided silicon wafer bearing device is characterized in that a support is mounted on a base, the support comprises a first support and a second support, a first elevation structure and a second elevation structure are mounted between the first support and the second support, the first elevation structure and the second elevation structure can be used for supporting the bottom edge of a silicon wafer to prevent the silicon wafer from contacting with a metal support, namely, the silicon wafer can be vertically erected on the first elevation structure and the second elevation structure, and the silicon wafer is located in a containing space formed between the first support and the second support; further, in order to improve the stability of silicon chip transmission or placement, the first support and the second support are respectively provided with a first upper half surrounding structure, a first lower half surrounding structure, a second upper half surrounding structure and a second lower half surrounding structure, wherein the first upper half surrounding structure and the second upper half surrounding structure are symmetrically arranged, and the first lower half surrounding structure and the second lower half surrounding structure are symmetrically arranged, so that the limitation on the silicon chip can be realized, and the inclination of the silicon chip is prevented. Therefore, the silicon wafer bearing device adopting the structure can adapt to the size of a whole silicon wafer or a half silicon wafer, can keep the production capacity of the half silicon wafer, can adapt to the requirement of improving the transmission stability of the battery transmission of the half silicon wafer, avoids the influence of the easy inclination of the silicon wafer, particularly the half silicon wafer, on the transmission stability, and has the advantages of simple structure, stability, reliability and strong adaptability.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a schematic structural diagram of a whole silicon wafer supported by a silicon wafer supporting apparatus according to some embodiments of the present invention;

fig. 2 is a schematic structural diagram of a half silicon wafer supported by a silicon wafer supporting apparatus according to some embodiments of the present invention;

fig. 3 is a schematic structural diagram of a silicon wafer carrying apparatus according to some embodiments of the present invention;

fig. 4 is a schematic view of another perspective view of a silicon wafer carrying apparatus according to some embodiments of the present invention;

fig. 5 is a schematic structural diagram of a first support in a silicon wafer carrying device according to some embodiments of the present invention;

fig. 6 is a schematic structural diagram of a silicon wafer carrying apparatus according to another embodiment of the present invention;

fig. 7 is a schematic view of another perspective view of a silicon wafer carrier according to another embodiment of the present invention.

Description of reference numerals:

100-a base;

200-a scaffold; 201-a first support; 211-a first upper semi-surrounding structure; 212-first lower semi-enclosure; 202-a second support; 221-a second upper half enclosure; 222-a second lower semi-surrounding structure; 231-front support column; 232-rear support column;

301-a first elevation configuration; 302-a second elevation configuration;

401-a whole silicon wafer; 402-half a silicon wafer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. Furthermore, the term "and/or"/"as used in the specification and claims is merely an associative relationship describing associated objects, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In the present invention, unless stated to the contrary, directional terms such as "upper, lower, left, right" are generally used with respect to the orientation shown in the drawings, or with respect to the component itself in the vertical, perpendicular, or gravitational direction. Similarly, for ease of understanding and description, the definitions of "inner and outer" are consistent with the common definitions of inner and outer, such as "inner and outer" referring to the inner and outer contours of the respective component itself, but the above directional terms are not intended to limit the present invention.

The embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

Those skilled in the art will appreciate that, as is known in the art, existing silicon wafer support or support structures suffer from certain drawbacks, to a greater or lesser extent. For example, most of the existing silicon wafer supports bear square whole silicon wafers, and are not compatible with half silicon wafers. Meanwhile, if the distance between the supporting pins is narrowed to adapt to half silicon wafers, the silicon wafer battery is easy to topple and influence the transmission stability.

Based on this, the technical scheme of this application embodiment provides silicon chip and bears device, and this silicon chip bears device is a reliable and can adapt to the bearing structure of half silicon chip battery production, not only can adapt to whole or half silicon chip size, can keep half silicon chip's production productivity moreover, can also improve the stability of silicon chip transmission, can make the high-efficient and stable transmission or deposit of silicon chip. See below for a description of specific embodiments.

Referring to fig. 1 and 2, fig. 1 shows a structural diagram of a whole silicon wafer, and fig. 2 shows a structural diagram of a half silicon wafer. The following will explain the cutting process of the whole silicon wafer and the half silicon wafer by taking single crystal silicon as an example. Typically, the silicon wafer cutting raw material is a cylindrical silicon crystal bar, and the cutting form of a square wafer is shown in fig. 1, and the material around the middle rectangle is usually removed during cutting, and the middle rectangle material is left to cut the square wafer, so that a square whole wafer 401 is obtained. Taking 182mm square pieces as an example, the utilization rate eta of the silicon rod is at the moment₁Calculated as the cross section of the silicon rod, eta₁The rectangular area/round cross section of the silicon rod is 182 × 182/52031 ≈ 63.66%.

When the half-wafer cutting process is adopted, on the basis of the original process, four leftover materials are utilized to cut the size of a half wafer along the axis direction of the silicon rod, and at the moment, a rectangular half silicon wafer 402, namely 91 × 182mm, is obtained. At this time, the utilization ratio eta of the silicon rod₂Calculated as the cross section of the silicon rod, eta₂The effective utilization area/silicon rod circular cross section is approximately equal to 43818/52031 and is approximately equal to 84.22 percent. Of course, the dimensions of the wafer are provided for illustration of the wafer dicing process and are not limited to specific wafer sizes.

Therefore, by adopting the semi-sheet cutting process, the utilization rate of the silicon rod raw materials is improved by 20.56%, and the cost of the raw materials is greatly reduced. In addition, the production by using half silicon wafers has obvious advantages: if cutting loss is reduced, subfissure is reduced, pre-sorting can be performed, the problem of flaking is solved, and the flaw-piece income is increased. These advantages also make the half-sheet a new trend in the production of battery sheets. The increasing popularity of the half silicon wafer makes the improvement of the transmission stability of the half silicon wafer more important.

Referring to fig. 3 to 7, in some embodiments of the present application, there is provided a silicon wafer carrier, including: a base 100 and a stand 200 mounted on the base 100;

along a first direction, the support 200 comprises a first support 201 and a second support 202 which are arranged at intervals, a first elevation structure 301 and a second elevation structure 302 which are installed on the base 100 and used for supporting a silicon wafer are arranged between the first support 201 and the second support 202, and a containing space for enabling the silicon wafer to vertically stand on the first elevation structure 301 and the second elevation structure 302 is formed between the first support 201 and the second support 202;

along the second direction, the first bracket 201 is provided with a first upper semi-surrounding structure 211 and a first lower semi-surrounding structure 212 which are arranged at intervals, the second bracket 202 is provided with a second upper semi-surrounding structure 221 and a second lower semi-surrounding structure 222 which are arranged at intervals, the first upper semi-surrounding structure 211 and the second upper semi-surrounding structure 221 are symmetrically arranged, and the first lower semi-surrounding structure 212 and the second lower semi-surrounding structure 222 are symmetrically arranged;

the first direction is an extending direction of the base 100, and the second direction is an extending direction of the stand 200.

The embodiment protects a silicon wafer bearing device, which can also be called a silicon wafer supporting structure, and the silicon wafer bearing device can be used for bearing or storing an entire silicon wafer 401 or a half silicon wafer 402, i.e. the silicon wafer bearing device can be used in the production process of the entire silicon wafer 401 or the half silicon wafer 402, and especially when the silicon wafer bearing device is applied to the production of the half silicon wafer 402, the problem of the transmission stability of the existing half silicon wafer can be alleviated, and the production performance of the half silicon wafer can be ensured. Specifically, the silicon wafer carrying device includes a base 100 and a support 200 mounted on the base 100, wherein the base 100 may be, for example, an elongated structure, the length of the base 100 is much greater than the width of the base 100, and the extending direction of the base 100 may be the length direction of the base 100, in this embodiment, the extending direction of the base 100 is regarded as a first direction; the stand 200 may be vertically or slightly obliquely disposed on the base 100, and the extending direction of the stand 200 may be perpendicular to (or slightly obliquely inclined to) the extending plane of the base 100, for example, when the base 100 is placed in the horizontal direction, the stand 200 extends in the longitudinal direction, and the extending direction of the stand 200 may be the height direction of the stand 200, in this embodiment, the extending direction of the stand 200 is regarded as the second direction.

Here, the width direction, the length direction, the height direction, or the like referred to herein may be determined according to actual circumstances.

Further, the bracket 200 includes a first bracket 201 and a second bracket 202, which may also be referred to as a left bracket and a right bracket, disposed at an interval. The accommodating space for accommodating the silicon wafers is arranged between the first support 201 and the second support 202, the accommodating space can be used for inserting and placing the vertically-arranged silicon wafers, and the distance between the first support 201 and the second support 202, namely the length of the accommodating space, can be adjusted according to the sizes of different silicon wafers so as to meet the use requirements of the silicon wafers with different sizes. A first elevation structure 301 and a second elevation structure 302 are further mounted on the base 100, the first elevation structure 301 and the second elevation structure 302 are located between the first support 201 and the second support 202, the first elevation structure 301 is close to the first support, the second elevation structure 302 is close to the second support, and a silicon wafer can be vertically erected on the first elevation structure 301 and the second elevation structure 302, that is, the first elevation structure 301 and the second elevation structure 302 can be used for supporting the silicon wafer to prevent the silicon wafer from contacting the metal support.

Further, the first support 201 is provided with a first upper semi-surrounding structure 211 and a first lower semi-surrounding structure 212 which are arranged at intervals, the first upper semi-surrounding structure 211 can be understood as a structure which can realize semi-surrounding to the silicon slice and is arranged at the upper part of the first support 201, and similarly, the first lower semi-surrounding structure 212 can be understood as a structure which can realize semi-surrounding to the silicon slice and is arranged at the lower part of the first support 201; the first upper half surrounding structure 211 and the first lower half surrounding structure 212 can realize half surrounding of one side of the silicon wafer. Similarly, the second bracket 202 is provided with a second upper semi-surrounding structure 221 and a second lower semi-surrounding structure 222 which are arranged at intervals, the first upper semi-surrounding structure 211 and the second upper semi-surrounding structure 221 are symmetrically arranged, and the first lower semi-surrounding structure 212 and the second lower semi-surrounding structure 222 are symmetrically arranged; the second upper semi-surrounding structure 221 and the second lower semi-surrounding structure 222 can realize semi-surrounding to the other side of the silicon wafer. Therefore, the silicon wafer is not easy to move or incline, and the transmission stability of the silicon wafer, particularly the half silicon wafer, can be improved.

This silicon chip bears device, simple structure through the setting of above-mentioned support, angle of elevation structure, half surrounding structure etc. can adapt to the size of whole piece or half silicon chip, guarantees the production productivity of half silicon chip, and adaptability improves, and stable in structure is reliable, and the silicon chip is difficult to take place to remove, can improve the transmission stability of half silicon chip.

In some cases, in this embodiment, the first elevation structure 301 and the second elevation structure 302 may be collectively referred to as an elevation structure. The first upper half surrounding structure 211 and the second upper half surrounding structure 221 may be collectively referred to as an upper half surrounding structure, the first lower half surrounding structure 212 and the second lower half surrounding structure 222 may be collectively referred to as a lower half surrounding structure, and the upper half surrounding structure and the lower half surrounding structure may be collectively referred to as a half surrounding structure.

According to the embodiment of the present application, as shown in fig. 1 and fig. 2, the silicon wafer is a whole silicon wafer 401 or a half silicon wafer 402. Namely, the silicon wafer bearing device can adapt to the size of the whole silicon wafer 401 and the size of the half silicon wafer 402, and has strong adaptability and stable and reliable structure.

In addition to the above-described embodiments, as shown in fig. 3 or 4, the first elevation structure 301 and the second elevation structure 302 are in point contact with the silicon wafer.

In the silicon wafer bearing device, the contacts of the silicon wafers are all point contacts, so that the deformation of the silicon wafers can be reduced, the transmission stability is improved, and the product quality is high.

In addition to the above embodiments, the first upper semi-surrounding structure 211, the first lower semi-surrounding structure 212, the second upper semi-surrounding structure 221, and the second lower semi-surrounding structure 222 are all in point contact with the silicon wafer.

According to this application embodiment, the silicon chip is the point contact with each angle of elevation structure and each support, also the position that the silicon chip in the device contacted is the point contact promptly, through the setting that uses symmetrical first half surrounding structure and second half surrounding structure in the support, can realize spacingly to the silicon chip, make the silicon chip be difficult to take place to remove, simple structure and reliable and stable have improved depositing or transmission stability of silicon chip, can adapt to the demand that half silicon chip transmission needs improve transmission stability, satisfy actual technology production requirement.

On the basis of the above embodiments, as shown in fig. 3 or fig. 4, the surfaces of the first elevation structure 301 and the second elevation structure 302 for contacting with the silicon wafer are cambered surfaces or flat surfaces; that is, the first elevation structure 301 and the second elevation structure 302 may be an arc-shaped structure or a flat structure. For example, the first elevation structure 301 and the second elevation structure 302 may be cylindrical support rods transversely disposed on the base 100, and the support rods may be cylindrical support rods or support rods with edges, that is, the cross section of the support rods may be circular, trapezoidal, hexagonal, or other polygonal shape. Preferably, in some embodiments, the surfaces of the first elevation structure 301 and the second elevation structure 302 for contacting the silicon wafer are cambered surfaces, and the first elevation structure 301 and the second elevation structure 302 are cylindrical support rods.

In addition to the above embodiments, the first elevation structure 301 and the second elevation structure 302 are made of a metal material or a non-metal material. Because the silicon chip is in point contact with the first elevation structure 301 and the second elevation structure 302, the first elevation structure 301 and the second elevation structure 302 can be made of various materials, and the silicon chip can be made of both metal elevation structures and nonmetal elevation structures, so that the adaptability is improved.

In addition to the above embodiments, as shown in fig. 3, the shapes of the first upper semi-surrounding structure 211, the first lower semi-surrounding structure 212, the second upper semi-surrounding structure 221, and the second lower semi-surrounding structure 222 are each independently a U shape, a semi-circle shape, a trapezoid shape, and other regular or irregular shapes. That is, the first upper semi-surrounding structure 211 may be U-shaped, or semi-circular, or trapezoidal, or other common regular or irregular shape, the first lower semi-surrounding structure 212 may be U-shaped, or semi-circular, or trapezoidal, or other common regular or irregular shape, the second upper semi-surrounding structure 221 may be U-shaped, or semi-circular, or trapezoidal, or other common regular or irregular shape, and the second lower semi-surrounding structure 222 may be U-shaped, or semi-circular, or trapezoidal, or other common regular or irregular shape. The shapes of the first upper semi-surrounding structure 211, the first lower semi-surrounding structure 212, the second upper semi-surrounding structure 221, and the second lower semi-surrounding structure 222 may be the same or different; preferably, the shape of each semi-enclosing structure is the same. More preferably, in some embodiments, the first upper semi-surrounding structure 211, the first lower semi-surrounding structure 212, the second upper semi-surrounding structure 221, and the second lower semi-surrounding structure 222 are all U-shaped structures, so that the structure is stable, the adaptability is strong, and the production and manufacturing are facilitated.

It is understood that the shape of each of the upper and lower semi-surrounding structures in the present embodiment may be various, including but not limited to the above listed U-shape, semi-circular shape or trapezoidal shape, but may also be other regular or irregular shapes similar or common in the art, and are not listed here. In particular, it is preferable that each of the upper and lower semi-surrounding structures is a symmetrical U-shaped structure, and the detailed description will be given mainly by taking each of the upper and lower semi-surrounding structures as a U-shaped semi-surrounding structure as an example.

In addition to the above embodiments, as shown in fig. 3 and 5, each of the first holder 201 and the second holder 202 includes a front support column 231 and a rear support column 232 which are arranged in parallel, and a distance between the front support column 231 and the rear support column 232 is greater than 1mm or more of a thickness of a silicon wafer. That is, each of the holders includes two support columns such as a front support column 231 and a rear support column 232, the front support column 231 and the rear support column 232 may be rod-shaped structures, and a silicon wafer is disposed between the front support column 231 and the rear support column 232. The distance between the front support column 231 and the rear support column 232 is a certain distance, which can be slightly smaller than the width of the base 100, and the distance between the front support column 231 and the rear support column 232 needs to be larger than 1mm and more than (1 mm) of the actual silicon wafer, such as the thickness of a half silicon wafer structure, for example, the distance can be larger than 1mm to 10mm of the thickness of the silicon wafer, or 1mm to 5mm, and the like. Therefore, the stability and reliability of the structure can be ensured, the storage or transmission of the silicon wafer is facilitated, and the transmission stability of the silicon wafer is improved.

Further, as shown in fig. 5, taking the first support 201 as an example, it includes a front support 231 and a rear support 232 which are arranged in parallel, the bottom ends of the front support 231 and the rear support 232 are fixedly connected with the base 100, respectively, the top ends of the front support 231 and the rear support 232 are connected with the two ends of the first upper semi-surrounding structure 211, such as a U-shaped semi-surrounding structure, respectively, thereby forming a semi-surrounding structure for the silicon chip, and the bottom ends or middle lower portions of the front support 231 and the rear support 232 may be connected with the first lower semi-surrounding structure 212 to prevent the silicon chip from tilting. The distance between the front support column 231 and the rear support column 232 may be the width of the U-shaped semi-enclosed structure.

On the basis of the above embodiments, as shown in fig. 3 or fig. 5, the first upper semi-surrounding structure 211 and the second upper semi-surrounding structure 221 are respectively located at the top ends of the first support 201 and the second support 202; that is, the first upper semi-surrounding structure 211 is provided at the top ends of the front support column 231 and the rear support column 232 in the first bracket 201, and the second upper semi-surrounding structure 221 is provided at the top ends of the front support column 231 and the rear support column 232 in the second bracket 202, which are symmetrically arranged.

In order to prevent the bottom of the silicon wafer from inclining and further improve the stability of storage or transmission of the silicon wafer, a lower semi-surrounding structure is further arranged, and the specific arrangement position of the lower semi-surrounding structure can be various and has strong flexibility. Specifically, the first lower semi-surrounding structure 212 and the second lower semi-surrounding structure 222 are respectively located at the bottom, the middle or any position (middle and lower part) between the bottom and the middle of the first bracket 201 and the second bracket 202. That is, the first lower semi-surrounding structure 212 is provided at the bottom or middle or lower portion of the front support column 231 and the rear support column 232 in the first bracket 201, and the second lower semi-surrounding structure 222 is provided at the bottom or middle or lower portion of the front support column 231 and the rear support column 232 in the second bracket 202, and the first lower semi-surrounding and the second lower semi-surrounding are symmetrically arranged. The specific arrangement position of the lower half-enclosure structure is not limited in this embodiment, as long as the requirement of improving the transmission stability provided by this embodiment can be satisfied.

In addition to the above embodiments, the first support 201 and the second support 202 are vertically disposed on the base 100; alternatively, the first bracket 201 and the second bracket 202 are disposed on the base 100 in an inclined manner at an angle. Alternatively, one of the first bracket 201 and the second bracket 202 may be disposed vertically and the other may be disposed obliquely.

Based on the arrangement of the elevation angle structure, the upper half surrounding structure, the lower half surrounding structure and the like in the silicon wafer bearing device in the embodiment, the stability and the reliability of the structure are improved, the effect of limiting the silicon wafer is achieved, the positions of the silicon wafer in the device, which are contacted with each other, are all point contacts, and the transmission stability is improved. Therefore, the requirement for the arrangement of the bracket in the device is reduced, so that the bracket can be a vertical or inclined structure with an angle, that is, the bracket (the first bracket 201 and the second bracket 202) can be vertically installed on the base 100, or can be slightly inclined installed on the base 100, as long as the requirement of improving the transmission stability provided by the embodiment can be met.

Here, the inclination angle is an angle between the support 200 and the base 100, and the angle is smaller than 90 °. Preferably, the bracket 200 is slightly inclined, i.e. the inclination angle is small, which helps to ensure the stable reliability of the structure. For example, the inclination angle may be 5 ° to 60 °, or 10 ° to 45 °, or 10 ° to 30 °, or the like.

In some embodiments, a first support 201 and a second support 202 are disposed on the base 100 along the first direction. Alternatively, as shown in fig. 6 and 7, in other embodiments, a plurality of the first brackets 201 and a plurality of the second brackets 202 are disposed on the base 100 along the first direction. Wherein a plurality means two or more.

It is understood that the number of the first brackets 201 and the second brackets 202 corresponds, that is, the first brackets 201 and the second brackets 202 are used in pairs. The number of the first support 201 and the second support 202 in the embodiment of the present application is not limited, as long as the requirement of improving the transmission stability provided by the embodiment can be satisfied. For example, in some cases, the base 100 is provided with a first support 201 and a second support 202, i.e., the supports are arranged in a single row. Alternatively, in other cases, a plurality (e.g., two, three, four or more) of the first brackets 201 and a plurality (e.g., two, three, four or more) of the second brackets 202 are disposed on the base 100, i.e., the brackets are arranged in multiple rows. Therefore, the production requirement space of the half silicon wafer battery can be met, and the actual process production requirement can be met.

In some embodiments, as shown in fig. 6 and 7, the brackets 200 are arranged in a plurality of rows, and along the first direction, two first brackets 201 and two second brackets 202, or three first brackets 201 and three second brackets 202, or four first brackets 201 and four second brackets 202 are disposed on the base 100.

To sum up, the silicon wafer bearing device provided by the embodiment of the application can be used for bearing a whole silicon wafer or a half silicon wafer when in use. If when accepting rectangular half silicon chip, half silicon chip can adopt the minor face to transmit from top to bottom, be about to half silicon chip and place at first angle of elevation structure and second angle of elevation structure, and half silicon chip is arranged in the accommodation space that first support and second support formed, half silicon chip and each angle of elevation structure and each support are the point contact, the position that also the silicon chip in the device contacted is the point contact promptly, the first half surrounding structure of symmetry and the setting of second half surrounding structure through first support and second support setting, can realize spacingly to the silicon chip, make the battery piece be difficult to take place to remove, stable in structure is reliable, the storage or the transmission stability of silicon chip has been improved, can adapt to half silicon chip transmission and need the demand that improves transmission stability, satisfy actual technology production requirement. In addition, the support can adopt the mode of arranging of single-row or multiseriate formula to satisfy the space of half silicon chip battery production demand or satisfy the productivity requirement, adaptability is stronger.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. The silicon wafer bearing device is characterized by comprising a base and a bracket arranged on the base;

along a first direction, the bracket comprises a first bracket and a second bracket which are arranged at intervals, a first elevation angle structure and a second elevation angle structure which are arranged on the base and used for supporting the silicon chip are arranged between the first bracket and the second bracket, and a containing space used for enabling the silicon chip to vertically stand on the first elevation angle structure and the second elevation angle structure is formed between the first bracket and the second bracket;

along a second direction, the first bracket is provided with a first upper semi-surrounding structure and a first lower semi-surrounding structure which are arranged at intervals, the second bracket is provided with a second upper semi-surrounding structure and a second lower semi-surrounding structure which are arranged at intervals, the first upper semi-surrounding structure and the second upper semi-surrounding structure are symmetrically arranged, and the first lower semi-surrounding structure and the second lower semi-surrounding structure are symmetrically arranged;

the first direction is the extending direction of the base, and the second direction is the extending direction of the support.

2. The silicon wafer carrier device according to claim 1, wherein the first elevation structure and the second elevation structure are in point contact with the silicon wafer.

3. The silicon wafer carrier device according to claim 1, wherein the surfaces of the first elevation structure and the second elevation structure for contacting the silicon wafer are cambered surfaces or flat surfaces.

4. The silicon wafer carrier device of claim 1, wherein the first elevation structure and the second elevation structure are made of metal or nonmetal.

5. The silicon wafer carrier device according to claim 1, wherein the first upper semi-surrounding structure, the first lower semi-surrounding structure, the second upper semi-surrounding structure and the second lower semi-surrounding structure are all in point contact with the silicon wafer.

6. The silicon wafer carrier device of claim 1, wherein the first upper semi-surrounding structure, the first lower semi-surrounding structure, the second upper semi-surrounding structure, and the second lower semi-surrounding structure are each independently U-shaped, semi-circular shaped, or trapezoidal shaped.

7. The silicon wafer carrier device according to claim 1, wherein the first upper semi-surrounding structure and the second upper semi-surrounding structure are respectively positioned at the top ends of the first support and the second support;

the first lower semi-surrounding structure and the second lower semi-surrounding structure are respectively positioned at the bottom, the middle or any position between the bottom and the middle of the first support and the second support.

8. The silicon wafer carrier device according to claim 1, wherein the first support and the second support each comprise a front support column and a rear support column arranged in parallel, and the distance between the front support column and the rear support column is greater than 1mm and more than the thickness of a silicon wafer;

and/or the silicon wafer is a whole silicon wafer or a half silicon wafer.

9. The silicon wafer carrier device according to any one of claims 1 to 8, wherein the first support and the second support are vertically disposed on the susceptor;

or the first support and the second support are obliquely arranged on the base at an angle.

10. The silicon wafer carrier device according to any one of claims 1 to 8, wherein a plurality of the first supports and a plurality of the second supports are provided on the susceptor along the first direction.

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