CN216818279U

CN216818279U - Integrated chip with test circuit

Info

Publication number: CN216818279U
Application number: CN202220948896.6U
Authority: CN
Inventors: 阳冠欧; 金慧娇
Original assignee: Beijing Xingeno Microelectronics Co ltd
Current assignee: Beijing Xingeno Microelectronics Co ltd
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2022-06-24
Anticipated expiration: 2032-04-24

Abstract

The utility model discloses an integrated chip with a test circuit, wherein the integrated chip 1 comprises a low-voltage stabilizing circuit 2, a low-voltage stabilizing circuit input pin 3, a low-voltage stabilizing circuit output pin 4, a comparator circuit 5 and a main controller 6; the input end of the low-voltage stabilizing circuit 2 is connected with an input pin 3 of the low-voltage stabilizing circuit; the output end of the low-voltage stabilizing circuit 2 is connected with an output pin 4 of the low-voltage stabilizing circuit; one input end of the comparator circuit 5 is connected to the output end of the low voltage stabilizing circuit 2, and the other input end of the comparator circuit 5 is connected to the input end of the low voltage stabilizing circuit 2; the output end of the comparator circuit 5 is connected with the main controller 6, so that the judgment signal is transmitted to the main controller 6.

Description

Integrated chip with test circuit

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to an integrated chip with a test circuit.

Background

As the chip fabrication process gets smaller and larger, testing of the chip becomes more and more difficult. As an important link for ensuring the product yield and cost management, the test becomes a large core which cannot be ignored. DFT (design for test) is a concept that arises with the advent of testing and is becoming a key element in chip design. DFT refers to the insertion of various hardware logics for improving the testability (including controllability and observability) of a chip in the original design stage of the chip, so as to generate test vectors and achieve the purpose of testing a large-scale chip. After the chip is manufactured, some additional self-test circuits added in the design of the chip need to be tested, and only necessary control signals need to be applied from the outside during testing, and the defects or faults of the tested circuit are checked by running built-in self-test hardware and software. In order to perform a functional test (normal mode) on a normal circuit of a chip during a chip test, a test mode (testmode) of the chip needs to be entered during the test. In the traditional test mode design, pins of a test circuit are reserved on a chip at the beginning of chip design, so that the number of the pins of the chip is greatly increased, and the requirement on chip integration is greatly influenced. Therefore, a novel chip which can save the number of chip pins and can simultaneously realize that the chip enters a test mode is needed in the prior art.

SUMMERY OF THE UTILITY MODEL

The technical object of the present invention is to provide a novel chip, which can enter a test mode without using additional test pins.

The utility model provides an integrated chip with a test circuit according to the technical purpose, wherein the integrated chip 1 comprises a low voltage stabilizing circuit 2, a low voltage stabilizing circuit input pin 3, a low voltage stabilizing circuit output pin 4, a comparator circuit 5 and a main controller 6; the input end of the low-voltage stabilizing circuit 2 is connected with an input pin 3 of the low-voltage stabilizing circuit; the output end of the low-voltage stabilizing circuit 2 is connected with an output pin 4 of the low-voltage stabilizing circuit;

one input end of the comparator circuit 5 is connected to the output end of the low voltage stabilizing circuit 2, and the other input end of the comparator circuit 5 is connected to the input end of the low voltage stabilizing circuit 2; the output end of the comparator circuit 5 is connected with the main controller 6, so that the judgment signal is transmitted to the main controller 6.

In one embodiment, when the integrated chip is tested, the output pin 4 of the low voltage stabilizing circuit is externally connected with a voltage source.

The utility model is characterized in that the utility model utilizes the circuit characteristic of the low voltage stabilizing circuit in the integrated chip to enable the low voltage stabilizing circuit to achieve the effect that the output voltage is less than the input voltage by applying voltage externally, and starts the test mode of the integrated chip according to the effect. By the technical means, the test pins and the test starting circuit of the integrated chip can be saved, so that the technical effects of simplifying the integrated chip circuit and saving the pins of the integrated chip are achieved.

Additional features and advantages of the utility model will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model. The objectives and other advantages of the utility model will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the principles of the utility model and not to limit the utility model. In the drawings:

FIG. 1 is a schematic diagram of an integrated chip with test circuitry according to the present invention;

FIG. 2 is a timing diagram of voltage signals when an integrated chip according to the present invention is in a normal operating mode;

FIG. 3 is a timing diagram of voltage signals when an integrated chip according to the present invention is in a test mode.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings.

The integrated chip 1 with the test circuit in this embodiment includes a low voltage regulator circuit 2, a low voltage regulator circuit input pin 3, a low voltage regulator circuit output pin 4, a comparator circuit 5, and a main controller 6.

The utility model improves the mode of entering the chip into the test mode by utilizing the performance of a low-voltage regulator (LDO)2 in the chip. The low voltage stabilizing circuit 2 has the characteristic that the input voltage value Vin of the low voltage stabilizing circuit is greater than the output voltage value Vout of the low voltage stabilizing circuit under the normal working mode, namely, Vin is greater than Vout. In the utility model, a voltage source is applied to the output pin 4 of the low voltage stabilizing circuit 2, and the input pin 3 of the low voltage stabilizing circuit is not connected with a potential to keep the low voltage stabilizing circuit in a floating state (floating). And one input terminal of the comparator circuit 5 is connected to the output terminal of the low voltage stabilizing circuit 2, and the other input terminal of the comparator circuit 5 is connected to the input terminal of the low voltage stabilizing circuit 2. The comparator circuit 5 will compare the input voltage value Vin and the output voltage value Vout of the low voltage stabilizing circuit 2, and the judgment signal outputted by the comparator circuit 5 is transmitted to the main controller 6 for analysis and judgment. If Vin is less than or equal to Vout, the chip is judged to enter a test mode, and if Vin is more than Vout, the chip is judged to enter a normal working mode.

Fig. 2 is a timing diagram of voltage signals when the chip is in a normal operation mode. When the chip is in a normal working mode, the chip pressurizes an input voltage value Vin to 15V through an external power supply through an input pin 3 of a low-voltage stabilizing circuit, the potential of an output voltage value Vout of an output pin 4 of the low-voltage stabilizing circuit is gradually high and stabilized at 5V, when the voltage of the output voltage value Vout rises to 4.3V, a power-on reset signal is started, a circuit inside the chip starts to be powered on, a comparator circuit 2 compares the potential of the input voltage value Vin with the potential of the output voltage value Vout, and when the input voltage value Vin is larger than the output voltage value Vout, the comparator circuit 2 outputs a low-level time sequence signal. And when the potential of the output voltage value Vout is stabilized at 5V for a certain time, the main controller 6 can send out relevant instructions through the logic circuit, when the chip enters a normal working mode, the chip starts to work normally.

Fig. 3 is a timing diagram of voltage signals when a chip enters a test mode, in order to enable the chip to enter the test mode, first, an input pin 3 of a low voltage stabilizing circuit is in a suspended state, an output pin 4 of the low voltage stabilizing circuit gradually rises from 0V to output voltage value Vout, when the voltage of the output voltage value Vout rises to 4.3V, a power-on reset signal is turned on, at this time, a circuit inside the chip starts to be powered on, a comparator circuit 2 compares the potential of the input voltage value Vin with the potential of the output voltage value Vout, and when the input voltage value Vin is smaller than the output voltage value Vout, the comparator circuit 2 outputs a high-level timing signal. And when the output voltage Vout is stabilized at 5V for a certain time, the main controller 6 will issue related instructions through the logic circuit, and the chip enters the test mode.

In the process of entering the test mode, the integrated chip does not depend on arranging independent test mode signal pins on the integrated chip, so that the number of pins of the integrated chip is reduced, the related circuit design for starting the test mode is simplified, the design area of the chip is reduced, and the cost is saved.

Claims

1. An integrated chip with a test circuit is characterized in that the integrated chip (1) comprises a low-voltage stabilizing circuit (2), a low-voltage stabilizing circuit input pin (3), a low-voltage stabilizing circuit output pin (4), a comparator circuit (5) and a main controller (6); the input end of the low-voltage stabilizing circuit (2) is connected with an input pin (3) of the low-voltage stabilizing circuit; the output end of the low-voltage stabilizing circuit (2) is connected with an output pin (4) of the low-voltage stabilizing circuit;

one input end of the comparator circuit (5) is connected to the output end of the low-voltage stabilizing circuit (2), and the other input end of the comparator circuit (5) is connected to the input end of the low-voltage stabilizing circuit (2); the output end of the comparator circuit (5) is connected with the main controller (6), so that the judgment signal is transmitted to the main controller (6).

2. The integrated chip with the test circuit according to claim 1, wherein the output pin (4) of the low voltage regulator circuit is externally connected with a voltage source when the integrated chip is tested.