CN216816864U - Test board and test system - Google Patents
Test board and test system Download PDFInfo
- Publication number
- CN216816864U CN216816864U CN202122406384.5U CN202122406384U CN216816864U CN 216816864 U CN216816864 U CN 216816864U CN 202122406384 U CN202122406384 U CN 202122406384U CN 216816864 U CN216816864 U CN 216816864U
- Authority
- CN
- China
- Prior art keywords
- test
- board
- tested
- chip
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The test board and the test system provided by the application are characterized in that the test board is applied to testing of a chip to be tested integrated on a board to be tested, a test connector connected with the chip to be tested is arranged on the board to be tested, and the test board comprises a test seat, a connector and a serial peripheral interface which are sequentially connected; the connector is detachably connected with the test connector; the serial peripheral interface is used for externally connecting control equipment; the test seat is used for externally connecting a signal tester; when the control equipment sends a control signal to the chip to be tested through the serial peripheral interface, the chip to be tested outputs a corresponding working signal to the signal tester through the test socket based on the control signal. Furthermore, through the detachable connection mode, the test board and the board to be tested are connected together to realize chip testing, and after the testing is finished, the test board can also realize the testing of other chips through the connector, so that the testing cost is saved.
Description
Technical Field
The application relates to the field of testing, in particular to a testing board and a testing system.
Background
At present, before a chip is used, in order to ensure whether each index parameter or function of the chip meets the requirement, the chip is usually required to be tested.
In the related art, when testing a chip, test environments such as the chip and a test circuit required by the chip test are usually integrated on the same test board, and whether each index parameter or function of the chip meets the use requirement is determined by analyzing a working signal generated by the chip.
However, when the chip is tested by the chip testing method, the chip is directly welded on the testing board, so that the subsequent testing board cannot test other chips, and the testing cost of the chip is increased.
SUMMERY OF THE UTILITY MODEL
The application provides a test board and a test system, which are used for solving the problem that the test cost of a chip is higher when the chip and the test board are integrated on a circuit board in the related technology.
In a first aspect, the application provides a test board, which is applied to test a chip to be tested integrated on a board to be tested, wherein the board to be tested is provided with a test connector connected with the chip to be tested, and the test board comprises a test seat, a connector and a serial peripheral interface which are sequentially connected;
the connector is detachably connected with the test connector; the serial peripheral interface is used for externally connecting control equipment; the test seat is used for externally connecting a signal tester;
when the control equipment sends a control signal to the chip to be tested through the serial peripheral interface, the chip to be tested outputs a corresponding working signal to the signal tester through the test socket based on the control signal.
In some embodiments of the present application, the test plate further comprises: the chip to be detected is a sensor chip, and the working signal corresponding to the chip to be detected comprises an intermediate frequency signal.
In some embodiments of the present application, the board under test further comprises: the sensor chip includes a millimeter wave radar chip.
In some embodiments of the present application, the test socket includes a plug interface, and the plug interface of the test socket is connected to the connector.
In some embodiments of the present application, the connector includes a connection line interface, and the connector is detachably connected to the connection line interface of the test connector through the connection line interface and the connection line.
In some embodiments of the present application, the connector includes a socket, and the connector is detachably connected to the socket of the test connector through the socket.
In some embodiments of the present application, the test plate further comprises: a first power supply;
the first power supply is connected with the test socket and used for supplying power to the test socket.
In some embodiments of the present application, the connector supports at least one of the following types of chips under test: 2T4R chips, 4T4R chips, and 4T8R chips.
In some embodiments of the present application, the test plate comprises: the test socket comprises a plurality of connectors, a plurality of test sockets in one-to-one correspondence with the connectors, and a plurality of serial peripheral interfaces in one-to-one correspondence with the connectors.
In a second aspect, the present application provides a test system comprising: a board to be tested, a control device, a signal tester and any one test board according to the first aspect are integrated with a chip to be tested; wherein the content of the first and second substances,
the test board is detachably connected with the test chip on the board to be tested through the connector and is used for testing the chip to be tested;
the serial peripheral interface is connected with the control equipment and used for receiving a control signal sent by the control equipment;
the test seat is connected with the signal tester and used for receiving working signals output by the chip to be tested based on the control signals.
In some embodiments of the present application, the chip to be tested is disposed on the first surface of the board to be tested, and the test connector is disposed on the second surface of the board to be tested.
In some embodiments of the present application, the board under test further comprises: a second power supply; and the second power supply is connected with the chip to be tested and used for supplying power to the chip to be tested.
In some embodiments of the present application, the second power supply is disposed at the second face of the board under test, and the second power supply is disposed outside an overlapping area formed on the board under test when the test connector is connected with the connector.
The test board and the test system provided by the application are characterized in that the test board is applied to testing of a chip to be tested integrated on a board to be tested, a test connector connected with the chip to be tested is arranged on the board to be tested, and the test board comprises a test seat, a connector and a serial peripheral interface which are sequentially connected; the connector is detachably connected with the test connector; the serial peripheral interface is used for externally connecting control equipment; the test seat is used for externally connecting a signal tester; when the control equipment sends a control signal to the chip to be tested through the serial peripheral interface, the chip to be tested outputs a corresponding working signal to the signal tester through the test socket based on the control signal. Furthermore, through the detachable connection mode, the test board and the board to be tested are connected together to realize chip testing, and after the testing is finished, the test board can also realize the testing of other chips through the connector, so that the testing cost is saved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of a test board according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of another test board provided in the present embodiment;
FIG. 3 is a schematic view of another exemplary embodiment of a test board;
FIG. 4 is a schematic diagram of a connection of a test board according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a board to be tested according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a test system according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of another board to be tested according to an embodiment of the present application.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
At present, in the process of testing a chip, the chip and an external circuit structure for testing the chip are generally integrated on the same test board, so as to test the functions of the chip.
However, when the chip is tested by the method, after the test is completed, the chip to be tested is directly welded on the test board, so that the subsequent test board cannot be reused, and the test cost of the chip is increased. The application provides a test board and test system, aims at solving prior art technical problem as above.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a test board according to an embodiment of the present disclosure, where the test board is used to test a chip to be tested integrated on a board to be tested. As shown in fig. 1, in this embodiment, a test connector connected to a chip to be tested is disposed on a board to be tested, and the test board further includes: the test socket, the connector and the serial peripheral interface are connected in sequence. The connector is detachably connected with the test connector, and the serial peripheral interface is used for externally connecting control equipment; the test seat is used for externally connecting a signal tester. When the control equipment sends a control signal to the chip to be tested through the serial peripheral interface, the chip to be tested outputs a corresponding working signal to the signal tester through the test socket based on the control signal.
For example, the connectors in the test board provided in this embodiment may be detachably connected together through the test connectors on the board to be tested, and when the chip to be tested is tested, the connectors on the test board and the test connectors on the board to be tested may be used to transmit signals generated during the test process.
Specifically, the connector on the test board is connected to the test socket and the serial peripheral interface, respectively. Wherein, the test socket is used for connecting the signal tester of outside. In one example, an external signal tester connected to the test socket can display a working signal output by the chip to be tested in real time, so that a tester can detect the chip to be tested according to the displayed working signal. In another example, the external signal tester connected to the test socket can automatically analyze whether the chip to be tested meets the test requirements according to the received working signal.
And a serial peripheral interface is also arranged on the test board and connected with the connector for externally connecting the control equipment. In one example, the control device outside the spi may be configured to send a control signal to the spi, where the control signal may be configured to configure an address of a register in the chip to be tested, thereby further determining a type of a working signal sent by the chip to be tested to the test board.
In practical application, before testing a chip to be tested, the board to be tested and the test board are connected together through the test connector on the board to be tested and the connector on the test board, the serial peripheral interface on the test board is connected to the control device, and the test socket on the test board is connected to the signal tester. In the process of testing a chip to be tested, the serial peripheral interface can be used for receiving a control signal sent by control equipment connected with the serial peripheral interface, then the control signal is transmitted to a connector on a board to be tested connected with the serial peripheral interface, and then the control signal is sent to the chip to be tested connected with the test connector through the connector and a test connector on the board to be tested connected with the connector, so that the chip to be tested is controlled to generate a corresponding working signal, and the working signal is transmitted to a signal tester connected with the test socket through the test connector, the connector and the test socket which are sequentially connected, so that the signal tester displays the received working signal or the signal tester directly analyzes the received working signal to obtain a signal analysis result.
In this embodiment, when testing the chip to be tested, the board to be tested and the test board can be detachably connected together through the connector and the test connector, so that after the chip test is finished, the test board and the board to be tested can be connected through the disconnection connector and the test connector, and the test board can be used for testing other chips. Compared with the testing method of the chip to be tested in the related art, the board to be tested integrated with the chip to be tested in the application can be directly integrated in an actual product, wherein the testing connector on the board to be tested can be used for transmitting signals generated by the chip on the board to be tested when being integrated into the actual product, and when the chip on the board to be tested needs to be tested, the chip to be tested on the board to be tested does not need to be disassembled, and the testing connector can be directly applied to a testing process according to the testing connector on the board to be tested and used for transmitting working signals generated by the chip in the testing process. After the test is completed, the test board and the board to be tested can be directly disconnected through the connector and the test connector, and then the board to be tested can be applied to an actual product. And among the correlation technique, when will await measuring the chip beading on surveying the board, after the chip test is accomplished, the chip that welds on waiting to survey the board in order to avoid the chip to cause the damage to the chip in the dismantlement process from surveying the board, consequently after the test is accomplished, can abandon this test chip, the board that waits to survey in this application still can directly use to reduce test cost.
In some embodiments, the chip to be tested integrated on the board to be tested is a sensor chip, and the working signal corresponding to the chip to be tested includes an intermediate frequency signal.
In some embodiments, the sensor chip comprises a millimeter wave radar chip.
Specifically, when the chip to be detected is a millimeter wave radar chip, a plurality of transmitting and receiving paths can be arranged in the millimeter wave radar chip, and the millimeter wave radar chip can be used for realizing accurate positioning of the distance, the speed, the angle, the position and the like of an object monitored by the millimeter wave radar chip. When the millimeter wave radar chip is tested, the method can be used for testing intermediate frequency signals generated by the millimeter wave radar.
For example, in a specific testing process, the control device externally connected to the serial peripheral interface on the testing board may be configured to send a control signal to the millimeter wave radar chip through the serial peripheral interface, the connector, and the testing connector, which are connected in sequence. For example, the control signal may be used to place the millimeter wave radar chip in a transmit mode. Later, the intermediate frequency signal that millimeter wave radar chip can produce is through test connector, the test socket that connects gradually, transmits to the signal tester who is connected with the test socket, detects the intermediate frequency signal of millimeter wave radar output through the signal tester, and then the signal tester can be based on each item index parameter to the intermediate frequency signal that receives and carry out the analysis, and then confirms whether current millimeter wave radar chip can the job requirement.
In one example, on a board to be tested, an intermediate frequency signal of a chip to be tested may be transmitted by using an LVDS (Low-Voltage Differential Signaling) transmission technology, for example, radar data output by a millimeter wave radar chip may be transmitted to an LVDS converter for data processing, and then the processed data is transmitted to a test board through a test connector, so as to reduce power consumption of a working signal during transmission, and the data transmission is not easily affected by noise.
In some embodiments, the test socket includes a plug interface, and the plug interface of the test socket is connected to the connector.
Specifically, fig. 2 is a schematic structural diagram of a test board according to an embodiment of the present disclosure. As shown, a plurality of plug interfaces may be disposed in the test socket. And the pins of the connector are correspondingly connected with the sockets in the test socket one by one. For example, the test socket in the figure is provided with 8 round hole type plug interfaces, and the pins of the connector on the test board are electrically connected with the 8 round hole type plug structures in a one-to-one correspondence manner. When the connector on the test board can support the parallel transmission of the working signals of the 8-channel chip, the 8-channel signals can be displayed and analyzed through the test socket and the signal tester connected with the test socket correspondingly in the test socket connected with the connector.
In some embodiments, the connector may support at least one of the following types of chips under test at the time of a particular test: the chip comprises a two-path transmitting four-path receiving 2T4R chip, a four-path transmitting four-path receiving 4T4R chip and a four-path transmitting eight-path receiving 4T8R chip.
In one example, when the test socket includes the plug structure with 8 round holes as shown in fig. 2, the corresponding connector can support the 4T8R chip. In addition, the connector can be used for supporting chip testing of a cascade stage, for example, signal transmission when two 2T4R chips with two-path transmission and four-path reception are cascaded together can be supported.
In some embodiments, the test plate may have disposed thereon: the test socket comprises a plurality of connectors, a plurality of test sockets in one-to-one correspondence with the connectors, and a plurality of serial peripheral interfaces in one-to-one correspondence with the connectors. Wherein, each connector is connected with the corresponding connector and the corresponding test socket.
For example, fig. 3 is a schematic structural diagram of another test board according to an embodiment of the present disclosure. Fig. 3 includes two connectors, two serial peripheral interfaces correspondingly connected to the two connectors, and two test sockets. Based on the structure shown in fig. 3, fig. 4 is a schematic connection diagram of a test board according to an embodiment of the present application. As shown in the figure, one connector can support 8-channel signal transmission, the test socket corresponding to the connector includes 8 plugging interfaces, and pins of the connector are electrically connected with the 8 round-hole plugging structures in a one-to-one correspondence manner. The other connector can support 4-path signal transmission, a test seat corresponding to the connector comprises 4 plugging interfaces, pins of the connector are electrically connected with the 4 round-hole type plugging structures in a one-to-one correspondence mode, and the connector can support at least one type of chips to be tested: the chip comprises a 2T4R chip for two-way transmission and four-way reception and a 4T4R chip for four-way transmission and four-way reception. It should be noted that, in the actual test board, the number of signal transmissions supported by the plurality of connectors may be the same or different, and is not limited herein.
In this embodiment, the test board includes two different connectors, wherein each connector can support different types of chips for testing. In addition, during actual testing, the connectors on the test board can be respectively connected to different boards to be tested, so that the same test board can simultaneously realize testing of different types of chips. It should be noted that, in practical applications, the connection manner of the connector on the test board is not particularly limited, and the number of signals that can be supported by the connector is also not particularly limited. Moreover, the types of connectors on the test board can be replaced or added according to actual conditions so as to be suitable for different chip types. That is, the compatibility of the test board in this embodiment is strong, and the test board can be used subsequently all the time.
In some embodiments, the connector includes a patch cord interface, the connector being removably connectable to the patch cord interface of the test connector by the patch cord interface, the patch cord.
Specifically, the test board provided in this embodiment may be connected to a test connector on the board to be tested through a connector on the test board, where the connector and the test connector may be connected together in a wire connection manner. During actual connection, a connecting line interface is arranged on the connector, and one end of the connecting line can be detachably connected with the connector through the connecting line interface on the connector. And at the other end of the connecting wire, the test connector is connected with the other end of the connecting wire in a pluggable manner through a connecting wire interface on the test connector. And then the test board and the board to be tested are connected together through the connector and the connector. In practical application, the connection interface of the connector and one end of the connection line are male and female interfaces. The connecting interface of the test connector and the other end of the connecting line are male and female interfaces.
In this embodiment, the test board and the connector on the board to be tested are connected together in a wiring manner, so as to realize the remote connection between the test board and the board to be tested.
In some embodiments, the connector includes a socket through which the connector is removably connectable to the socket of the test connector.
Specifically, in this embodiment, a socket is disposed on the connector on the test board, and the connector can be connected to the socket of the test connector on the chip to be tested through the socket. In one example, the connector and the test connector may be a male-female header board-level socket, and the connector and the test connector may be directly plugged together to connect the test board and the board to be tested.
In this embodiment, the test board and the board to be tested can be directly connected through the sockets on the respective connectors. Compared with the connection of the test board and the board to be tested by adopting a wiring mode, the connection mode in the embodiment can realize the connection without an additional connecting wire. However, in some examples, for example, when the board to be tested needs to be placed in the incubator for testing, that is, when the working signals of the chip to be tested at different temperatures need to be tested, the board to be tested may be placed in the incubator, the test board may be placed outside the incubator, and the board to be tested and the test board may be connected by using the wire type connector, thereby completing the chip testing.
In some embodiments, the connection modes of the plurality of connectors on the test board may be different, so that the test board may meet the test connector interface with different boards to be tested, thereby improving the compatibility of the test board.
On the basis of the above embodiment, the test board further includes a first power supply, wherein the first power supply is connectable to the test socket on the test board, and the first power supply is configured to supply power to the test socket on the test board.
In one example, when the test socket is externally connected with the rest equipment, the first power supply can supply power to the rest equipment.
In another example, the first power supply on the test board may also supply power to the chip to be tested on the board to be tested through the connector.
Fig. 5 is a schematic structural diagram of a board to be tested according to an embodiment of the present application, and as shown in fig. 5, the board to be tested includes: testing the connector and the chip to be tested;
the test connector is provided with a connecting wire interface, the test connector is detachably connected to one end of a connecting wire through the connecting wire interface, and the other end of the connecting wire is used for being detachably connected to the first connector of the test board; the test board is provided with a test seat, and a plug interface of the test seat is connected with the connector; the serial peripheral interface on the test board is connected with the connector and used for externally connecting the control equipment;
when the serial peripheral interface is externally connected to the control equipment and the connector on the test board is connected to the test connector on the board to be tested through the connecting line, the chip to be tested receives a control signal sent to the serial peripheral interface by the control equipment through the test connector and outputs a corresponding working signal based on the control signal; the test connector sends a working signal to the connector and transmits the working signal to a signal tester connected to the test socket through the test socket so that the signal tester displays the working signal.
For example, the board under test provided in this embodiment may be connected to the connector on the test board through the test connector on the board under test, wherein the connector and the test connector are connected together in a wire connection manner. Specifically, a connection interface is arranged on the test connector, and one end of the connection line can be detachably connected with the connection line through the connection interface on the test connector. At the other end of the connecting wire, the connector on the test board is connected with the other end of the connecting wire in a pluggable manner through the connecting wire interface on the connector. And then the test board is connected with the board to be tested through the connector and the test connector. In practical application, the connection interface of the connector and one end of the connection line are male and female interfaces. The connecting interface of the test connector and the other end of the connecting line are male and female interfaces.
Specifically, the testing process of the chip testing is similar to the testing process in the above embodiments, and is not repeated here.
In one example, on a board to be tested, a working signal of a chip to be tested may be transmitted by using an LVDS (Low-Voltage Differential Signaling) transmission technology, so that power consumption of the working signal in a transmission process is reduced, and the working signal is not easily affected by noise.
In this embodiment, the board to be tested is connected to the test board through the connector, so that after the chip test is finished, the test board and the board to be tested can be connected through the disconnected connector, and the test board can be used for testing other chips. On the other hand, the connector between the test board and the board to be tested in the embodiment is connected through the connection interface and the connection line on the connector, so that the remote connection between the test board and the board to be tested can be realized.
In some embodiments, the test connectors on the board under test and the connectors on the test board may be connected by sockets. Specifically, the test connector is provided with a socket, and the test connector is connected with the socket of the connector of the test board through the socket.
In addition, in some embodiments, the board under test may also be provided with a plurality of different types or different numbers of connectors to facilitate connection with the test board.
Fig. 6 is a schematic structural diagram of a test system according to an embodiment of the present application, where as shown in the drawing, the test system includes: the test board comprises a board to be tested, a control device, a signal tester and the test board in any one of the above embodiments, wherein the board to be tested, the control device and the signal tester are integrated with the chip to be tested.
In the test system, a test board is detachably connected with a test chip on a board to be tested through a connector and is used for testing the chip to be tested; the serial peripheral interface is connected with the control equipment and is used for receiving a control signal sent by the control equipment; the test seat is connected with the signal tester and used for receiving working signals output by the chip to be tested based on the control signals.
For example, in the test system in this embodiment, a chip to be tested and a test connector connected to the chip to be tested are disposed on the board to be tested. And the test board is provided with a serial peripheral interface, a connector and a test seat which are connected in sequence.
Specifically, the connector on the test board is connected to the test socket and the serial peripheral interface, respectively. The test socket is used for connecting a plug interface of an external signal tester. In one example, an external signal tester connected to the test socket can display a working signal output by the chip to be tested in real time, so that a tester can detect the chip to be tested according to the displayed working signal. In another example, the external signal tester connected to the test socket may automatically analyze whether the chip to be tested meets the test requirements according to the received working signal, for example, the signal tester that is eaten next time in practical application may be a spectrum analyzer, and then detects parameters such as power, receiving gain, receiving sensitivity, noise coefficient, and the like in the working limit number output by the chip to be tested.
And a serial peripheral interface is also arranged on the test board, and the serial peripheral interface is connected with the connector and is used for externally connecting control equipment. In one example, the serial peripheral interface is externally connected with a control device, and the control device is configured to send a control signal to the serial peripheral interface, where the control signal may be used to configure an address of a register in the chip to be tested, so as to further determine a type of a working signal sent by the chip to be tested to the test board.
In practical application, before testing a chip to be tested, the board to be tested and the test board are connected together through a test connector on the board to be tested and a connector on the test board, a serial peripheral interface on the test board is connected to the control device, and a test socket on the test board is connected to the signal tester. In the process of testing a chip to be tested, the serial peripheral interface can be used for receiving a control signal sent by control equipment connected with the serial peripheral interface, then the control signal is transmitted to a connector on a board to be tested connected with the serial peripheral interface, then the control signal is sent to the chip to be tested connected with the test connector through the connector and a test connector on the board to be tested connected with the connector, the chip to be tested is further controlled to generate a corresponding working signal, and the working signal is transmitted to a signal tester connected with the test socket through the test connector, the connector and the test socket which are sequentially connected, so that the signal tester displays the received working signal or directly analyzes the received working signal according to the signal tester to obtain a signal analysis result.
In some embodiments, in order to facilitate the connection between the board to be tested and the test board, when the chip is tested, the chip is disposed on the first surface of the board to be tested, and the test connector is disposed on the second surface of the board to be tested.
Illustratively, the board to be tested includes two surfaces, a first surface of the board to be tested and a second surface of the board to be tested. Specifically, when the board to be tested is designed specifically, the chip to be tested and the test connectors on the board to be tested can be arranged on two sides of the board to be tested respectively, namely the chip to be tested is arranged on the first surface of the board to be tested, and the connectors on the board to be tested are arranged on the second surface, so that the connection between the board to be tested and the board to be tested is facilitated.
In this embodiment, on the board to be tested, the chip to be tested and the connectors on the test board are respectively disposed on two sides of the board to be tested. Through foretell mode of setting up, on the one hand, can conveniently wait to examine the board and be connected with surveying the board, avoid when two circuit boards are connected, because the chip that awaits measuring highly too high makes two circuit boards can't connect completely. On the other hand, the circuit structure on the board to be tested and the test board can be prevented from interfering signals received or generated in the chip test process, and the accuracy of chip test is improved.
In some embodiments, the board to be tested is further provided with: a second power supply; the second power supply is connected with the chip to be tested and used for supplying power to the chip to be tested. That is, in this embodiment, the chip that awaits measuring not only can be through the first power supply on surveying the board, can also set up the second power on waiting to survey the board, for the chip power supply that awaits measuring, and then can avoid when surveying the board power supply through surveying, the not enough problem of power supply.
In one example, the second power supply on the board under test is disposed on the second side of the board under test, and the second power supply is disposed outside an overlapping area formed on the board under test when the test connector is connected to the connector. That is, when the second power supply is disposed on the board to be tested, the second power supply and the test connector on the board to be tested may be disposed on the second surface of the board to be tested. And the chip to be tested is arranged on the first surface of the board to be tested. In addition, in the specific design, it may be considered that the power supply on the board to be tested or other devices on the board to be tested, except the power supply, are disposed outside the overlapping area where the board to be tested and the connector on the test board are connected (for example, the second power supply is disposed outside the overlapping area covered on the board to be tested when the connector is connected to the connector), so as to avoid the situation that the board to be tested or the devices on the test board cannot be completely connected due to the influence of the devices on the board to be tested when the board to be tested and the test board are connected.
In an actual test process, fig. 7 is a schematic structural diagram of another board to be tested according to the embodiment of the present application. In fig. 7, a second power supply is disposed on one side of the board to be tested to supply power to the chip to be tested on the other side of the board to be tested. In addition, a switch is further arranged on the board to be tested, and the switch is connected with the chip to be tested on the other surface of the board to be tested and used for controlling the working state of the chip to be tested to be a closed state or an open state. In addition, a storage module is further arranged on the board to be tested and used for storing working data of the chip to be tested or writing data into the chip to be tested. And the dial switch on the board to be tested is connected with the chip and can be used for controlling the working mode of the chip. And a crystal oscillator is arranged on the other surface of the board to be tested and near the chip to be tested so as to provide local oscillation signals for the chip to be tested. In some examples, an indicator light may be further disposed on the side of the chip to be tested, and the indicator light is connected to the chip to be tested and is used for indicating the working state of the chip through brightness. During specific testing, the output data of a storage module (for example, a register) on a board to be tested can be controlled according to an SPI (serial peripheral interface) on the testing board, the working mode of the chip is controlled through the dial switch, the working state of the chip to be tested is controlled to be on through the switch, and then the testing process of the chip is started.
In addition, different interfaces or interface conversion circuits are further disposed on the board to be tested in fig. 7, for example, a USB (Universal Serial Bus) conversion circuit, a CAN (Controller Area Network) interface conversion circuit, and a JTAG (Joint Test Action Group) interface, and after the chip Test is finished, the board to be tested may be directly connected to an external processing unit through the interface or the interface conversion circuit, so as to send data in the memory module or the chip to be tested to the external processing unit. The board to be tested can be directly integrated into an actual product, the chip does not need to be detached from the board to be tested, and the product cost is reduced.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (13)
1. A test board is characterized in that the test board is applied to a chip to be tested integrated on the board to be tested for testing, a test connector connected with the chip to be tested is arranged on the board to be tested, and the test board comprises a test seat, a connector and a serial peripheral interface which are sequentially connected;
the connector is detachably connected with the test connector; the serial peripheral interface is used for externally connecting control equipment; the test seat is used for externally connecting a signal tester;
when the control equipment sends a control signal to the chip to be tested through the serial peripheral interface, the chip to be tested outputs a corresponding working signal to the signal tester through the test socket based on the control signal.
2. The test board according to claim 1, wherein the chip under test is a sensor chip, and the corresponding operating signal of the chip under test comprises an intermediate frequency signal.
3. A test board according to claim 2, characterised in that the sensor chip comprises a millimeter wave radar chip.
4. The test board of claim 1, wherein the test socket comprises a plug interface, the plug interface of the test socket being connected to the connector.
5. The test board according to claim 1, wherein the connector comprises a connection line interface, the connector being detachably connected to the connection line interface of the test connector through the connection line interface, the connection line.
6. The test board of claim 1, wherein the connectors comprise sockets through which the connectors are removably connected to the sockets of the test connectors.
7. The test plate of claim 1, further comprising: a first power supply;
the first power supply is connected with the test socket and used for supplying power to the test socket.
8. The test board according to claim 1, wherein the connectors support at least one of the following types of chips under test: 2T4R chips, 4T4R chips, and 4T8R chips.
9. The test plate of claim 1, wherein the test plate comprises: the test socket comprises a plurality of connectors, a plurality of test sockets in one-to-one correspondence with the connectors, and a plurality of serial peripheral interfaces in one-to-one correspondence with the connectors.
10. A test system, the test system comprising: a board under test, a control device, a signal tester, and the test board of any one of claims 1 to 9, which integrate a chip under test; wherein the content of the first and second substances,
the test board is detachably connected with the test chip on the board to be tested through the connector and is used for testing the chip to be tested;
the serial peripheral interface is connected with the control equipment and used for receiving a control signal sent by the control equipment;
the test seat is connected with the signal tester and used for receiving working signals output by the chip to be tested based on the control signals.
11. The test system of claim 10, wherein the chip under test is disposed on a first side of the board under test, and the test connector is disposed on a second side of the board under test.
12. The test system of claim 10, wherein the board under test further comprises: a second power supply; and the second power supply is connected with the chip to be tested and used for supplying power to the chip to be tested.
13. The test system of claim 12, wherein the second power supply is disposed on the second side of the board under test, and the second power supply is disposed outside an overlapping area formed on the board under test when the test connector is connected to the connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122406384.5U CN216816864U (en) | 2021-09-30 | 2021-09-30 | Test board and test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122406384.5U CN216816864U (en) | 2021-09-30 | 2021-09-30 | Test board and test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216816864U true CN216816864U (en) | 2022-06-24 |
Family
ID=82039870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122406384.5U Active CN216816864U (en) | 2021-09-30 | 2021-09-30 | Test board and test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216816864U (en) |
-
2021
- 2021-09-30 CN CN202122406384.5U patent/CN216816864U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9146277B2 (en) | Test board and test system | |
| WO2008097751A1 (en) | Distributing data among test boards to determine test parameters | |
| CN108346404B (en) | Parameter debugging method for time schedule controller and screen driving circuit | |
| US7478298B2 (en) | Method and system for backplane testing using generic boundary-scan units | |
| CN108732454A (en) | A kind of multi-core cable break-make decision maker and method based on Radio Transmission Technology | |
| CN109470974A (en) | A kind of testing lines system and method based on wireless technology | |
| CN216816864U (en) | Test board and test system | |
| CN101437133A (en) | Test switching device | |
| CN106646002A (en) | Anti-interference detection system of electronic device and testing antenna thereof | |
| CN102411528A (en) | MXM (Mobile PCI-Express Module)-interface testing-connecting card and testing system provided with same | |
| CN205786708U (en) | A kind of PCBA test needle plate | |
| CN206387909U (en) | A kind of universal satellite navigation receiver test platform | |
| CN107947836A (en) | Wireless near-field power coupling test device and test method | |
| CN212808842U (en) | Test keysets of display module assembly | |
| CN212781091U (en) | Intelligent detection system of KNX equipment | |
| CN212965016U (en) | Test panel suitable for different pin definitions | |
| CN111667783B (en) | Detection device and detection method thereof | |
| CN213302432U (en) | Function testing device and system | |
| US7688093B2 (en) | Sharing conversion board for testing chips | |
| CN218512480U (en) | Instrument control IO board card detection device | |
| CN212064018U (en) | LoRaWAN gateway module detection device based on raspberry group | |
| CN109302332B (en) | Automatic testing arrangement of communication network controller | |
| KR20150128840A (en) | System and method for confirming radio frequency (rf) signal connectivity with device under test (dut) | |
| CN219842811U (en) | Compatible sub-motherboard chip test system | |
| CN220671580U (en) | Test platform, jig and system for server board card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |