CN216773256U - Composite SiC epitaxial wafer and semiconductor device - Google Patents

Abstract

The application discloses compound SiC epitaxial wafer and semiconductor device, compound SiC epitaxial wafer includes: the method comprises the steps of forming a first SiC layer based on a preset semiconductor substrate, wherein the first SiC layer is a polycrystalline SiC epitaxial layer; and the second SiC layer is bonded on the surface of the first SiC epitaxial layer and is a single crystal SiC slice. This application technical scheme provides a combined type SiC epitaxial wafer, bonds monocrystalline SiC thin slice on polycrystal SiC epitaxial layer, through the effective utilization to high quality monocrystalline SiC thin slice, reaches reduction material cost, improves the output quality, promotes the purpose of supply security.

Description

Composite SiC epitaxial wafer and semiconductor device

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a composite SiC epitaxial wafer and a semiconductor device.

Background

Under the large background of carbon neutralization, high-power electronic technologies such as electric vehicles, rail transit, large-scale long-distance power transmission and the like become important strategic technical development directions of China. Traditional power electronic devices are mainly developed based on Si materials, but due to the limitation of physical properties of the materials, when the application scenes of large voltage and large power, such as 650V and 1200V, are approached, the problems of insufficient reliability, large volume, high energy consumption and the like of the devices based on the Si materials occur. When the application scene gradually goes to the application at the ten-thousand-volt level, the Si material cannot meet the demand, and therefore, a material with a wider forbidden band and a more stable crystal structure is needed to adapt to the technical development of the power electronic industry. Under the background, SiC materials become the first choice of power device materials, and have been greatly developed while receiving extensive attention.

As the most important third-generation semiconductor material, SiC material has a larger energy gap, a higher dielectric constant, and a higher thermal conductivity than Si material, and can be applied to high-voltage and high-power scenes with a simpler structure and a smaller size, and thus has attracted much attention.

The current methods for manufacturing SiC substrates and epitaxial wafers are limited by the special physical properties of SiC itself, and require extremely high temperatures, extremely long processing times, and precise control thereof, thereby resulting in extremely high technical thresholds and high costs, and hindering the wide application and development of SiC power electronic devices. Therefore, the SiC wafer substrate and the epitaxial solution with low cost can greatly reduce the material cost while ensuring the quality of the SiC material, further reduce the device cost, and have very important technical prospects and commercial values.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a composite SiC epitaxial wafer and a semiconductor device, and the scheme is as follows:

a composite SiC epitaxial wafer, comprising:

the method comprises the steps that a first SiC layer is formed on the basis of a preset semiconductor substrate, and the first SiC layer is a polycrystalline SiC epitaxial layer;

and the second SiC layer is bonded on the surface of the first SiC epitaxial layer and is a single crystal SiC slice.

Preferably, in the composite SiC epitaxial wafer described above, the composite SiC epitaxial wafer includes the semiconductor substrate having a first surface;

wherein the first SiC layer is grown on the first surface; the second SiC layer is located on a surface of the first SiC layer on a side facing away from the semiconductor substrate.

Preferably, in the composite SiC epitaxial wafer, the semiconductor base is a Si substrate.

Preferably, in the above composite SiC epitaxial wafer, the Si substrate has a thickness of not more than 650 μm.

Preferably, in the composite SiC epitaxial wafer, the semiconductor substrate is thinned and removed after the second SiC layer is bonded.

Preferably, in the above composite SiC epitaxial wafer, the thickness of the first SiC layer is not more than 100 μm.

Preferably, in the composite SiC epitaxial wafer, the thickness of the second SiC layer is in a range of 1 μm to 20 μm.

Preferably, in the above composite SiC epitaxial wafer, the second SiC layer is a single crystal SiC wafer that is peeled from the single crystal SiC substrate based on the ion-implanted layer in the surface of the single crystal SiC substrate.

Preferably, in the above composite SiC epitaxial wafer, the composite SiC epitaxial wafer further includes:

a third SiC layer grown on a surface of the second SiC layer on a side facing away from the first SiC layer;

wherein the third SiC layer is a single crystal SiC epitaxial layer.

The present application also provides a semiconductor device, including:

a composite SiC epitaxial wafer according to any one of the preceding claims.

As can be seen from the above description, in the composite SiC epitaxial wafer and the semiconductor device provided in the technical solution of the present application, the composite SiC epitaxial wafer includes: the method comprises the steps that a first SiC layer is formed on the basis of a preset semiconductor substrate, and the first SiC layer is a polycrystalline SiC epitaxial layer; and the second SiC layer is bonded on the surface of the first SiC epitaxial layer and is a single crystal SiC slice. This application technical scheme provides a combined type SiC epitaxial wafer, bonds single crystal SiC thin slice on polycrystal SiC epitaxial layer, through the effective utilization to high quality single crystal SiC thin slice, reaches reduction material cost, improves the output quality, promotes the purpose of supply security.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.

Fig. 1 is a schematic structural diagram of a composite SiC epitaxial wafer provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of another composite SiC epitaxial wafer provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of another composite SiC epitaxial wafer provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of another composite SiC epitaxial wafer provided in an embodiment of the present application;

fig. 5 to fig. 9 are process flow diagrams of a method for manufacturing a composite SiC epitaxial wafer according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The mainstream technical scheme for the growth of SiC crystals at present is PVT (physical vapor transport) growth. When the PVT process is used for manufacturing SiC crystals, proper SiC seed crystals and prefabricated SiC powder need to be prepared in advance, the SiC powder can be directly sublimated at high temperature to form mixed gas, the gas can be desublimated on the surfaces of the seed crystals through temperature field control and temperature curve control of the whole furnace body, crystal growth is carried out along the lattice structure of the seed crystals, and SiC crystal ingots with certain sizes are gradually formed. The process needs high temperature of 1800-2500 ℃, and both a resistance type heating mode and an inductance type heating mode need to consume great electric energy for at least one week. After the ingot is formed, annealing at a high temperature of thousands of degrees celsius for about one week is also required in order to improve defects and relieve stress. And because the controllability of the whole process is poor, the quality of the obtained crystal is uncertain, and high failure rate exists, so that the cost of the high-quality SiC substrate slice is extremely high.

The core technology of the current SiC substrate and epitaxy industry is mastered internationally by a few major manufacturers. The SiC substrate is expensive and the source of goods is tight. And for manufacturing a high-quality SiC epitaxial wafer, a high-quality SiC substrate is required, and then an epitaxial layer with the thickness of 10-20 um is formed on the surface of the SiC substrate by an epitaxial growth technology, and then the power device can be processed.

Therefore, the SiC crystal and epitaxial wafer grown based on the PVT process have high cost, unstable process quality and high supply chain risk due to high energy consumption and long process time. Meanwhile, the SiC crystal growth technology has high difficulty and low reproducibility, so that the technology is monopolized by large international factories and the domestic market supply capacity is poor.

Aiming at the problems of long process time, high cost, uncontrollable quality, high supply risk and the like in the prior art, the technical scheme of the application provides a novel composite SiC epitaxial wafer, and the purposes of reducing material cost, improving output quality and improving supply safety are achieved by effectively utilizing a high-quality substrate.

One of the key points of the technical scheme of the application is that a low-cost semiconductor substrate, such as a Si substrate, is adopted, a low-cost polycrystalline SiC epitaxial layer is prepared on the surface of the semiconductor substrate to serve as a first SiC layer, and a high-quality single crystal SiC slice is bonded on the surface of the first SiC layer to serve as a second SiC layer, so that the SiC composite substrate is formed.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

As shown in fig. 1, fig. 1 is a schematic structural diagram of a composite SiC epitaxial wafer provided in an embodiment of the present application, where the composite SiC epitaxial wafer includes:

a first SiC layer 11 formed on the basis of a preset semiconductor substrate, wherein the first SiC layer 11 is a polycrystalline SiC epitaxial layer;

and a second SiC layer 12 bonded to the surface of the first SiC epitaxial layer 11, the second SiC layer 12 being a single crystal SiC wafer. The first SiC layer 11 serves as a buffer layer for bonding the second SiC layer.

Wherein the second SiC layer 12 is bonded to the surface of the first SiC layer 11, and fixed therebetween by interatomic force. The polycrystalline SiC epitaxial layer may be a 3C-SiC epitaxial layer. The single crystal SiC flake is a 4H-SiC flake.

Optionally, the thickness of the first SiC layer 11 does not exceed 100 μm. For example, the thickness of the first SiC layer 11 may be 50 μm. The thickness of the second SiC layer 12 ranges from 1 μm to 20 μm, for example, the thickness of the second SiC layer 12 ranges from 1 μm, or from 10 μm to 15 μm.

The second SiC layer 12 is formed of a single crystal SiC substrate, such as a 4H-SiC substrate, based on a single crystal SiC wafer exfoliated from an ion-implanted layer in the surface of the single crystal SiC substrate. A high concentration ion implantation layer may be formed at a predetermined depth in the surface of the single crystal SiC chip by H ion implantation, and a stress difference may be formed based on the ion implantation layer so that the single crystal SiC chip can be vitrified in the ion implantation layer to form a single crystal SiC chip of a desired thickness.

In the embodiment shown in fig. 1, the composite SiC epitaxial wafer has a double-layer SiC structure formed of the first SiC layer 11 and the second SiC layer 12, and does not include the semiconductor substrate. A first SiC layer 11 formed on the basis of a predetermined semiconductor substrate, and a second SiC layer 12 bonded to a surface of the first SiC layer 11 facing away from the semiconductor substrate. And thinning and removing the semiconductor substrate after the second SiC layer 12 is bonded.

As shown in fig. 2, fig. 2 is a schematic structural diagram of another composite SiC epitaxial wafer provided in an embodiment of the present application, and based on the composite SiC epitaxial wafer shown in fig. 1, the composite SiC epitaxial wafer shown in fig. 2 includes the semiconductor substrate 10, and the semiconductor substrate 10 has a first surface; wherein the first SiC layer 11 is grown on the first surface; the second SiC layer 12 is located on a surface of the first SiC layer 11 facing away from the semiconductor substrate 10. In this embodiment, the composite SiC epitaxial wafer has a three-layer structure including the semiconductor substrate 10 and the first SiC layer 11 and the second SiC layer 12 which are located on the same side of the semiconductor substrate 10 and stacked in this order.

In the embodiment of the present application, the semiconductor base 10 is a Si substrate. Optionally, the thickness of the Si substrate 10 does not exceed 650 μm.

As shown in fig. 3, fig. 3 is a schematic structural diagram of another composite SiC epitaxial wafer provided in an embodiment of the present application, and based on the composite SiC epitaxial wafer shown in fig. 2, the composite SiC epitaxial wafer shown in fig. 2 further includes: a third SiC layer 13 grown on a surface of the second SiC layer 12 on a side facing away from the first SiC layer 11; wherein the third SiC layer 13 is a single crystal SiC epitaxial layer. In this embodiment, the composite SiC epitaxial wafer includes the semiconductor substrate 10. In this embodiment, the composite SiC epitaxial wafer has a four-layer structure including the semiconductor substrate 10, and the first SiC layer 11, the second SiC layer 12, and the third SiC layer 13 which are located on the same side of the semiconductor substrate 10 and stacked in this order.

As shown in fig. 4, fig. 4 is a schematic structural diagram of another composite SiC epitaxial wafer provided in an embodiment of the present application, and based on the composite SiC epitaxial wafer shown in fig. 1, the composite SiC epitaxial wafer shown in fig. 4 further includes: a third SiC layer 13 grown on a surface of the second SiC layer 12 on a side facing away from the first SiC layer 11; wherein the third SiC layer 13 is a single crystal SiC epitaxial layer. In this embodiment, the composite SiC epitaxial wafer does not include the semiconductor base 10, and the semiconductor substrate 10 may be thinned and removed after the second SiC layer 12 is bonded, specifically, the semiconductor substrate 10 may be thinned and removed after the third SiC layer 13 is formed. In this embodiment, the composite SiC epitaxial wafer has a three-layer structure, and includes the first SiC layer 11, the second SiC layer 12, and the third silicon carbide layer 13 stacked in this order, excluding the semiconductor substrate 10.

The embodiment of the application provides a novel composite SiC epitaxial wafer, 3C-SiC epitaxial layer growth with low cost and low process difficulty is carried out on the surface of a low-cost Si substrate, the 3C-SiC epitaxial layer is used as a buffer layer, and a high-quality 4H-SiC slice is bonded on the surface of the 3C-SiC epitaxial layer, so that the composite SiC epitaxial wafer is formed. Epitaxial processing can be further carried out on the side, away from the 3C-SiC epitaxial layer, of the 4H-SiC thin slice based on the requirements of the semiconductor device.

According to the composite SiC epitaxial wafer, a single crystal SiC substrate, such as a 4H-SiC substrate, can be stripped to form a plurality of single crystal SiC slices, the high-quality single crystal SiC substrate can be used for multiple times, and the composite SiC epitaxial wafer can meet the requirement of a power device on a SiC material by adopting the single crystal SiC slices with smaller thickness. The composite SiC epitaxial wafer adopts relatively low-cost 3C-SiC as a buffer layer for bonding the single crystal SiC slice, and simultaneously adopts a very low-cost Si substrate as a support. The requirements of the power device on the substrate and the epitaxial material can be completely realized, and meanwhile, the cost of the substrate and the epitaxial material is greatly reduced. Meanwhile, the utilization efficiency of the high-quality substrate is greatly improved, the requirement on the single crystal SiC material can be greatly reduced, and the robustness of a supply chain is improved.

The following describes a manufacturing process of a composite SiC epitaxial wafer according to an embodiment of the present application:

taking the fabrication of the composite SiC epitaxial wafer shown in fig. 3 as an example, as shown in fig. 5 to 9, fig. 5 to 9 are process flow diagrams of a method for fabricating a composite SiC epitaxial wafer according to an embodiment of the present application, where the method includes:

step S11: as shown in fig. 5, a semiconductor substrate 10 is provided.

The semiconductor substrate 10 is a Si substrate, and the Si substrate has a mature manufacturing process and low cost. The thickness of the Si substrate is typically 650 μm.

Step S12: as shown in fig. 6, after the surface treatment of the semiconductor substrate 10, a polycrystalline SiC epitaxial layer is formed on the surface of the semiconductor substrate 10, and the polycrystalline SiC epitaxial layer serves as the first SiC layer 11.

The surface treatment of the semiconductor substrate 10 includes: the surface of the semiconductor substrate 10 is subjected to cleaning and polishing treatment. After the surface treatment of the semiconductor substrate 10, the polycrystalline SiC epitaxial layer is formed on the surface of the semiconductor substrate 10 by an epitaxial process, specifically, 3C-SiC epitaxial growth may be performed by a CVD (chemical vapor deposition) apparatus, and the polycrystalline SiC epitaxial layer is formed based on a silicon source gas and a carbon source gas.

When the polycrystalline SiC epitaxial layer is deposited, the temperature and the gas ratio need to be accurately controlled, and due to polycrystalline growth, the required temperature, time and control requirements are lower compared with those of single crystal SiC. When the polycrystalline SiC epitaxial layer is deposited, the temperature is between 1000 ℃ and 1300 ℃, the growth time is based on the required film thickness and can be from several minutes to several hours, and the growth time is determined according to the actual growth thickness.

Wherein the thickness of the first SiC layer 11 does not exceed 100 μm. For example, the thickness of the first SiC layer 11 may be 50 μm. The thickness of first SiC layer 11 may be set based on semiconductor device performance requirements, and first SiC layer 11 is not limited to the thickness range described in the embodiments of the present application.

Step S13: as shown in fig. 7, a bonding (bonding) process is used to bond the second SiC layer 12 to the surface of the first SiC layer 11 on the side facing away from the semiconductor substrate 10, with a single crystal SiC wafer as the second SiC layer 12.

In step S13, a modified layer may be formed on the surface of the single crystal SiC substrate piece at a predetermined depth by irradiation with high-energy laser light using a high-quality low-doped single crystal SiC substrate, and then a portion of the single crystal SiC substrate above the modified layer may be removed by lift-off to obtain a single crystal SiC wafer of a desired thickness as the second SiC layer 12. Namely, a single crystal SiC wafer in which the second SiC layer 12 is peeled off from the 4H-SiC substrate based on the ion-implanted layer in the surface of the 4H-SiC substrate. By repeating this peeling process, a single crystal SiC substrate of a conventional thickness can be peeled into 300 pieces of single crystal SiC wafers, which can be up to 1 μm in minimum thickness. And polishing the single crystal SiC slice, bonding and fixing the single crystal SiC slice and the polycrystalline SiC epitaxial layer to form a composite SiC epitaxial wafer, and annealing the composite SiC epitaxial wafer.

Wherein the preset depth range is 1 μm to 20 μm to prepare a single crystal SiC wafer having a thickness of 1 μm to 20 μm as the second SiC layer 12. Alternatively, the preset depth range may be 10 μm to 15 μm to prepare a single crystal SiC wafer 10 μm to 15 μm in thickness as the second SiC layer 12.

When the composite SiC epitaxial wafer includes the third SiC layer 13, a functional structure of a semiconductor device can be produced based on the third SiC layer 13, and at this time, a thin single crystal SiC wafer of a relatively small thickness can be employed, and thus the single crystal SiC wafer can be 1 μm. When the composite SiC epitaxial wafer does not include the third SiC layer 13, at which time it is necessary to prepare a functional structure of a semiconductor device based on the second SiC layer 12, it is necessary to employ a single crystal SiC wafer having a large thickness as the second SiC layer 12, and thus the single crystal SiC wafer has a thickness in the range of 10 μm to 15 μm.

Step S14: as shown in fig. 8, the surface of semiconductor substrate 10 on the side away from first SiC layer 11 is thinned, semiconductor substrate 10 is thinned from thickness H1 to thickness H2, and a portion of semiconductor substrate 10 remains.

Before the thinning, the thickness of the semiconductor substrate 10 is H1, and after the thinning, the thickness of the semiconductor substrate 10 is H2, and H2 is smaller than H1. If the Si substrate is adopted, the thickness of the common Si substrate is about 650 μm generally, and the thickness of the thinned Si substrate is not more than 650 μm.

If the composite SiC epitaxial wafer has a portion of the semiconductor substrate 10 remaining, the semiconductor substrate 10 may be thinned to 350 μm ± 15 μm, or the semiconductor substrate 10 may be thinned to 500 μm ± 20 μm, depending on the use requirements of the semiconductor device.

Step S15: as shown in fig. 9, the third SiC layer 13 is epitaxially grown on the surface of the second SiC layer 12 on the side facing away from the first SiC layer 11, and a composite SiC epitaxial wafer as shown in fig. 3 is finally formed.

If the process flow for manufacturing the composite SiC epitaxial wafer shown in FIG. 4 and the composite SiC epitaxial wafer shown in FIG. 3 is based on, the method further comprises the following steps: after step S15, the semiconductor substrate 10 is subjected to thinning polishing again to completely remove the semiconductor substrate 10.

If a composite SiC epitaxial wafer as shown in fig. 1 is produced, the production process is the same as the above-described step S11 to step S14, and the semiconductor substrate 10 is completely thinned and removed in step S14.

If a composite SiC epitaxial wafer as shown in fig. 2 is fabricated, the fabrication process is the same as the above-described step S11-step S14, and partial thinning removal is performed on the semiconductor substrate 10 at step S14.

In the embodiment of the present application, if the compound SiC epitaxial wafer will the semiconductor substrate 10 is thinned completely and removed, at this time, the compound SiC epitaxial wafer is an epitaxial wafer only including SiC materials, and has high thermal conductivity, so that the heat dissipation efficiency of the semiconductor device can be improved, and the thickness of the semiconductor device can be reduced.

In the embodiment of the application, if the semiconductor substrate 10 with partial thickness is reserved on the composite SiC epitaxial wafer, on one hand, the process time for thinning and polishing treatment can be reduced, and the cost is reduced; on the other hand, for some existing semiconductor device package structures, the thickness is required to be certain, and the thickness cannot be uniformly reduced to about 60 micrometers, so that the semiconductor substrate 10 can be thinned to a standard thickness commonly used in the industry, and the final thickness can be determined according to the requirements of users.

According to the embodiment of the application, the high-quality single crystal SiC substrate is efficiently utilized, and the low-cost semiconductor substrate is used for replacing SiC materials, so that the purpose of reducing the cost of the SiC epitaxial wafer is achieved, and the cost of the epitaxial wafer can be reduced by more than 50%. Meanwhile, the dependence on a high-quality single crystal SiC substrate is greatly reduced, so that the safety of a supply chain can be ensured more easily.

Based on the above embodiments, another embodiment of the present application further provides a semiconductor device, including: the composite SiC epitaxial wafer described in the above embodiment. The semiconductor device includes, but is not limited to, a power device or a radio frequency device.

According to the embodiment of the application, the semiconductor device adopts the composite SiC epitaxial wafer, the manufacturing cost can be greatly reduced, and the SiC material has better heat conduction efficiency, so that the semiconductor device has better heat dissipation performance.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other.

It is to be understood that in the description of the present application, the drawings and the description of the embodiments are to be regarded as illustrative in nature and not as restrictive. Like numerals refer to like structures throughout the description of the embodiments. Additionally, the figures may exaggerate the thicknesses of some layers, films, panels, regions, etc. for ease of understanding and ease of description. It will also be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In addition, "on …" means that an element is positioned on or under another element, but does not essentially mean that it is positioned on the upper side of another element according to the direction of gravity.

The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like refer to an orientation or positional relationship relative to an orientation or positional relationship shown in the drawings for ease of description and simplicity of description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A composite SiC epitaxial wafer, characterized in that it comprises:

the method comprises the steps that a first SiC layer is formed on the basis of a preset semiconductor substrate, and the first SiC layer is a polycrystalline SiC epitaxial layer;

and the second SiC layer is bonded on the surface of the first SiC epitaxial layer and is a single crystal SiC slice.

2. The composite SiC epitaxial wafer of claim 1, wherein the composite SiC epitaxial wafer comprises the semiconductor substrate, the semiconductor substrate having a first surface;

wherein the first SiC layer is grown on the first surface; the second SiC layer is located on a surface of the first SiC layer on a side facing away from the semiconductor substrate.

3. The composite SiC epitaxial wafer of claim 1, wherein the semiconductor base is a Si substrate.

4. A composite SiC epitaxial wafer according to claim 3, characterized in that the Si substrate has a thickness not exceeding 650 μm.

5. The composite SiC epitaxial wafer of claim 1, wherein the semiconductor substrate is thinned and removed after bonding the second SiC layer.

6. The composite SiC epitaxial wafer of claim 1 wherein the thickness of the first SiC layer is no more than 100 μ ι η.

7. The composite SiC epitaxial wafer of claim 1 wherein the second SiC layer has a thickness in the range of 1-20 μ ι η.

8. The composite SiC epitaxial wafer of claim 1 wherein the second SiC layer is a single crystal SiC wafer that is peeled from a single crystal SiC substrate based on an ion implanted layer in the surface of the single crystal SiC substrate.

9. The composite SiC epitaxial wafer of any one of claims 1-8, further comprising:

a third SiC layer grown on a surface of the second SiC layer on a side facing away from the first SiC layer;

wherein the third SiC layer is a single crystal SiC epitaxial layer.

10. A semiconductor device, characterized in that the semiconductor device comprises:

a composite SiC epitaxial wafer according to any one of claims 1 to 9.

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