JP2002299277A - Manufacturing method for thin-film structural unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a thin-film structural unit free from warpage. SOLUTION: This manufacturing method for a thin-film structural unit includes (1) a process in which substrate separation layers 3a and 3b are formed in a substrate (Si wafer) 1 having first and second main surface in a reaction chamber, (2) a process in which a first epitaxial growth layer 5a made of a material different from the material of the Si wafer 1 and second epitaxial growth layer 5b made of a material different from the materials of the first layer 5a and the Si substrate 1 are deposited simultaneously on the first main surface and the second main surface, respectively, in the same reaction chamber, and (3) a process in which the Si wafer 1 is separated by using the substrate separation layers 3a and 3b to obtain first and second independent thin-film structural units 8a and 8b which include the first and second epitaxial growth layers 5a and 5b, respectively. As hetero-epitaxial growth layers are deposited simultaneously on the first and second main surface of the substrate, warpages caused by a difference in lattice constaints and heat expansion coefficients cancel each other, so that the high quality epitaxial growth layers 5a and 5b can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a thin film structure, and more particularly to a method of manufacturing a thin film structure made of a semiconductor material in which it is difficult to obtain a large-diameter bulk crystal serving as a material for a substrate for epitaxial growth.

[0002]

2. Description of the Related Art In recent years, silicon carbide (hereinafter referred to as "Si
C ". ) Or gallium nitride (below,
"GaN". ), Etc. (hereinafter, referred to as “wide band gap semiconductor”). The forbidden band width Eg of SiC is 3C-Si
2.23 eV for C, 2.93 eV for 6H-SiC, 4H
A value of about 3.26 eV has been reported for -SiC. G
The forbidden band width Eg of aN is about 3.4 eV. In addition to the wide band gap semiconductor, forbidden band width Eg = zinc telluride (ZnTe) having a band gap of about 2.2 eV, forbidden band width Eg
= About 2.4 eV cadmium sulfide (CdS), band gap Eg = about 2.7 eV zinc selenide (ZnSe), band gap Eg = about 3.7 eV zinc sulfide (ZnS), and band gap Eg. = About 5.5 eV diamond and the like are known. These wide band gap semiconductors have a high binding energy, a forbidden band width (band gap), and a large breakdown electric field strength. Taking advantage of the characteristics of these wide band gap semiconductors, they are attracting attention as materials for high-efficiency, high-breakdown-voltage power devices, high-frequency power devices, high-temperature operating devices, or blue to ultraviolet light emitting devices.

[0003]

SUMMARY OF THE INVENTION Silicon which has been studied in the semiconductor industry from an early stage and has been put to practical use (forbidden band width Eg =
About 1.1 eV) and gallium arsenide (forbidden band width Eg = about 1.
Compared to semiconductor materials having a normal bandgap Eg such as 4 eV), it can be said that these wide gap semiconductors have not yet developed a crystal growth technique or an impurity diffusion technique. For example, silicon (hereinafter referred to as “Si”) has reached a stage where a wafer having a diameter of 30 cm is commercially available. On the other hand, in these wide band gap semiconductors, at present, good single crystals cannot be obtained as bulk crystals. In particular, a large-diameter wide band gap semiconductor substrate (wafer) suitable for mass production has not been obtained. Therefore, when a large-diameter epitaxial growth layer is required for manufacturing a semiconductor device such as an individual semiconductor device or a semiconductor integrated circuit, heteroepitaxial growth is usually performed on a large-diameter substrate made of a material different from the intended wide band gap semiconductor. The method is adopted. At this time, crystal defects and warpage are caused between the substrate and the heteroepitaxially grown wide band gap semiconductor thin film due to differences in lattice constant and thermal expansion coefficient.

When a warped thin film structure is used as a substrate of a semiconductor device, an optically out-of-focus portion occurs in a photolithography process in a semiconductor device manufacturing process. The inconvenience that a pattern cannot be transferred occurs.
In addition, a semiconductor manufacturing apparatus such as a stepper, an ion implantation apparatus, and a CVD apparatus has a loader and a substrate support designed on the assumption that a flat substrate without warpage is handled.
In some cases, the warped substrate cannot be accommodated in the semiconductor manufacturing apparatus. Further, since a large stress acts on the heterojunction interface, a defect occurs in the crystal structure of the semiconductor thin film near the heterojunction interface, which adversely affects the electrical characteristics and surface morphology when used as a semiconductor device. Also, as the diameter of the wafer becomes larger, the difference between the lattice constant and the coefficient of thermal expansion cannot be ignored. For example, SiC
At present, when epitaxial growth is performed on a Si wafer having a diameter of 15 cm, high quality and high yield crystals cannot be obtained. If a SiC epitaxial growth layer having a large area cannot be obtained, only a small number of semiconductor devices can be obtained from one wafer when a semiconductor device using SiC is manufactured industrially, and efficient mass production must be performed. Is difficult.

As a method for solving this problem, a manufacturing method for SiC is proposed in Japanese Patent Application Laid-Open No. H11-60389 (hereinafter referred to as "first conventional technique").
Japanese Patent Application Laid-Open No. 2000-12900 proposes a manufacturing method for aN (hereinafter, referred to as "second conventional technique"). However, in the first and second prior arts, a complicated mask pattern must be transferred onto a substrate in advance as a method for preventing warpage occurring in a crystal growth process due to a difference in lattice constant. Is required, and the manufacturing process becomes complicated. Further, even if the occurrence of warpage during growth due to a difference in lattice constant can be prevented, it is necessary to prevent warpage due to a difference in thermal expansion coefficient newly generated after the growth is returned to room temperature. One method is to remove the substrate after growth in order to prevent warpage due to the difference in thermal expansion coefficient. However, the first and second prior arts do not disclose any remarkable techniques for this step. In the second prior art, since the step of removing the substrate is performed only by ordinary etching,
It takes a considerable amount of time to remove all the substrates having a large area, which is not efficient. For example, in the second conventional technique, it takes 10 hours to remove the substrate.

[0006] There is another problem concerning epitaxial growth, particularly vapor phase epitaxial growth. When epitaxially growing a wide band gap semiconductor thin film,
In reality, only a small amount of the source gas fed into the reaction vessel reacts with the substrate surface and contributes to the formation of the epitaxial layer. In other words, the other unreacted source gas is discharged from the reaction vessel as it is,
Does not contribute to epitaxial growth at all. Therefore, it is necessary to perform more efficient vapor phase epitaxial growth.

The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method of manufacturing a thin film structure without warpage.

It is another object of the present invention to provide a method of manufacturing a thin film structure having higher productivity suitable for mass production of semiconductor devices.

[0009]

In order to achieve the above object, the present invention provides (a) a step of providing a substrate separation layer inside a substrate having first and second main surfaces, and (b) the same reaction vessel. A step of simultaneously depositing a first epitaxial growth layer made of a material different from the substrate on the first main surface, and a second epitaxial growth layer made of the same material as the first epitaxial growth layer on the second main surface; Obtaining a first thin film structure including the first epitaxial growth layer and a second thin film structure including the second epitaxial growth layer by separating the substrate using the layers. Is the gist. By separating the substrate using the substrate separation layer, it is possible to obtain first and second thin film structures having the same structure of the epitaxial growth layer and being independent from each other. Here, the “first main surface” is
One main surface (surface having the largest area or the second largest area) of a substantially flat (wafer-shaped) substrate.
The “second main surface” is the other main surface facing the “first main surface”. That is, one of the first and second main surfaces is defined as two opposing surfaces having a relationship that can be interpreted as “front surface” and the other as “back surface”. The “thin film structure” is a structure made of a thin film grown by epitaxial growth, and is a concept including a case where a substrate remains under an epitaxially grown thin film.

The method for producing a thin film structure according to the present invention includes
It is suitable for the production of a thin film structure including epitaxial growth of a wide band gap semiconductor having a wider forbidden band than 2.2 eV, which makes it difficult to obtain a large-diameter wafer. By simultaneously depositing the epitaxial growth layer on the first main surface and the second main surface, it becomes possible to effectively cancel the stress and warpage inside the epitaxial growth layer generated during the growth. This is because distortions of the same magnitude are generated on the first main surface and the second main surface and cancel each other. Therefore, an epitaxially grown layer having high crystal perfection can be obtained without warping the epitaxially grown layer.

According to the method of manufacturing a thin film structure according to the present invention, the epitaxial growth layer is deposited on both the first main surface and the second main surface. Here, the amount of the source gas supplied in the epitaxial growth may be the same amount as when the epitaxial growth layer is grown only on the first main surface of the substrate. By separating the thin film structure from the substrate after the growth, there is an advantage of improving productivity that two thin film structures can be obtained from one substrate in one growth.

In the features of the present invention, it is preferable that the thickness of the substrate included in the first thin film structure is smaller than the thickness of the first epitaxial growth layer. By making the thickness of the included substrate thin, the epitaxial growth layer side can be regarded as a rigid body. That is, the stress generated between the substrate and the epitaxial growth layer acts on the thin substrate side. Therefore, even after separation into two thin film structures, it is possible to prevent stress and warpage from reaching the epitaxial growth layer side.

In the features of the present invention, SiC or GaN is preferable as the wide band gap semiconductor. In particular, when SiC is used for the epitaxially grown thin film, a large-diameter wafer can be easily obtained as a substrate.
It is preferable to use i. On the other hand, when GaN is adopted as the epitaxially grown thin film, it is possible to use SiC, which can be relatively easily made larger in diameter than GaN, as the substrate. It is possible to carry out the manufacturing method according to the present invention even with a combination of other materials.

Preferably, the step of providing a substrate separation layer includes a step of injecting protons (H ⁺ ) into the substrate. This is because, by injecting protons, the interatomic bonds in the substrate are partially cut, and the substrate can be separated at a specific crystal plane. In particular, the heating of the substrate promotes the breaking of interatomic bonds in the substrate in the region into which protons have been implanted, and further increases the thermal stress, causing the interatomic bonds in the substrate to grow on specific surfaces. Completely disconnected.

A “bond region” in which protons are not implanted in some regions is left, and after the epitaxial growth is completed,
The first and second thin film structures can be separated from each other by performing selective etching only on the bond region where the interatomic bond is maintained. Since only the bond region is required to be dissolved and removed by the selective etching, only a small amount of etching is required, and the step of separating the first and second thin film structures from each other can be performed very quickly.

In addition to the step of providing the substrate separation layer, a step of forming an SOI structure by a SIMOX method or a direct bonding method (SDB method) may be used. After epitaxial growth on both sides, the substrate can be separated by selective etching of the buried insulating film constituting the SOI structure.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the width of the layers, the ratio of the thickness of each layer, and the like are different from actual ones. In addition, it is needless to say that the drawings include portions having different dimensional relationships and ratios.

First, a double-sided epitaxial growth apparatus for obtaining a thin-film structure according to the embodiment of the present invention will be described. The double-sided epitaxial growth apparatus relates to vapor phase epitaxial growth, and includes a semiconductor wafer holding device 16 shown in FIG. 4, a cylindrical quartz tube (reaction vessel) 18 containing the semiconductor wafer holding device 16 therein, and a coil wound around the quartz tube 18. A heating coil (high-frequency induction heating coil) 19, a pressure regulator (not shown), a material supply mechanism such as a mass flow controller and a gas piping system, and a discharge mechanism are provided. Although not shown, the semiconductor wafer holding device 16 is fixed inside the quartz tube 18 by a support frame or the like.

The semiconductor wafer holding device 16 comprises wafer holding portions 16a and 16b and connecting portions 39a and 39b. As shown in FIGS. 4 and 5, the wafer holding portions 16a and 16b have a deep comb structure made of graphite covered with an ultra-high purity SiC coating. The two comb structures connect each other with the connecting portions 39a, 39b.
The cross section of the semiconductor wafer holding device 16 shown in FIG. 4 is circular. The semiconductor wafer 17 is fixed in the semiconductor wafer holding device 16 by sandwiching both ends of the semiconductor wafer 17 by a pair of wafer holding portions 16a and 16b having a comb-shaped concave portion. Since the semiconductor wafer 17 is fixed at both ends by the wafer holding portions 16a and 16b, both surfaces of the semiconductor wafer 17 are exposed in a quartz tube 18 serving as a reaction vessel, and a raw material gas atmosphere to which both surfaces of the semiconductor wafer 17 are supplied. Will be exposed inside. Further, since the wafer holding units 16a and 16b have a plurality of concave portions, the semiconductor wafer holding device 16 can hold a large number of semiconductor wafers 17. As a result, the first vapor-phase epitaxial growth of a plurality of semiconductor wafers
The epitaxial growth layer can be grown on the main surface and the second main surface, and a more efficient thin film structure can be manufactured.

The wafer holders 16a and 16b are made of graphite covered with an ultra-high purity SiC coating. The purpose is to efficiently absorb the RF power radiated from the heating coil 19 and generate heat to transfer the heat to the semiconductor wafer 17. R
From the viewpoint of excellent F power absorption characteristics and thermal conductivity, graphite is used. Therefore,
The wafer holders 16a and 16b may be made of a material other than graphite as long as the RF power generated by the heating coil 19 can be efficiently transmitted to the semiconductor wafer 17. Further, the heating coil 19 may be constituted by a resistance heating element, and the semiconductor wafer 17 may be heated by a resistance heating method. However, in this case, a quartz tube (reaction vessel)
Since the tube wall of the tube 18 is heated to be a hot wall system, there is a problem of a falling object from the quartz tube 18 and a decrease in growth rate.

In the surface area of the semiconductor wafer 17,
At the portions held by the pair of wafer holding portions 16a and 16b, there is no surface reaction with the source gas, so that vapor phase epitaxial growth is not performed. Therefore, in order to increase the area of the semiconductor wafer 17 on which the vapor phase epitaxial growth can be performed, the semiconductor wafer 17 may be fixed not at both ends but by only one end. However, in this case, the semiconductor wafer 17 tends to move due to gas flow and thermal distortion during growth, and lacks stability, as compared with the case where both ends are fixed. For this reason, some other holding tool is required to ensure stability. Also, the semiconductor wafer holding portions 16a, 1
It is also preferable to adopt a structure in which the side 6b does not contact the first and second main surfaces of the semiconductor wafer 17 at all and sandwiches the side surface (end surface) of the semiconductor wafer 17. In this case, since both surfaces of the semiconductor wafer 17 are surface-reacted with the source gas on the entire surface, more efficient epitaxial growth can be performed. In addition, any device that holds the semiconductor wafer 17 in such a manner that both surfaces of the semiconductor wafer 17 can ensure a surface reaction with the source gas can be used as a double-sided epitaxial growth device.

In the portion near and far from the source of the source gas during the double-sided epitaxial growth, the amount of the source gas existing near the semiconductor wafer 17, the linear velocity of the source gas, the supply amount of the reactive species to the substrate surface, the substrate The amount of reactive species adsorbed on the surface, the amount of reaction product desorbed from the substrate surface, and the like are different, and the film thickness after vapor phase epitaxial growth may not be uniform in the plane. In order to prevent such a situation, the quartz tube 18
Semiconductor wafer holding device 1 having a large inner diameter
It is also effective to adopt a structure in which the semiconductor wafer holding device 16 can be rotated by a supporting tool by separating the quartz tube 18 from the quartz tube 18. By rotating the semiconductor wafer 17
The amount of the source gas in contact with the substrate is averaged, so that a double-sided epitaxial growth layer having a more uniform film thickness can be deposited. In order to more efficiently cause the average amount of the source gas to be present in the vicinity of each region of the semiconductor wafer 17, two rotation axes may be provided.

(First Embodiment) A method for manufacturing a thin film structure according to a first embodiment will be described with reference to FIGS. Here, as the wide band gap semiconductor single crystal thin film of the present invention, cubic SiC (hereinafter referred to as “3
C-SiC ". A case where a single crystal thin film is epitaxially grown on both sides will be described as an example. A Si substrate (Si wafer) 1 is used as a substrate for double-sided epitaxial growth.

Hereinafter, a method for manufacturing a thin film structure including a 3C-SiC single crystal thin film will be described step by step.

(A) A resist is spin-coated on the first main surface of the Si wafer 1, and an ion implantation mask 2a is formed by a resist pattern. The ion implantation mask 2a
Using a photolithography method, a pattern composed of two concentric rings is used as shown in FIGS.

(B) Then, as shown in FIG.
First main table of Si wafer 1 using ON implantation mask 2a
Proton (H⁺Inject). Of the first implementation
In the embodiment, the Si wafer 1 is 1 μm deep from the first main surface.
H in position⁺An implantation region 3a is formed. Specifically, acceleration
Energy 150 keV and dose 5 × 10¹⁶cm
^-2And As a result of this process, the Si wafer 1
As shown in (b), the bond of the Si atom is partially broken.
H⁺An implantation region 3a is formed.

(C) Next, the first main surface and the second main surface of the Si wafer 1 are reversed, and the second main surface of the Si wafer 1 is applied to the second main surface by photolithography as shown in FIGS. An ion implantation mask 2b composed of two concentric ring-shaped resist patterns as shown in FIG.

(D) Next, using the ion implantation mask 2b formed in the step (c), as shown in FIG.
H ⁺ implantation is performed on the second main surface of the i-wafer 1. As a result, as shown in FIG. 2D, the H ⁺ implantation region 3b is formed at a position 1 μm deep from the surface. And FIG.
As shown in (d), the ion implantation masks 2a and 2b are removed.

(E) Next, the Si wafer 1 is fixed using the semiconductor wafer holding device 16 so that the first and second main surfaces do not contact the quartz tube 18 of the double-sided epitaxial growth device. After being fixed in the quartz tube 18, first, the first and second main surfaces of the Si wafer 1 are carbonized. 3C-SiC epitaxial growth layer 5a directly on Si wafer 1,
When 5b is deposited, many dislocations are generated due to a difference in lattice constant and the like.
3C-Si by carbonizing the first and second main surfaces of wafer 1
C films 4a and 4b are formed in advance. Specifically, the quartz tube 1
Acetylene (C2H2) is supplied into the quartz tube 18 so that the inside pressure of the tube 8 becomes 2.7 Pa. The supply amount of acetylene is 10 sccm. In this acetylene atmosphere, the temperature in the quartz tube 18 is raised from room temperature to 1050 ° C. over 2 hours. In this process, carbon contained in acetylene enters the position of Si on the first and second main surfaces of the Si wafer 1, and as shown in FIG.
3C-SiC films 4a and 4b are formed on the first and second main surfaces.

(F) Next, the first and second main vapor phase epitaxial growths of the Si wafer 1 are performed. The temperature in the quartz tube 18 is maintained at 1050 ° C., and dichlorosilane (SiH 2 Cl 2) and acetylene are used as raw materials for 3C—SiC. The two raw materials are alternately flowed into the quartz tube 18 at 20 sccm for 10 seconds and at an interval of switching between the two raw materials of 5 seconds. At this time, the pressure in the quartz tube 18 is 27.0 Pa when dichlorosilane is supplied, and is 2.7 Pa when acetylene is supplied. The raw materials and the inflow amount in the vapor phase epitaxial growth are the same as those in the normal vapor phase epitaxial growth in which the epitaxial growth is performed only on one surface of the Si wafer. The supply cycle of the raw material is repeated, and both surfaces are epitaxially grown until the 3C-SiC epitaxial growth layers 5a and 5b have a thickness of 100 μm as shown in FIG. The thickness of the 3C-SiC epitaxial growth layers 5a and 5b can be controlled by adjusting the growth time. 3C-Si
Since the C epitaxial growth layers 5a and 5b need to have a certain thickness in order to be made of a good single crystal having few defects, the thickness of the 3C-SiC epitaxial growth layers 5a and 5b is desirably 50 μm or more.

(G) After growing the 3C-SiC epitaxial growth layers 5a and 5b on the first and second main surfaces, a first thin film structure 8a consisting of the 3C-SiC epitaxial growth layer 5a on the first main surface side, The second thin film structure 8b composed of the 3C-SiC epitaxial growth layer 5b on the 2 main surface side is separated. The bonding of Si atoms in the Si wafer 1 is partially cut by the H ⁺ implanted regions 3a and 3b previously provided in the Si wafer 1 in the steps (b) and (d). Further, when the 3C-SiC epitaxial growth layers 5a and 5b are epitaxially grown on both sides on the Si wafer 1, the temperature of the Si wafer 1 has risen to 1050 ° C., so that the H ⁺ implantation region 3a,
3b is in a peeled state in which the bond between Si atoms is completely cut. Therefore, the atoms are bonded only by the bond regions other than the H ⁺ implantation regions 3a and 3b. By selectively removing the bond region maintaining the interatomic bond as shown in FIG. 2 (g), finally, as shown in FIG.
As shown in (h), the wafer is separated into the Si wafer 6 and the first and second thin film structures 8a and 8b. Here, the selective removal of the bond region maintaining the interatomic bond is shown in FIG.
Is performed by side etching on the Si wafer 1 as shown in FIG. As an etching solution used for the side etching, a Si selective etching solution such as a mixed solution of nitric acid (HNO3) and hydrofluoric acid (HF) at a ratio of 1: 7 is used. This S
Since the selective etching solution i dissolves only Si and is completed in a short time, it does not affect the 3C-SiC epitaxial growth layers 5a and 5b at all. With the above, 3C-Si
The first and second thin film structures 8a and 8b including the C epitaxial growth layers 5a and 5b are obtained.

In the conventional epitaxial growth method, the 3C-SiC epitaxial growth layer is grown on one side only on one main surface of the Si wafer.
Due to the lattice constant mismatch between the i-substrate and the 3C-SiC epitaxial growth layer and the difference in the coefficient of thermal expansion,
-Since tension is generated in the direction of the heterojunction interface of the SiC epitaxial growth layer, there is a problem that the epitaxial growth layer is warped. However, when the 3C-SiC epitaxial growth layers 5a and 5b are simultaneously epitaxially grown on the first and second main surfaces of the Si wafer 1 under the same conditions, the Si substrate (wafer) 1 and the first and second
The stress generated at each heterojunction interface with the 3C-SiC epitaxial growth layers 5a, 5b of the Si wafer 1
Have the same size on the first and second main surfaces. Therefore, by depositing the 3C-SiC epitaxial growth layers 5a and 5b on the first and second main surfaces, stresses generated above and below the Si wafer 1 cancel each other out, and as a result, a high-quality thin film structure without warpage can be obtained. .

According to the method of manufacturing the thin film structure according to the first embodiment, the first and second 3C-SiC epitaxial growth layers 5 are formed on the first and second main surfaces of the Si wafer 1.
a and 5b, respectively, the stress generated at the heterojunction interface between the Si substrates 7a and 7b and the first and second 3C-SiC epitaxial growth layers 5a and 5b due to lattice mismatch and difference in thermal expansion coefficient. It is possible to prevent cancellation and warp of the thin film structures 8a and 8b. Therefore, it is possible to manufacture a thin film structure including a high-quality, large-area epitaxial growth layer.

Further, according to the method of manufacturing a thin film structure according to the first embodiment, the thin film structure is formed such that the thickness of the remaining Si substrates 7a and 7b is smaller than that of the 3C-Si epitaxially grown C layers 5a and 5b. It is possible to separate the bodies 8a and 8b and influence the crystal structure by stress or the like due to lattice constant mismatch, instead of the 3C-SiC epitaxial growth layers 5a and 5b, instead of the Si substrates 7a and 7b. It is possible to obtain a thin film structure including a large-area epitaxial growth layer without changing the structure of the 3C-SiC epitaxial growth layers 5a and 5b.

Further, according to the method of manufacturing a thin film structure including an epitaxial growth layer according to the first embodiment,
The first and second 3C-SiC epitaxial growth layers 5 are formed not only on one side of the wafer 1 but also on both sides of the Si wafer 1.
In order to deposit a and 5b, the same amount of raw material gas as in the conventional vapor phase epitaxial growth is used, and the same amount of time is spent, whereby the vapor phase epitaxial growth for two wafers can be performed.

The step (g) in the method for manufacturing a thin film structure according to the first embodiment includes the steps of: forming first and second epitaxial growth layers 5 on the first and second main surfaces of the substrate, respectively;
a and 5b, the first and second 3C-Si
This is for separating the first and second thin film structures 8a and 8b composed of the C epitaxial growth layers 5a and 5b from the Si wafer 1 by a plane parallel to the first and second main surfaces. The series of steps (a), (b), (c), and (d) are preparation steps for facilitating separation into the first and second thin film structures 8a and 8b. Although it is not impossible to use a SiC / Si / SiC double heterojunction structure for a semiconductor device, a semiconductor device having a Si / SiC single heterostructure or a thin film structure of only SiC has higher versatility.

As a method of separating into a plurality of thin film structures,
A method is considered in which the first and second 3C-SiC epitaxial growth layers 5a and 5b are grown on the first and second main surfaces of the Si wafer 1 and then the Si wafer 1 is melted in the lateral direction by side etching. However, when such a method is used, the area in contact with the etching solution is small,
Since the volume to be etched is large, it takes a very long time to separate the first and second 3C-SiC thin film structures 8a and 8b from each other. This is a great disadvantage in terms of manufacturing cost for manufacturing semiconductor devices.
As an etching solution used for etching Si, there is a mixed solution of nitric acid (HNO ₃ ) and hydrofluoric acid (HF).
And second 3C-SiC epitaxial growth layers 5a, 5a
There is a concern that b may be adversely affected.

Therefore, the method of manufacturing the thin film structure according to the first embodiment is based on the fact that the first and second 3C-SiC epitaxial growth layers 5a and 5b are deposited before the Si wafer 1 is deposited.
Are formed in advance inside the H ⁺ region. By implanting H ⁺ , H ⁺ enters the position of Si inside the Si wafer 1 and partially cuts bonds between Si atoms. Subsequent first and second 3C-Si
When the C epitaxial growth layers 5a and 5b are deposited, the temperature of the entire Si wafer 1 becomes high and thermal stress is applied, so that H
^{In the +} implantation regions 3a and 3b, the bond between Si atoms is completely cut. On the other hand, the first and second thin film structures 8a and 8b including the first and second 3C-SiC epitaxial growth layers 5a and 5b during the growth of the first and second 3C-SiC epitaxial growth layers 5a and 5b and the Si wafer It is undesirable for 1 to separate. Therefore, when H ⁺ is implanted during epitaxial growth, a bond region in which the H ⁺ implanted regions 3a and 3b are not formed is secured in advance. Thus, the Si wafer 1 is not completely separated during the growth of the first and second 3C-SiC epitaxial growth layers 5a and 5b. And the first and second 3C-
After the SiC epitaxial growth layers 5a and 5b are grown, the first and second thin film structures 8a and 8b are separated from the Si wafer 6 by performing side etching on the bond regions. In this step, since the Si wafer 1 is already partially cut and peeled, the Si region to be finally removed only needs to be a bond region having a small area. Therefore, compared to the case where the H ⁺ implanted regions 3a and 3b are not formed, the time for performing the etching is shorter, and the first and second thin film structures 8a and 8b and the Si wafer 6 can be efficiently separated. .

In the steps (a) and (c), the pattern of the ion implantation masks 2a and 2b to be formed does not have to be in the form of two concentric rings, but may be in other shapes. The method for manufacturing a thin film structure according to the first embodiment can be implemented even if patterns having different shapes are formed on the first main surface and the second main surface of the wafer 1. However, for example, when the bond region remains only in a very small portion of the Si wafer 1, the wafers are bonded to each other only in the bond region during epitaxial growth, and the mechanical strength is weakened. Therefore, the Si wafer 1 is easily peeled off by a small impact force. Therefore, the bond region needs to have a certain large area. Also, from the viewpoint of eliminating the warpage of the substrate, it is necessary to consider the pattern layout of the bond region. If the stress generated at the first main surface and the stress generated at the second main surface are not effectively canceled out, the substrate may be partially warped, and a thin film structure including a high-quality 3C-SiC single crystal thin film may be formed as in the related art. This is because they cannot be obtained. Therefore, it is desirable to have a topology in which atoms are bonded in a plurality of uniformly arranged bond regions and the patterns on the first and second main surface sides are the same. Also, the first
If the second main surface has the same pattern, it is sufficient to prepare one mask pattern in the photolithography method, which is preferable from the viewpoint of working cost. The pattern of the ion implantation masks 2a and 2b may be formed as shown in FIG. When formed in this manner, in the side etching step (g), the etching liquid easily enters the inside, so that the Si wafer 6 and the thin film structures 8a and 8b can be more quickly separated.

In the steps (b) and (d), the projection range of the H ⁺ implanted regions 3a and 3b is set to 1 μm from the surface of the Si wafer 1, but the projection range is not limited to this value. , May be formed in a deeper projection range, or may be formed in a shallower projection range. However, in each of the separated thin film structures 8a and 8b, the 3C-SiC epitaxial growth layer 5 is larger than the remaining Si substrates 7a and 7b.
The H ⁺ implantation region 3 is formed so that the thicknesses of a and 5b are larger.
It is preferable to set the projection ranges of a and 3b. If the 3C-SiC epitaxial growth layers 5a and 5b are thicker than the Si substrates 7a and 7b after separating the thin film structures 8a and 8b, the crystal structure is distorted due to lattice mismatch or the like. This is because the remaining Si substrates 7a and 7b are used instead of 5a and 5b. Therefore, high quality 3C-SiC epitaxial growth layer 5
a and 5b can be obtained. After the thin film structures 8a and 8b and the Si wafer 6 are separated, etching is further added to the thin film structures 8a and 8b.
3C-Si by removing Si substrates 7a and 7b from a and 8b
It is also possible to take out only the C epitaxial growth layers 5a and 5b. However, the obtained thin film structures 8a, 8b
Is used for a semiconductor device such as a lateral MOS transistor or the like, the presence of the Si substrate 7 does not affect the operation of the semiconductor device at all, so the Si substrates 7a and 7b need not be removed.

Rather, the Si substrates 7a and 7b can be used as ohmic contact layers by leaving the Si substrates 7a and 7b finally. As described at the outset, since a wide band gap semiconductor such as SiC is a material closer to an insulator, an impurity diffusion technique has not yet been established. For this reason, it is difficult at present to sufficiently reduce the specific resistance so that the 3C-SiC epitaxial growth layers 5a and 5b can be used as ohmic contact layers. On the other hand, for Si, a technique for obtaining a low resistivity layer that can be easily used as an ohmic contact layer has already been established.

The steps (b) and (d) of proton implantation may be performed after the 3C-SiC epitaxial growth layers 5a and 5b are grown. However, when the projection range to be implanted is increased before the growth of the 3C-SiC epitaxial growth layers 5a and 5b,
Since the thickness can be reduced by the thickness of a and 5b, it is desirable in that the acceleration voltage can be reduced. Especially by proton injection 3
In consideration of the damage to the C-SiC epitaxial growth layers 5a and 5b, it is preferable to perform the process before growing the 3C-SiC epitaxial growth layers 5a and 5b.

(Second Embodiment) In the second embodiment, a hexagonal GaN (hereinafter, referred to as "H-GaN") single crystal thin film is used as the wide band gap semiconductor single crystal thin film of the present invention. A case where both sides are epitaxially grown will be described as an example. Here, a SiC substrate (SiC wafer) 9 is used as a substrate for double-sided epitaxial growth. Compared to the GaN bulk crystal, the SiC bulk crystal is easier to increase the diameter, and the SiC substrate can be obtained as a substrate for epitaxial growth.

Hereinafter, a method of manufacturing a thin film structure including an H-GaN single crystal thin film will be described with reference to FIG. 3, focusing on differences from the first embodiment.

(A) The substrate used is a 4H-SiC wafer 9. A resist is spin-coated on the first main surface of the 4H-SiC wafer 9, and an ion implantation mask 10a having a resist pattern shown in FIGS. 1A and 1B is formed by photolithography.

(B) H ⁺ is implanted into the first main surface of the 4H-SiC wafer 9 using an ion implantation mask 10a as shown in FIG. In the ion implantation, the acceleration energy is set to 150 keV, and the dose is set to 5 × 10 ¹⁶ cm ^−2.
This is the same as the process (b) in the first embodiment, and by changing these values, the 4H-SiC substrate 1 included in the thin film structures 30a and 30b after separation is changed.
The point that the thickness of 5a and 15b can be adjusted is also the same as that of the first embodiment.

(C) The first main surface and the second main surface of the 4H-SiC wafer 9 are inverted to form an ion implantation mask 10b on the second main surface. In the same manner as in the step (a), a resist is spin-coated, and an ion implantation mask 10b having two concentric ring patterns is formed by photolithography as shown in FIGS. 1A and 1B.

(D) Next, H ⁺ implantation is performed on the second main surface of the 4H-SiC wafer 9 using the ion implantation mask 10b. As in the step (b), the depth from the surface is 1 μm.
The H ⁺ implantation region 11b is formed at the position. Thereafter, although not shown, the ion implantation masks 10a and 10b are removed.

(E) Next, after fixing the 4H-SiC wafer 9 in the reaction vessel 18 of the double-sided epitaxial growth apparatus, the AlN buffer layers 12a and 12b are formed. 4H
This is because the difference in lattice constant between the SiC wafer 9 and the H-GaN epitaxial growth layers 13a and 13b is reduced, and the occurrence of defects is suppressed. The raw materials are trimethylaluminum (TMA) and dimethylhydrazine (DM
Hy) is used. 50 nm with substrate temperature of 600 ° C
Laminate to about the thickness.

(F) Next, on both the first and second main planes of the 4H-SiC wafer 9, H-GaN epitaxial growth layers 13a and 13b are simultaneously epitaxially grown on both sides. By alternately supplying trimethylgallium (TMG) and dimethylhydrazine as raw materials, the H-GaN epitaxial growth layers 13a and 13b are epitaxially grown on both sides. The amount of trimethylgallium is 7.6 scc
m, the amount of dimethylhydrazine is 270 sccm, and 3
Grow for 0 minutes.

(G) Finally, the 4H-SiC wafer 14 is separated from the thin film structures 30a and 30b. 4 in advance
H ⁺ implanted regions 11 a and 11 b in H-SiC wafer 9
Is provided, the bond between the Si atom and the C atom in the 4H-SiC wafer 9 is partially cut. H-
GaN epitaxial growth layers 13a and 13b are 4H-S
When depositing on the iC wafer 9, the temperature of the 4H-SiC wafer 9 becomes high and thermal stress is applied, so that H
^{In the +} implantation regions 11a and 11b, the interatomic bonds are completely broken. Therefore, as in the case of the first embodiment, the thin film structures 30a and 30b can be easily and quickly formed on the 4H-SiC wafer 14 by performing side etching on the bond regions other than the H ⁺ implantation regions 11a and 11b. Can be separated from Thus, the first and second thin film structures 30a and 30b including the H-GaN epitaxial growth layers 13a and 13b are obtained.

Conventionally, H-GaN is epitaxially grown on a sapphire substrate. However, since sapphire itself is an insulator, there is a drawback that an electrode cannot be taken out from the back surface of the substrate. In addition, due to the poor thermal conductivity of the sapphire substrate, the sapphire substrate has a drawback that its life is extremely short in high-temperature operation or high-power operation. On the other hand, when 4H—SiC is used as the substrate, the conductivity can be increased by doping the substrate with impurities. Also, the forbidden band width of 4H-SiC is sufficiently large as compared with other semiconductors, and the thermal conductivity is high. Therefore, a semiconductor device in which an H-GaN layer is formed on a 4H-SiC substrate is expected to be able to solve the drawbacks when using a sapphire substrate. On the other hand, when H-GaN is epitaxially grown on a 4H-SiC substrate, defects are more likely to occur than when sapphire is used as the substrate. H using a 4H-SiC substrate
-GaN grown, 4H-SiC and H-GaN
Cracks occur during crystal growth due to differences in the thermal expansion coefficients of the system semiconductors, making it difficult to form a laminated structure having a sufficient thickness. Therefore, a laser diode using H-GaN for the active layer is actually manufactured on a sapphire substrate, but when 4H-SiC is used as a substrate, continuous oscillation at room temperature has not yet been achieved. In the method of manufacturing the thin film structure according to the second embodiment, since high-quality crystals can be obtained by effectively preventing the warpage of the crystals, it is expected that these disadvantages will be solved.

In the method (d) of the method for manufacturing a thin film structure according to the second embodiment, the buffer layer
Not only N but also GaN can be used.

In the method of manufacturing a thin film structure according to the second embodiment, the 4H-SiC substrate is formed by epitaxially growing H-GaN on both the first main surface and the second main surface of the 4H-SiC wafer 9. 15a, 15b and H
H-Ga, which is generated by the stress generated between the -GaN epitaxial growth layers 13a and 13b cancel each other and does not warp,
The first and second thin film structures 30a and 30b including the N epitaxial growth layers 13a and 13b can be manufactured.

In the method of manufacturing a thin film structure according to the second embodiment, both the first main surface and the second main surface of the 4H-SiC wafer 9 are H-GaN in one growth step.
Since the epitaxial growth layers 13a and 13b are epitaxially grown on both sides, the first and second thin film structures 30a and 30b can be efficiently manufactured.

Further, in the method of manufacturing a thin film structure according to the second embodiment, by injecting H ⁺ into 4H—SiC, a bond between Si atoms and C atoms is partially cut. . Therefore, as in the first embodiment, the 4H-SiC wafer 14 and the thin film structures 30a and 30b can be separated easily and in a short time by using the side etching after performing the double-sided epitaxial growth. Become.

(Third Embodiment) A method of manufacturing a thin film structure according to a third embodiment will be described. Here, a method of manufacturing a thin film structure including a cubic GaN (hereinafter, referred to as “C-GaN”) single crystal thin film as the wide band gap semiconductor single crystal thin film of the present invention will be described. As a substrate for double-sided epitaxial growth, a SiC substrate (SiC wafer) 9 manufactured by a process similar to that of the first embodiment is used.

Hereinafter, C-Ga will be described with reference to FIGS.
A method for manufacturing a thin film structure including an N single crystal thin film will be described.

(A) First, a 3C-SiC substrate 40 to be used as a substrate is prepared. As the 3C-SiC substrate 40, a substrate manufactured by a process similar to that of the first embodiment is used.
Unlike the embodiment, H ⁺ for Si wafer 1
No injection step is required. Thin film structure 8 from Si wafer
This is because a and 8b are used as a substrate for double-sided epitaxial growth of a C-GaN single crystal thin film without separation. Other manufacturing methods of the 3C-SiC substrate 40 are described in (C) and (D) of the first embodiment.
Since it can be performed in exactly the same way, the description is omitted here.

(B) In the third embodiment, an H ⁺ implanted region 20a is formed in the 3C-SiC epitaxial growth layer 5a in FIG. After growing the C-GaN epitaxial growth layers 22a and 22b, the thin film structure 23a is
This is for separation from the C-SiC epitaxial growth layer 5a. Step of injecting H ⁺ to form H ⁺ implanted region 20a is in the first embodiment (b), carried out in the same manner as in (b).

(C) Next, the first main part of the 3C-SiC substrate 40
3C-SiC epitaxy by reversing the surface and the second main surface
H in the growth layer 5b⁺An implantation region 20b is formed. C
Growing the GaN epitaxial growth layers 22a and 22b
After that, the thin film structure 23b is subjected to 3C-SiC epitaxial growth.
This is for separating from the growth layer 5b. H⁺And inject H
⁺The step of forming the implantation region 20b is described in the first embodiment.
(C) and (d).

(D) Next, the AlN buffer layers 21a and 21b are formed on the first main surface and the second main surface of the 3C-SiC substrate 40, respectively.
Is deposited. The 3C-SiC substrate 40 was fixed in a double-sided epitaxial growth apparatus, heated to 800 ° C., and trimethylaluminum was 9 sccm and dimethylhydrazine was 55
The growth is performed for 5 minutes by supplying sccm.

(E) C-GaN epitaxial growth layer 2
2a and 22b are simultaneously deposited. 3C-SiC substrate 40
Is heated to 900 ° C. and trimethylgallium is heated to 8 sc
cm, dimethylhydrazine is supplied at 55 sccm,
The epitaxial growth is performed for minutes.

(F) Finally, side etching is performed to remove the thin film structures 23a and 23b from the Si wafers 1 and 3C-S
It is separated from the iC epitaxial growth layers 5a and 5b. SiC remaining under the AlN buffer layers 21a and 21b after the separation is the C-GaN epitaxial growth layers 22a and 22b.
b, the thin film structures 23a, 23
b is not warped, and the thin film structure 23 including the high-quality C-GaN epitaxial growth layers 22a and 22b is formed.
a and 23b can be obtained.

Since 3C-SiC has a similar lattice constant to that of C-GaN, 3C-SiC may be used as a substrate for epitaxial growth of C-GaN. However, conventionally, it was difficult to obtain a high-quality 3C-SiC substrate, and thus a high-quality C-GaN thin film structure epitaxially grown on the substrate could not be obtained. Also, as in the case of conventional SiC or H-GaN, warpage occurs due to differences in lattice constants and thermal expansion coefficients even in epitaxial growth of a C-GaN single crystal thin film. However, as for the 3C-SiC substrate 40, a high-quality substrate can be obtained by the method for manufacturing a thin film structure according to the first embodiment. As described above, the first and second substrates are warped.
This can be prevented by simultaneously epitaxially growing both surfaces on the main surface. Therefore, by these manufacturing methods, the C-GaN epitaxial growth layer 2 having good crystallinity can be obtained.
Thin film structures 23a and 23b including 2a and 22b are obtained.

In the step (A), the pure SiC epitaxial growth layer 5a obtained by completely removing the Si substrate 7a from the SiC thin film structure 8a obtained in the first embodiment by chemical etching is replaced with the SiC substrate. 40 may be used. However, even when used in the state shown in FIG. 2F, since the first and second main surfaces have the high-quality SiC epitaxial growth layers 5a and 5b, it can be used as it is as the 3C-SiC substrate 40.

(Method of Manufacturing Semiconductor Device Using Thin Film Structure) FIG. 7 shows an example of a semiconductor device using the thin film structure of the present invention. That is, the semiconductor device shown in FIG. 7 is a Schottky diode using the thin film structure 8a according to the first embodiment as a base.

The Schottky diode using the thin film structure according to the first embodiment uses the thin film structure 8a in which the n ⁻ -SiC layer 24 is laminated on the upper surface of the n ⁺ -Si layer 28 as a base. A Schottky electrode 26 serving as an anode electrode is provided at the center of the upper surface of the n ^-- SiC layer 24,
Ap ⁺ -SiC region 25 functioning as a guard ring region is provided in an upper region excluding the center and the end of the n ⁻ -SiC layer 24. An ohmic electrode 27 serving as a cathode electrode is provided on the lower surface of the n ⁺ -Si layer 28. The reason why the guard ring region 25 is provided on the n ⁻ -SiC layer 24 is to reduce a leakage current when a reverse voltage is applied. Although the function of the Schottky diode can be achieved without providing the guard ring region 25, when the guard ring region 25 is not provided, the electric field concentrates at the end of the Schottky electrode 26, and the leakage when the reverse voltage is applied is reduced. Since the current increases, it is necessary to provide another measure to reduce the leakage current.

In the Schottky diode shown in FIG. 7, the semiconductor layer (ohmic contact region) 28 in contact with the ohmic electrode 27 has a thickness of 0.006 Ωcm to 0.02 Ωcm (impurity density of 1 × 10 ¹⁹ cm ^{−3 to} 1.5 × 10 ^18).
The formation of the Si substrate 28 having a low specific resistance (cm ⁻³ ) has an advantage that a good ohmic junction can be easily obtained. As described above, it is difficult to lower the specific resistance of the ohmic contact region because the impurity diffusion technology has not been developed for SiC. For this reason, in the case of SiC, it is not easy to lower the value of the contact resistance of the ohmic contact, but on the other hand, for Si, 0.006Ωcm to 0.02Ω.
This is because a cm semiconductor substrate is common as a commercially available specification and can be easily purchased. Important factors that affect the performance of the Schottky diode as a semiconductor device include the magnitude of the on-resistance Ron per unit chip area and the leakage current when a reverse voltage is applied, but the contact resistance at the ohmic junction is reduced. This is important in that it greatly contributes to the reduction of the on-resistance Ron. Therefore, the Schottky diode using the thin film structure of the present invention has an on-resistance Ron
And the conduction loss can be reduced.

The Schottky diode shown in FIG. 7 is manufactured by using the method for manufacturing a 3C-SiC thin film structure shown in the first embodiment. The details will be described below with reference to FIGS.

(A) First, the CZ method, MCZ method, or F
S with specific resistance of 0.006 Ωcm to 0.02 Ωcm grown by Z method
An i-substrate 7 is prepared. Next, the n ⁻ -SiC layer 24 is grown by using the method for manufacturing a thin film structure according to the first embodiment. When the SiC layers 5a and 5b obtained by the method for manufacturing a thin film structure according to the first embodiment are used for a Schottky diode, an n-type dopant is added to a source gas for vapor phase epitaxial growth. Specifically, in addition to the raw material gases acetylene and dichlorosilane,
A small amount of nitrogen (N2) is used as a dopant. Other substrate temperature, pressure in the quartz tube, growth time, separation of the thin film structure 8a from the Si wafer 1, and the like are basically performed in the same manner as the manufacturing method according to the first embodiment. However, the first
After performing the side etching for separating the thin film structure 8a in the step (g) of the embodiment, the Si substrate 7a
The surface of (corresponding to the n ⁺ -Si layer 28 of the Schottky diode) is rough, and it is necessary to planarize the surface of the n ⁺ -Si layer 28 to form the ohmic electrode 27. Therefore, in the manufacturing process of the Schottky diode using the thin film structure according to the first embodiment, CM
A step of flattening the surface of the Si substrate 7a using a P method or the like is added.

(B) Next, a guard ring region 25 is selectively formed in the upper surface region of the n ⁻ -SiC layer 24 in the thin film structure 8a obtained in the step (a). First, n ⁻ −Si
A resist film is spin-coated on the upper surface of the C layer 24, and an ion implantation mask 29 having an opening is formed on a region where the guard ring region 25 is to be formed by photolithography. Then, using this ion implantation mask 29, n ⁻
Top to boron ions -SiC layer 24 ^{(11 B} +)
Inject. ¹¹ B ⁺ implantation is 120 keV, 80 kV
eV, 50 keV, carried out in four steps of 30 keV, the total dose is 3 x10 ¹⁵ cm ^- a ^2. The width of the guard ring region 25 is 100 μm, and the width of the overlapping portion between the guard ring region 25 and the Schottky electrode 26 is 10 μm. The ion implantation is performed at room temperature, and the ion implantation mask 29 is removed after the ion implantation. Thereafter, in order to activate the implanted ions, heat treatment (annealing) is performed in an argon (Ar) gas atmosphere at 1550 ° C. for 30 minutes.

(C) Next, an ohmic electrode 27 is formed below the n ⁺ -Si layer 28. Further, when it is desired to make the surface of the n ⁺ -Si layer 28 have a low specific resistance, n-type impurity ions such as ³¹ P ⁺ , ⁷⁵ As ⁺ are added to the n ⁺ -Si layer 28 before forming the ohmic electrode 27. 3 × 10 ¹⁵ cm ⁻² to
Ion implantation is performed at a high dose of about 8 × 10 ¹⁶ cm ⁻² , and then activation annealing is performed at 1000 ° C. for about 30 minutes. Al is generally used as the metal material of the ohmic electrode 27, but aluminum alloy (Al—Si, Al
-Cu-Si) or the like may be used. Any other metal that can provide a good ohmic junction can be used as the material of the ohmic electrode 27. Ohmic electrode 2
7 performs deposition by metal vapor deposition or sputtering. Thereafter, sintering is performed in an H ₂ atmosphere at about 400 ° C. to 450 ° C. in order to realize an ohmic junction with low contact resistance.

(D) Finally, a Schottky electrode 26 is formed on the upper surface of the n ⁻ −SiC layer 24. First, a resist film is formed on the surface of the n ⁻ -SiC layer 24 by spin coating, and the Schottky electrode 2 is formed by photolithography.
A resist having a pattern having an opening in a region 6 to be formed is formed. Next, a metal material such as titanium (Ti) or gold (Au) used for the Schottky electrode 26 is deposited on the surface of the n ⁻ −SiC layer 24 by vapor deposition or sputtering. Thereafter, the resist and the metal material attached to the resist are removed by a lift-off method, so that the Schottky electrode 26 is formed.

Through the above steps, a Schottky diode using the thin film structure according to the first embodiment is completed.

When performing annealing for activation after injecting ¹¹ B ⁺ into the area where the guard ring region 25 is to be formed in the step (b), the 3C-SiC substrate 40 is placed in a polycrystalline SiC container. Is also effective. This is to prevent the stoichiometric composition shift due to the sublimation of Si among the atoms near the surface due to the high temperature and the crystal surface from being roughened.

The obtained Schottky diode is a conventional one.
Compared to Schottky diodes using SiC,
Si is used for the semiconductor layer in contact with the mic electrode 27
Therefore, the effect of realizing a low on-resistance Ron
Have. Also, this Schottky diode is the first
Since a simple manufacturing method according to the embodiment is used, n ⁺
-Special means must be used to provide the Si layer 28.
No need. The method of forming the ohmic electrode 27 is also
Easy to use technology that has been used for conventional Si
Manufacturing high-performance Schottky diodes in the manufacturing process
be able to.

Further, according to the method of manufacturing a thin film structure of the present invention, SiC can be grown on a large-diameter Si wafer, so that a large number of Schottky diodes can be manufactured in one lot. Manufacturing costs can be kept low.

(Other Embodiments) As described above, the present invention has been described with reference to the first to third embodiments. However, the description and drawings constituting a part of this disclosure limit the present invention. You should not understand that there is. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, in the first embodiment,
3C-SiC films 4a, 4b by carbonizing the surface of wafer 1
After the formation of 3C-SiC epitaxial growth layer 5
a and 5b are grown, but the 3C-SiC films 4a and 4b
May be grown instead of forming a SiC buffer layer, and then the 3C-SiC epitaxial growth layers 5a and 5b may be grown. By providing a SiC buffer layer between the Si wafer 1 and the 3C-SiC epitaxial growth layers 5a and 5b, it is possible to reduce defects in the SiC crystal. The method of manufacturing the thin film structure described in the first to third embodiments is merely an example. For example, in the process of double-sided epitaxial growth, the supply amount of the raw material, the pressure in the quartz tube, the growth time, and the like should be appropriately adjusted to set optimal conditions, and are not limited to the values described in the embodiment. The same applies to the selection of raw materials.

The semiconductor device using the thin film structure is not limited to the Schottky diode illustrated. Bipolar transistor (BJT), vertical field effect transistor (FET), insulated gate bipolar transistor (IGBT), static induction transistor (S
IT), gate turn-off thyristor (GTO thyristor), electrostatic induction thyristor (SI thyristor), pin
The thin film structure of the present invention can be used as a base of various semiconductor devices using a wide band gap semiconductor such as a diode. Further, the thin film structure of the present invention can be used as a base of various semiconductor light emitting devices such as LEDs and laser diodes. In particular, a favorable ohmic electrode can be realized by using a material constituting the thin film structure with a material having a smaller forbidden band width than that of the epitaxial growth layer and using the substrate as an ohmic contact region. Therefore, the ohmic contact region using this substrate can be used as a semiconductor region that becomes either the emitter region or the collector region in BJT or IGBT. In a vertical FET or SIT, an ohmic contact region can be used as a semiconductor region to be either a source region or a drain region. In an SI thyristor, a GTO thyristor, a diode, or the like, an ohmic contact region can be used as a semiconductor region to be one of an anode region and a cathode region.

In the manufacturing process of the exemplified Schottky diode, it has been shown that the n-type impurity ions are implanted before the ohmic electrode 27 is formed. Impurity ions are selectively implanted, and IGBT, SI thyristor, GTO
An anode short region of the thyristor may be formed.

In the first to third embodiments, Sic and GaN are exemplified as wide band gap semiconductors. However, ZnTe, CdS, ZnSe, ZnS,
Of course, other semiconductor materials such as diamond may be used.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0085]

As described above, according to the present invention,
It is possible to provide a method of manufacturing a thin film structure having a heteroepitaxial structure in which warpage does not easily occur on the epitaxial growth layer side.

Further, according to the present invention, there is provided a method for producing a thin film structure having higher productivity suitable for mass production even for a material such as a wide band gap semiconductor material in which a large diameter bulk crystal is difficult to obtain. Can be.

[Brief description of the drawings]

FIG. 1 is a plan view (a) and a sectional view (b) showing a pattern of an ion implantation mask used in the first and second embodiments, and a plan view (c) showing another pattern.

FIG. 2 is a cross-sectional view illustrating the method for manufacturing the thin film structure according to the first embodiment.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a thin film structure according to a second embodiment.

FIG. 4 is a sectional view of a semiconductor wafer holding device in the double-sided epitaxial growth device.

FIG. 5 is a lateral view showing a main part of a double-sided epitaxial growth apparatus.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a thin-film structure according to a third embodiment.

FIG. 7 is a cross-sectional view illustrating a semiconductor device using a thin film structure.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device using a thin film structure.

[Explanation of symbols]

Reference Signs List 1 Si wafer 2, 2a, 2b, 10a, 10b, 29 Ion implantation mask 3a, 3b, 11a, 11b, 20a, 20b H ⁺ implantation region 4a, 4b 3C-SiC film 5a, 5b 3C-SiC epitaxial growth layer 6 Si wafer 7a, 7b Si substrate 8a, 23a, 30a First thin film structure 8b, 23b, 30b Second thin film structure 9 4H-SiC wafer 12a, 12b AlN buffer layer 13a, 13b H-GaN epitaxial growth layer 144H-SiC wafer 15a , 15b 4H-SiC substrate 16 semiconductor wafer holding device 16a, 16b wafer holder 17 semiconductor wafer 18 quartz tube 19 heating coil 21a, 21b AlN buffer layer 22a, 22b C-GaN epitaxial layer 24 n ^- -SiC layer 25 p ⁺ SiC region 26 Schottky electrode 27 ohmic electrode 28 n ⁺ -Si layer 39 and 39a, 39 b connecting portion 40 3C-SIC substrate

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F045 AB06 AB09 AB14 AC01 AC05 AC08 AD10 AD12 AD14 AE17 AE19 AF02 AF03 AF13 BB11 BB12 DA53 DA61 DA63 DP20 DQ06 EE12 EE19 EK02 EM02 EM09 GB06 HA05 HA14

Claims (5)

[Claims] A step of providing a substrate separation layer inside a substrate having first and second main surfaces; and a first epitaxial growth layer made of a material different from the substrate on the first main surface in the same reaction vessel. Simultaneously depositing a second epitaxial growth layer made of the same material as the first epitaxial growth layer on the second main surface; and separating the first epitaxial growth layer by separating the substrate using the substrate separation layer. Obtaining a second thin film structure including the first thin film structure including the second epitaxial growth layer. 2. The method according to claim 1, wherein the thickness of the substrate included in the first thin film structure is smaller than the thickness of the first epitaxial growth layer. 3. The material different from the substrate is 2.2 eV.
3. The method for manufacturing a thin film structure according to claim 1, wherein the semiconductor is a wide bandgap semiconductor having a wider forbidden band. 4. The method according to claim 3, wherein the wide bandgap semiconductor is silicon carbide or gallium nitride. 5. The method for manufacturing a thin film structure according to claim 1, wherein the step of providing the substrate separation layer includes a step of injecting protons into the substrate.