CN216773244U

CN216773244U - MIM capacitor

Info

Publication number: CN216773244U
Application number: CN202022921124.7U
Authority: CN
Inventors: 张拥华; 李朝勇; 贺忻; 李明; 王保
Original assignee: Galaxycore Shanghai Ltd Corp
Current assignee: Galaxycore Shanghai Ltd Corp
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2022-06-17
Anticipated expiration: 2030-12-09

Abstract

The utility model provides an MIM capacitor, which is characterized in that at least one dielectric buffer layer is arranged between an upper electrode plate and a lower electrode plate of the capacitor and a capacitor dielectric layer with a high dielectric constant and is used as a buffer transition layer between the high dielectric constant dielectric layer and the upper electrode plate and the lower electrode plate, so that a good contact interface can be provided, the high stress caused by the high dielectric constant dielectric layer material and the interlayer layering defect caused by the high stress are reduced, the capacitor breakdown voltage is improved, the reliability of the whole capacitor structure is improved, the higher capacitor density is maintained, and the requirement of a high-performance chip is met.

Description

MIM capacitor

Technical Field

The utility model relates to an MIM capacitor.

Background

Existing capacitors can be roughly classified into a front-channel capacitor such as a MOS capacitor and a PN junction capacitor, and a back-channel capacitor such as an MIM (metal layer-insulator-metal layer) capacitor and an MOM (metal layer-oxide-metal layer) capacitor. MIM capacitors provide better frequency and temperature dependent characteristics, and may be formed in inter-level metal and copper interconnect processes to reduce integration difficulty and complexity with CMOS front-end processes, and are therefore widely used in a variety of integrated circuits such as analog-logic, analog-digital, mixed-signal, and rf circuits.

The MIM capacitor structure generally includes a capacitor bottom plate (metal layer) 101, a capacitor dielectric layer (insulating layer) 102 and a capacitor top plate (metal layer) 103 as shown in fig. 1, and a sandwich structure 110 is formed between two metal electrodes and the insulating dielectric layer is sandwiched between the two metal electrodes.

With the improvement of the integration level of semiconductor technology and the performance requirement of chips, the demand for large-capacity capacitors is also increasing, however, the chip area is continuously reduced along with the development of the technology, the relative area provided by the surface energy of each chip to the capacitor is reduced, and thus the capacitor density needs to be improved to meet the demand of high-performance chips.

The methods for improving the density of the MIM capacitor mainly comprise the following steps: a composite structure of two or more layers of MIM capacitors 110 connected in parallel is used, and a capacitor dielectric layer 102 with a high dielectric constant K is used. The former needs to add a plurality of metal connecting layers, and has complex process and high cost. The latter is widely used by high-performance chips and advanced processes because of the relatively simple process flow without additionally adding a photomask layer. However, the preparation equipment, preparation process and process control requirements of the high-K dielectric layer are high, and the high-K dielectric layer material is generally high in hardness and has high stress difference with a combined interface of an upper polar plate and a lower polar plate of the capacitor, so that the problems of interlayer delamination defect and low breakdown voltage are caused.

In addition, in high-pixel and high-performance CMOS image sensor applications, a high-density capacitor needs to be configured for each pixel unit, and the area of all capacitors occupies more than half of the area of the whole chip, thereby more easily causing interlayer delamination defects and reliability problems of the capacitors.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide an MIM capacitor, which reduces the internal stress of a capacitor structure, reduces the interlayer lamination defect and improves the breakdown voltage of the capacitor, thereby improving the reliability of the whole capacitor structure, maintaining higher capacitor density and meeting the requirement of a high-performance chip.

Based on the consideration, the utility model provides an MIM capacitor, which sequentially comprises a capacitor lower electrode plate, a capacitor dielectric layer with high dielectric constant and a capacitor upper electrode plate; the capacitor further comprises at least one dielectric buffer layer positioned between the capacitor lower polar plate and the capacitor dielectric layer and/or between the capacitor dielectric layer and the capacitor upper polar plate.

Preferably, the dielectric buffer layer comprises any one of titanium and tantalum or a combination thereof.

Preferably, the thickness of the dielectric buffer layer is 5nm-15 nm.

Preferably, the dielectric constant of the capacitance dielectric layer is greater than 7.

Preferably, the capacitor dielectric layer comprises any one of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide and tantalum oxide or a combination thereof.

Preferably, the capacitor lower plate and the capacitor upper plate comprise any one of tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten nitride, aluminum and copper or a combination thereof.

Preferably, the MIM capacitor is applied to a CMOS image sensor chip.

According to the MIM capacitor, at least one dielectric buffer layer is arranged between the upper and lower electrode plates of the capacitor and the capacitor dielectric layer with the high dielectric constant and serves as a buffer transition layer between the high dielectric constant dielectric layer and the upper and lower electrode plates, so that a good contact interface can be provided, the high stress caused by the high dielectric constant dielectric layer material and the interlayer delamination defect caused by the high stress can be reduced, the capacitor breakdown voltage can be improved, the reliability of the whole capacitor structure can be improved, the higher capacitor density can be maintained, and the requirement of a high-performance chip can be met.

Drawings

Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a prior art MIM capacitor;

FIG. 2 is a flow chart of a method of forming a MIM capacitor according to the present invention;

fig. 3-7 are schematic diagrams illustrating a process of forming a MIM capacitor according to the present invention.

In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.

Detailed Description

In order to solve the problems in the prior art, the utility model provides the MIM capacitor, at least one dielectric buffer layer is arranged between the upper and lower electrode plates of the capacitor and the capacitor dielectric layer with high dielectric constant and is used as a buffer transition layer between the high dielectric constant dielectric layer and the upper and lower electrode plates, so that a good contact interface can be provided, the high stress caused by the high dielectric constant dielectric layer material and the interlayer layering defect caused by the high stress are reduced, the capacitor breakdown voltage is improved, the reliability of the whole capacitor structure is improved, the higher capacitor density is maintained, and the requirement of a high-performance chip is met.

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the utility model may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the utility model. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

The present invention will be described in detail with reference to specific examples.

FIG. 2 illustrates a method for forming a MIM capacitor according to the present invention, which comprises sequentially forming a capacitor lower plate, a capacitor dielectric layer with a high dielectric constant, and a capacitor upper plate; and forming at least one dielectric buffer layer between the capacitor lower electrode plate and the capacitor dielectric layer and/or between the capacitor dielectric layer and the capacitor upper electrode plate.

Fig. 3-7 illustrate the formation of a MIM capacitor according to the present invention.

Referring to fig. 3, a base 200 is first provided, where the base 200 is generally a semiconductor substrate (e.g., a wafer) with an insulating isolation layer deposited on the surface. Specifically, the underlying metal on the wafer surface may be polished by Chemical Mechanical Polishing (CMP), and then an insulating isolation layer is formed by one or more combinations of Physical Vapor Deposition (PVD), such as ionized PVD (I-PVD), Chemical Vapor Deposition (CVD), such as high density plasma CVD (hdpcvd), plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), such as plasma enhanced ALD (PE-ALD), or other suitable processes, and then further surface fine planarization and surface pretreatment are performed on the insulating isolation layer by CMP again to ensure that the subsequent MIM capacitor structure is prepared on a flat and clean substrate surface.

Referring to fig. 4-5, a capacitor bottom plate 201, a dielectric buffer layer 204, a capacitor dielectric layer 202, a dielectric buffer layer 204, and a capacitor bottom plate 203 are sequentially deposited on the surface of the flat and clean substrate 200 by one or more combined methods of Physical Vapor Deposition (PVD), such as ionized PVD (I-PVD), Chemical Vapor Deposition (CVD), such as high density plasma CVD (hdpcvd), plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), such as plasma enhanced ALD (PE-ALD), or other suitable processes. And then sequentially forming a capacitor upper plate pattern and a capacitor lower plate pattern by processes of photoetching, etching, cleaning and the like, thereby forming a sandwich structure 210 embedded with the dielectric buffer layer 204 as shown in fig. 5.

The capacitor dielectric layer 202 is made of a material having a high dielectric constant K greater than 7, and preferably, the capacitor dielectric layer 202 includes any one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide.

The capacitor bottom plate 201 and the capacitor top plate 203 comprise one or a combination of tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten nitride, aluminum, and copper.

Wherein the dielectric buffer layer 204 preferably has good adhesion to the capacitor dielectric layer 202, and a material having good adhesion with the capacitor lower plate 201 and the capacitor upper plate 203, and further preferably, the dielectric buffer layer 204 comprises any one or a combination of titanium and tantalum, because titanium and tantalum are naturally oxidized to form titanium oxide and tantalum oxide, which also have relatively high dielectric constant K, but lower hardness than the material of the capacitor dielectric layer 202, can be used as a buffer transition layer between the capacitor dielectric layer 202 and the upper and

lower electrode plates

201 and 203, provides a good contact interface, reduces high stress caused by the material of the capacitor dielectric layer 202 and interlayer delamination defect caused by the high stress, improves the breakdown voltage of the capacitor, therefore, the reliability of the whole capacitor structure is improved, higher capacitor density is maintained, and the requirement of a high-performance chip is met.

Those skilled in the art can understand that the dielectric buffer layer 204 between the capacitor lower plate 201 and the capacitor dielectric layer 202 and the dielectric buffer layer 204 between the capacitor dielectric layer 202 and the capacitor upper plate 203 may exist separately or simultaneously, and may be a single-layer structure or a multi-layer structure. That is, at least one dielectric buffer layer 204 is disposed between the upper and

lower capacitor plates

201 and 203 and the capacitor dielectric layer 202 with high dielectric constant, so that the interlayer delamination defect caused by high stress and high stress caused by the material of the dielectric layer 202 with high dielectric constant can be reduced, the breakdown voltage of the capacitor can be increased, the reliability of the whole capacitor structure can be improved, and the high capacitor density can be maintained. In addition, the thickness of the dielectric buffer layer 204 can be set according to the specific material and thickness selected for each layer, and is typically 5nm to 15 nm.

Referring to fig. 6-7, again by Physical Vapor Deposition (PVD), such as ionized PVD (I-PVD), Chemical Vapor Deposition (CVD), such as high density plasma CVD (hdpcvd), plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), such as plasma enhanced ALD (PE-ALD) or other suitable processes, or a combination of one or more methods, an insulating wrapping 205 covering the sandwich structure 210 is deposited and the surface of the insulating wrapping 205 is planarized by means of CMP, and finally the contact layer 206 of the upper plate 203 and the contact layer 207 of the lower plate 201 are respectively led out as positive and negative electrodes of the MIM capacitor by a mature damascene through-hole metal interconnection process of tungsten, aluminum or copper.

As shown in fig. 7, the MIM capacitor of the present invention sequentially includes a capacitor bottom plate 201, a capacitor dielectric layer 202 with a high dielectric constant, and a capacitor top plate 203; and at least one dielectric buffer layer 204 positioned between the capacitor lower plate 201 and the capacitor dielectric layer 202 and/or between the capacitor dielectric layer 202 and the capacitor upper plate 203.

Preferably, the thickness of the dielectric buffer layer is 5nm-15 nm.

Preferably, the capacitor lower plate and the capacitor upper plate comprise any one or a combination of tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten nitride, aluminum and copper.

The MIM capacitor is particularly suitable for CMOS image sensor chips, can solve the problems of interlayer lamination defects and reliability of the capacitor while providing higher capacitor density, and meets the application requirements of high-pixel and high-performance CMOS image sensors.

In summary, in the MIM capacitor of the present invention, at least one dielectric buffer layer is disposed between the upper and lower electrode plates of the capacitor and the capacitor dielectric layer with a high dielectric constant, which is used as a buffer transition layer between the high dielectric constant dielectric layer and the upper and lower electrode plates, so as to provide a good contact interface, reduce high stress caused by the high dielectric constant dielectric layer material and interlayer delamination defect caused by high stress, and improve the breakdown voltage of the capacitor, thereby improving the reliability of the whole capacitor structure, maintaining a high capacitor density, and meeting the requirement of high performance chips.

It will be evident to those skilled in the art that the utility model is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims

1. An MIM capacitor, characterized in that,

the capacitor comprises a capacitor lower polar plate, a capacitor dielectric layer with high dielectric constant and a capacitor upper polar plate in sequence;

the capacitor further comprises at least one dielectric buffer layer located between the capacitor lower electrode plate and the capacitor dielectric layer and/or between the capacitor dielectric layer and the capacitor upper electrode plate, the dielectric buffer layer is any one or combination of titanium and tantalum, and the thickness of the dielectric buffer layer is 5nm-15 nm.

2. The MIM capacitor according to claim 1 wherein the capacitor dielectric layer has a dielectric constant greater than 7.

3. The MIM capacitor according to claim 1 wherein the capacitor dielectric layer comprises any one or combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide.

4. The MIM capacitor according to claim 1 wherein the capacitor bottom plate and the capacitor top plate comprise any one or combination of tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten nitride, aluminum, copper.

5. The MIM capacitor according to claim 1 wherein the MIM capacitor is used in a CMOS image sensor chip.