CN216749882U - Double-chip frame - Google Patents

Double-chip frame Download PDF

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Publication number
CN216749882U
CN216749882U CN202220147514.XU CN202220147514U CN216749882U CN 216749882 U CN216749882 U CN 216749882U CN 202220147514 U CN202220147514 U CN 202220147514U CN 216749882 U CN216749882 U CN 216749882U
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China
Prior art keywords
chip
frame
seat
dual
double
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CN202220147514.XU
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Chinese (zh)
Inventor
陈盛隆
叶敏
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Parker Microelectronics Shenzhen Co ltd
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Parker Microelectronics Shenzhen Co ltd
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Priority to CN202220147514.XU priority Critical patent/CN216749882U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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Abstract

The utility model relates to a two core chip frame, this two core chip frame include transfer chain, first frame, second frame, two core chip and solder. The first chip base is connected with the first line body through the first pin, and the second chip base is connected with the second line body through the second pin. The first chip seat and the second chip seat are arranged up and down, and a gap is arranged between the first chip seat and the second chip seat. The double-chip is positioned in the gap, one side of the double-chip is tightly attached to the first mounting position of the first chip seat, and the other side of the double-chip is tightly attached to the two second mounting positions of the second chip seat. The double-chip is connected with the first chip seat and the second chip seat through welding flux in a welding mode. The first chip seat encapsulates two chips through a first installation position simultaneously, and the second chip seat encapsulates two corresponding chips respectively through two second installation positions, and the horizontal direction separately sets up, provides more process space, and the encapsulation operation of two chips does not influence each other, has improved the efficiency of encapsulation greatly.

Description

Double-chip frame
Technical Field
The utility model relates to a semiconductor package equipment field, in particular to two core chip frames.
Background
SMA, SMB and SMC are all chip packaging unit models of small electronic components, the packaging units are rectangular, each packaging unit comprises a chip area, and the packaging units are suitable for single-core structures or multi-core laminated structures. The single-core structure can only be packaged one time, and the multi-core lamination structure can be used for packaging a plurality of chips at the same time, but the chips can be influenced mutually in the packaging process, so that the packaging efficiency is low.
It is desirable to provide a dual chip frame to solve the above problems.
SUMMERY OF THE UTILITY MODEL
The utility model relates to a two core chip frame, this two core chip frame include transfer chain, first frame, second frame, two core chip and solder. The first chip seat on the first frame is connected with the first line body through the first pin, and the second chip seat on the second frame is connected with the second line body through the second pin. The first chip seat and the second chip seat are arranged up and down, a gap is formed between the first chip seat and the second chip seat, a first installation position is arranged on the first chip seat, two second installation positions are arranged on the second chip seat, and the first installation position and the second installation positions are arranged in opposite directions. The double-chip is positioned in the gap, one side of the double-chip is tightly attached to the first mounting position of the first chip seat, and the other side of the double-chip is tightly attached to the two second mounting positions of the second chip seat. The solder is used for welding connection of the dual-chip with the first chip holder and the second chip holder. The first chip base encapsulates two chips through a first installation position simultaneously, and the second chip base encapsulates two corresponding chips respectively through two second installation positions, and the horizontal direction separately sets up, provides more process space, and the encapsulation operation of two chips does not influence each other, has improved the efficiency of encapsulation greatly, has solved among the prior art because of the encapsulation unit only is applicable to single core structure or multicore lamination structure and has leaded to the lower problem of encapsulation efficiency.
In order to solve the above problems, the present invention comprises: a dual-chip die frame for packaging a die of a dual-chip configuration, comprising:
the conveying line comprises a first line body and a second line body, and the first line body and the second line body are arranged in parallel;
the first frame comprises a first pin and a first chip seat; one end of the first pin is fixedly connected with the first line body, and the other end of the first pin is fixedly connected with the first chip base; the first chip seat is provided with a first mounting position;
a second frame including a second lead and a second die pad; one end of the second pin is fixedly connected with the second wire body, and the other end of the second pin is fixedly connected with the second chip base; two second mounting positions are arranged on the second chip seat; the second chip seat is positioned above the first chip seat, and a gap is arranged between the second chip seat and the first chip seat;
the double-chip is arranged in the gap, and one chip in one side of the double-chip corresponds to one second mounting position; the other side of the double-chip is positioned at the first mounting position; and the number of the first and second groups,
and the solder is positioned on two sides of the double-chip and used for connecting the double-chip with the first chip seat and the second chip seat.
Two core chip frame in, the second chip seat includes two pedestals, every all be provided with one on the pedestal the second installation position, the adjacent one side of two chips of being convenient for weld improves encapsulation efficiency. Each seat body comprises a second platform body, the second platform bodies are located on the second installation positions, and the two second platform bodies are respectively connected with the two chips of the double-chip in a one-to-one correspondence mode. The one-to-one pressing setting improves the packaging effect of the chip.
Further, the second pin includes two pin bodies, and each pin body is correspondingly connected to one of the seats. The installation is torn open conveniently, when one of them the pedestal need be changed the maintenance when, only need change this one can, is favorable to practicing thrift the cost.
Furthermore, the second frame further comprises a second connecting block, the pin body and the base body are respectively connected with two ends of the second connecting block, the pin body and the base body are arranged in a staggered manner, and the pin body is located below one side of the base body. The staggered arrangement can provide more packaging space and improve the packaging efficiency.
Furthermore, the first frame further comprises a first connecting block, the first pin and the first chip seat are respectively connected with two ends of the first connecting block, the first pin and the first chip seat are arranged in a staggered mode, and the first pin is located above the first chip seat. The staggered arrangement can provide more packaging space and improve the packaging efficiency.
Furthermore, the distance between the lower surface of the first pin and the upper surface of the first chip seat is equal to the distance between the upper surface of the pin body and the lower surface of the seat body, so that a dual-chip is positioned between the first chip seat and the second chip seat, and packaging is facilitated.
Further, the pedestal sets up to the cuboid structure, the second stage body sets up to trapezoidal platform structure, improves and presses the effect, practices thrift the cost.
Furthermore, the first chip seat comprises a first platform body, the first platform body is located at the first installation position, the area of one side, in contact with the double-chip, of the first platform body is larger than the area of the two chips in the double-chip, and the pressing effect is improved.
Furthermore, the thickness of the first frame is equal to that of the second frame, so that the cost is saved.
Furthermore, the double-chip comprises a positioning plate and two positioning grooves, wherein the two positioning grooves are arranged in parallel on the positioning plate, and the two chips are correspondingly arranged in the two positioning grooves respectively, so that the packaging efficiency is improved.
The utility model discloses owing to adopted foretell two core chip frames, compare in prior art, its beneficial effect is: the utility model relates to a two core chip frame, this two core chip frame include transfer chain, first frame, second frame, two core chip and solder. The first chip seat on the first frame is connected with the first line body through the first pin, and the second chip seat on the second frame is connected with the second line body through the second pin. The first chip seat and the second chip seat are arranged up and down, a gap is formed between the first chip seat and the second chip seat, a first installation position is arranged on the first chip seat, two second installation positions are arranged on the second chip seat, and the first installation position and the second installation positions are arranged in opposite directions. The double-chip is positioned in the gap, one side of the double-chip is tightly attached to the first mounting position of the first chip seat, and the other side of the double-chip is tightly attached to the two second mounting positions of the second chip seat. The solder is used for welding connection of the dual-chip with the first chip holder and the second chip holder. The first chip base encapsulates two chips through a first installation position simultaneously, and the second chip base encapsulates two corresponding chips respectively through two second installation positions, and the horizontal direction separately sets up, provides more process space, and the encapsulation operation of two chips does not influence each other, has improved the efficiency of encapsulation greatly, has solved among the prior art because of the encapsulation unit only is applicable to single core structure or multicore lamination structure and has leaded to the lower problem of encapsulation efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments are briefly introduced below, and the drawings in the following description are only corresponding drawings of some embodiments of the present invention.
Fig. 1 is a front view of an embodiment of a dual chip frame according to the present invention.
Fig. 2 is a side view of an embodiment of a dual chip frame of the present invention.
Fig. 3 is a schematic diagram of an embodiment of a first frame on a first line of a dual chip frame according to the present invention.
Fig. 4 is a schematic diagram of an embodiment of a second frame on a second line of a dual chip frame according to the present invention.
Fig. 5 is a schematic diagram of an embodiment of a dual-chip of the dual-chip frame according to the present invention.
Fig. 6 is a front view of an embodiment of a first frame of a dual chip frame according to the present invention.
Fig. 7 is a side view of an embodiment of a first frame of a dual chip frame of the present invention.
Fig. 8 is a front view of an embodiment of a second frame of a dual chip frame according to the present invention.
Fig. 9 is a side view of an embodiment of a second frame of a dual chip frame according to the present invention.
In the figure: 10. the dual-chip module comprises a dual-chip frame, 20 conveying lines, 21 first lines, 22 second lines, 30 first frames, 31 first pins, 32 first connecting blocks, 33 first chip seats, 331 first table bodies, 40 second frames, 41 second pins, 411 pin main bodies, 42 second connecting blocks, 43 second chip seats, 431 seat bodies, 432 second table bodies, 50 dual-chip chips, 51 positioning grooves, 52 positioning plates and 60 solder.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.
In the present invention, the directional terms, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", "top" and "bottom", refer to the orientation of the drawings, and the directional terms are used for illustration and understanding, but not for limiting the present invention.
In the drawings, elements having similar structures are denoted by the same reference numerals.
Referring to fig. 1 and fig. 2, in the present embodiment, the dual chip frame 10 includes a transmission line 20, a first frame 30, a second frame 40, a dual chip 50 and a solder 60. The conveying line 20 includes a first line body 21 and a second line body 22, and the first line body 21 and the second line body 22 are arranged in parallel. Referring to fig. 3 and 4, a plurality of groups of first frames 30 are disposed on the first wire 21 at intervals, a plurality of groups of second frames 40 are disposed on the second wire 22 at intervals, and the first frames 30 and the second frames 40 are disposed in a one-to-one correspondence. Referring to fig. 5, the dual-chip 50 includes a positioning plate 52 and two positioning grooves 51, the two positioning grooves 51 are disposed on the positioning plate 52 in parallel, and the two chips are disposed in the two positioning grooves 51 respectively, so as to improve the packaging efficiency.
In the present embodiment, referring to fig. 6 and 7, the first frame 30 includes first leads 31, first connecting blocks 32 and a first die pad 33. One end of the first lead 31 and one end of the first chip holder 33 are respectively connected to two ends of the first connecting block 32, the first lead 31 and the first chip holder 33 are arranged in a staggered manner, and the first lead 31 is located above the first chip holder 33. The staggered arrangement can provide more packaging space and improve the packaging efficiency. The other end of the first pin 31 is fixedly connected to the first wire 21. The first die pad 33 includes a first stage 331 thereon, and the first stage 331 is located at a first mounting position of the first die pad 33. The first platform 331 is configured as a trapezoidal platform structure, which improves the pressing effect between the first platform 331 and the dual chip 50. Meanwhile, the side surface of the first platform 331 is inclined, so that the contact area between the first platform 331 and the dual-chip 50 through the solder 60 can be increased, and the packaging effect can be improved. The area of the first platform 331 on the side contacting the dual-chip 50 is larger than the area of the area where the two chips are located in the dual-chip 50, so that the first platform 331 can cover the two chips, and the pressing effect is improved.
Wherein the first leads 31 are disposed parallel to the first die pad 33, the first leads 31, the second connecting block 42 and the first die pad 33 have the same thickness, and the thickness of the first die pad 33 described herein does not include the thickness of the first stage 331.
In the present embodiment, referring to fig. 8 and 9, the second frame 40 includes second leads 41, a second connection block 42 and a second die pad 43. The second chip seat 43 includes two seat bodies 431, and each seat body 431 is provided with a second mounting position, so that the adjacent side of the two chips can be welded conveniently, and the packaging efficiency can be improved. Each base body 431 includes a second platform body 432 thereon, the second platform body 432 is located at the second mounting position, and the two second platform bodies 432 are respectively connected with the two chips of the dual-chip 50 in a one-to-one correspondence manner. The one-to-one pressing setting improves the packaging effect of the chip. Pedestal 431 sets up to the cuboid structure, and second stage 432 sets up to trapezoidal platform structure, improves and presses the effect, practices thrift the cost.
The second lead 41 includes two lead bodies 411, and one end of each lead body 411 is correspondingly connected to one of the seats 431. The mounting and dismounting are convenient, when one of the seat bodies 431 needs to be replaced and maintained, only the seat body needs to be replaced, and the cost is saved. The other end of the lead body 411 is fixedly connected to the second wire 22, and two adjacent lead bodies 411 are arranged in parallel.
The thickness of the first frame 30 is equal to the thickness of the second frame 40, the thicknesses of the first lead 31 and the second chip seat 43 are the same, the thicknesses of the first chip seat 33 and the second lead 41 are the same, the two-chip frame is greatly compatible with the traditional two-chip frame, a plastic package mold and a pin bending mold can be shared, and cost is saved.
The dual chip 50 is placed on the first stage 331 of the first chip holder 33 such that the two chips are correspondingly connected to the two second stages 432, respectively. The solder 60 is arranged on the upper and lower peripheries of the two chips, so that the solder 60, the chips and the corresponding table bodies are welded into a whole during welding, and firm packaging is ensured. Two chips all have the second stage 432 that corresponds to cooperate with first stage 331 to press, and two chips set up on the horizontal direction, consequently, can encapsulate the operation to two chips simultaneously, do not influence each other, improve the efficiency of encapsulation. Moreover, the SMB frame can realize a multi-core structure on the existing die equipment, lamination is not needed, and the existing equipment and the packaging appearance can be well compatible.
In this embodiment, the utility model relates to a two chip frame, this two chip frame includes transfer chain, first frame, second frame, two chip and solder. The first chip seat on the first frame is connected with the first line body through the first pin, and the second chip seat on the second frame is connected with the second line body through the second pin. The first chip seat and the second chip seat are arranged up and down, a gap is formed between the first chip seat and the second chip seat, a first installation position is arranged on the first chip seat, two second installation positions are arranged on the second chip seat, and the first installation position and the second installation positions are arranged in opposite directions. The double-chip is positioned in the gap, one side of the double-chip is tightly attached to the first mounting position of the first chip seat, and the other side of the double-chip is tightly attached to the two second mounting positions of the second chip seat. The solder is used for welding connection of the dual-chip with the first chip holder and the second chip holder. The first chip base encapsulates two chips through a first installation position simultaneously, and the second chip base encapsulates two corresponding chips respectively through two second installation positions, and the horizontal direction separately sets up, provides more process space, and the encapsulation operation of two chips does not influence each other, has improved the efficiency of encapsulation greatly, has solved among the prior art because of the encapsulation unit only is applicable to single core structure or multicore lamination structure and has leaded to the lower problem of encapsulation efficiency.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so that the scope of the present invention shall be determined by the scope of the appended claims.

Claims (10)

1. A dual-chip die frame for packaging a die of a dual-chip configuration, comprising:
the conveying line comprises a first line body and a second line body, and the first line body and the second line body are arranged in parallel;
the first frame comprises a first pin and a first chip seat; one end of the first pin is fixedly connected with the first line body, and the other end of the first pin is fixedly connected with the first chip base; the first chip seat is provided with a first mounting position;
a second frame including a second lead and a second die pad; one end of the second pin is fixedly connected with the second wire body, and the other end of the second pin is fixedly connected with the second chip base; two second mounting positions are arranged on the second chip seat; the second chip seat is positioned above the first chip seat, and a gap is arranged between the second chip seat and the first chip seat;
the double-chip is arranged in the gap, and one chip in one side of the double-chip corresponds to one second mounting position; the other side of the double-chip is positioned at the first mounting position; and the number of the first and second groups,
and the solder is positioned on two sides of the double-chip and used for connecting the double-chip with the first chip seat and the second chip seat.
2. The dual chip frame of claim 1, wherein the second chip carrier comprises two housing bodies, each housing body having one of the second mounting locations disposed thereon; each seat body comprises a second platform body, the second platform bodies are located on the second installation positions, and the two second platform bodies are respectively connected with the two chips of the double-chip in a one-to-one correspondence mode.
3. The dual-chip frame of claim 2, wherein the second leads comprise two lead bodies, each of the lead bodies being connected to one of the seats.
4. The dual-chip frame of claim 3, wherein the second frame further comprises a second connecting block, the lead body and the base are respectively connected to two ends of the second connecting block, the lead body and the base are disposed in a staggered manner, and the lead body is located under one side of the base.
5. The dual-chip frame of claim 4, wherein the first frame further comprises a first connection block, the first leads and the first chip pad are respectively connected to two ends of the first connection block, the first leads and the first chip pad are disposed in a staggered manner, and the first leads are located above the first chip pad.
6. The dual-chip frame of claim 5, wherein a distance between the lower surface of the first lead and the upper surface of the first chip pad is equal to a distance between the upper surface of the lead body and the lower surface of the pad body.
7. The dual chip frame of claim 2, wherein the base is configured as a rectangular parallelepiped and the second stage is configured as a trapezoidal stage.
8. The dual-chip frame of claim 2, wherein the first chip seat comprises a first platform thereon, the first platform is located at the first mounting position, and an area of a side of the first platform contacting the dual-chip is larger than an area of an area where two chips of the dual-chip are located.
9. The dual chip frame of claim 1, wherein a thickness of the first frame is equal to a thickness of the second frame.
10. The dual chip frame of claim 1, wherein the dual chip includes a positioning plate and two positioning grooves, the two positioning grooves are disposed in parallel on the positioning plate, and the two chips are disposed in the two positioning grooves respectively.
CN202220147514.XU 2022-01-19 2022-01-19 Double-chip frame Active CN216749882U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220147514.XU CN216749882U (en) 2022-01-19 2022-01-19 Double-chip frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220147514.XU CN216749882U (en) 2022-01-19 2022-01-19 Double-chip frame

Publications (1)

Publication Number Publication Date
CN216749882U true CN216749882U (en) 2022-06-14

Family

ID=81915230

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202220147514.XU Active CN216749882U (en) 2022-01-19 2022-01-19 Double-chip frame

Country Status (1)

Country Link
CN (1) CN216749882U (en)

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