CN216648296U - Composite electronic component - Google Patents
Composite electronic component Download PDFInfo
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- CN216648296U CN216648296U CN202123240732.2U CN202123240732U CN216648296U CN 216648296 U CN216648296 U CN 216648296U CN 202123240732 U CN202123240732 U CN 202123240732U CN 216648296 U CN216648296 U CN 216648296U
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- lead
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- electronic component
- composite electronic
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- 239000002131 composite material Substances 0.000 title claims description 41
- 238000003466 welding Methods 0.000 claims abstract description 13
- 239000011295 pitch Substances 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 17
- 230000010354 integration Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 150000001875 compounds Chemical class 0.000 abstract description 4
- 230000002349 favourable effect Effects 0.000 abstract description 4
- 238000005452 bending Methods 0.000 description 18
- 238000009434 installation Methods 0.000 description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 208000033999 Device damage Diseases 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- Thermistors And Varistors (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
The application discloses compound electronic component includes: a first chip (10), the first chip (10) having opposing first and second electrodes; the second chip (20) is provided with a third electrode and a fourth electrode which are opposite, and the fourth electrode and the second electrode are jointed and connected to form a common end; a first lead (30) connected to the first electrode; a second lead (40) connected to the third electrode; a third lead (50) connected to the common terminal; the first lead (30) and the second lead (40) comprise bent sections (100) and flat sections (200), the bent sections (100) are connected to the welding connection positions of the leads and the electrode surfaces, and the two flat sections (200) and the third lead (50) are parallel and coplanar. The method and the device can be suitable for automatic production lines and are favorable for improving the integration level of devices on the circuit board.
Description
Technical Field
The application belongs to the technical field of chip packaging, and particularly relates to a composite electronic component.
Background
At present, composite electronic components are widely applied to electric power instruments to protect the electric power instruments from being damaged. In order to facilitate production, most of the leads of the common composite electronic component are straight leads, and the tail end of each lead is irregularly distributed due to different lead leading-out positions. Due to the spatial distribution of the leads, the composite electronic component with the structure cannot be packaged by a braid, so that the composite electronic component cannot be suitable for automatic welding and has low production efficiency. In addition, when in use, the lead space distribution occupies a larger area of the PCB, which is not beneficial to the integration of the device. Therefore, it is urgent to design a composite electronic component which can save the area of the PCB and is suitable for automatic welding lines.
SUMMERY OF THE UTILITY MODEL
The application aims at providing a composite electronic component, the tail ends of leads of the composite electronic component are arranged in a line, the composite electronic component not only can be suitable for an automatic production line, but also can reduce the requirement on the installation area of a PCB.
The embodiment of the application provides a compound electronic component, includes:
a first chip having opposing first and second electrodes;
the second chip is provided with a third electrode and a fourth electrode which are opposite, and the fourth electrode and the second electrode are jointed and connected to form a common end;
a first lead connected to the first electrode;
a second lead connected to the third electrode;
a third lead connected to the common terminal;
the first lead and the second lead comprise bent sections and flat sections, the bent sections are connected to the welding connection positions of the leads and the surfaces of the electrodes, and the two flat sections and the third lead are parallel and coplanar.
Optionally, the third lead is interposed between the two straight sections.
Optionally, the third lead has a different distance from the two straight sections, and the first lead and the second lead can be identified according to the distance.
Optionally, the distance between the straight section of the second lead and the third lead is greater than the distance between the straight section of the first lead and the third lead, so that arc discharge and device damage caused by high voltage at two ends of the second chip can be avoided.
Optionally, the difference between the two pitches is greater than 0.5mm and less than 5 mm.
Optionally, the bending section and the corresponding straight section are arranged in a zigzag shape.
Optionally, the bending section includes a first bending section and a second bending section, one end of the first bending section is connected to the corresponding straight section, and the other end of the first bending section is connected to the second bending section.
Optionally, a coplanar plane of the two straight sections and the third lead is parallel to the common end.
Optionally, the first chip and the second chip are located within an encapsulation layer.
Optionally, the first chip is a thermistor chip, and the second chip is a varistor chip.
The technical scheme of the application has the following beneficial technical effects:
the compound electronic component of this application embodiment through bending partial lead wire, makes each lead wire end can be arranged in a word to can braid the packing to the lead wire end, carry out automated welding production, be favorable to improving production efficiency, reduction in production cost. In addition, because the tail ends of the leads are arranged in a line, the leads of the composite electronic element can be welded on a straight line during installation, so that the installation area on the circuit board can be reduced, the installation surface is regular, and the improvement of the integration level of devices on the circuit board is facilitated.
Drawings
FIG. 1 is a schematic structural diagram of a thermosensitive voltage-sensitive composite resistor in the related art;
FIG. 2 is a schematic diagram of a package of a thermal varistor in the related art;
FIG. 3 is a side view of FIG. 2;
fig. 4 is a schematic structural diagram of a composite electronic component in an embodiment of the present application;
fig. 5 is a schematic packaging diagram of a composite electronic component according to an embodiment of the present application;
FIG. 6 is a side view of FIG. 5;
fig. 7 is a schematic view of a braid package of a composite electronic component according to an embodiment of the present disclosure.
In the figure, 1, a thermistor; 2. a voltage dependent resistor; 10. a first chip; 11. a second electrode; 20. a second chip; 21. a third electrode; 30. a first lead; 40. a second lead; 50. a third lead; 60. an encapsulation layer; 70. a paper strap; 100. bending the section; 110. a first inflection segment; 120. a second turning section; 200. a straight section.
Detailed Description
In the related art, a thermal sensitive and voltage sensitive composite resistor, as shown in fig. 1-3, includes a thermal sensitive resistor 1 and a voltage sensitive resistor 2, wherein an electrode on one side of the thermal sensitive resistor 1 is connected with an electrode on one side of the voltage sensitive resistor 2 to form a common terminal, and the common terminal is led out through a lead; the other lead of the thermistor 1 and the other lead of the piezoresistor 2 are respectively and independently led out; the three leads are distributed in a delta shape.
To save cost and space, engineers design increasingly dense arrangements of components on Printed Circuit Boards (PCBs); electronic components with the same performance occupy a small area of the PCB and are more popular. The lead wires of the composite electronic component with the structure are distributed in space, and occupy a larger area on a circuit board in the installation process, so that the use requirement cannot be met.
In addition, with the rapid development of the automation technology level and the increase of labor cost, more and more enterprises adopt electronic components suitable for Surface Mount Technology (SMT) or automatic plug-in technology. The composite electronic component with the structure cannot be subjected to tape packaging due to the spatial distribution of the leads, so that the composite electronic component cannot be applied to automatic production.
Based on above-mentioned reason, this application embodiment provides a novel compound electronic component, through bending partial lead wire, makes each lead wire end can be arranged in a word to can carry out the braid packing to the lead wire end, carry out automated welding production, be favorable to improving production efficiency, reduction in production cost. In addition, because the tail ends of the leads are arranged in a line, the leads of the composite electronic element can be welded on a straight line during installation, so that the installation area on the circuit board can be reduced, the installation surface is regular, and the improvement of the integration level of devices on the circuit board is facilitated.
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to the accompanying drawings in combination with the detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present application. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present application.
In the drawings, a schematic diagram of a layer structure according to an embodiment of the application is shown. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
In the description of the present application, it is noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 4 to 6, an embodiment of the present application provides a composite electronic component, including:
a first chip 10, the first chip 10 having a first electrode (not shown) and a second electrode 11 opposite to each other;
a second chip 20, wherein the second chip 20 has a third electrode 21 and a fourth electrode (not shown in the figure) opposite to each other, and the fourth electrode is attached to the second electrode 11 to form a common terminal;
a first lead 30 connected to the first electrode;
a second lead 40 connected to the third electrode 21;
a third lead 50 connected to the common terminal;
the first lead 30 and the second lead 40 include a bent section 100 and a flat section 200, the bent section 100 is connected to a lead and electrode surface welding connection, and the two flat sections 200 are parallel and coplanar with the third lead 50.
Specifically, the positions of the first lead 30 and the second lead 40 of the composite electronic element, which are connected with the electrodes, are bent, after welding is completed, the tail ends of the first lead 30, the second lead 40 and the third lead 50 can be arranged in a line, and the plane where the three leads are arranged is parallel to the plane where the public end is arranged, so that when the composite electronic element is installed, the leads of the composite electronic element can be welded on a straight line, the installation area on a circuit board can be reduced, the installation surface is regular, and the improvement of the integration level of devices on the circuit board is facilitated. In addition, because the tail ends of the leads of the product are arranged in a line, the leads can be braided and packaged before being welded and then welded, so that the method can be used for automatic welding production, is favorable for improving the production efficiency and reducing the production cost.
In some embodiments, the composite electronic component may further be formed by bending the first lead 30 and the third lead 50, or bending the second lead 40 and the third lead 50.
In some embodiments, the third lead 50 is interposed between two of the straight segments 200.
In some embodiments, the third lead 50 is spaced differently from the two straight sections 200. For example, the distance between the straight portion 200 of the second lead 40 and the third lead 50 is greater than the distance between the straight portion 200 of the first lead 30 and the third lead 50, or the distance between the straight portion 200 of the second lead 40 and the third lead 50 is less than the distance between the straight portion 200 of the first lead 30 and the third lead 50. It should be noted that the leads may not be accurately identified due to the need to package the device at a later time, thereby causing a problem of incorrect lead mounting positions, and the two different pitches may help to distinguish the first leads 30 from the second leads 40. For example, the distance between the straight portion 200 of the second lead 40 and the third lead 50 is greater than the distance between the straight portion 200 of the first lead 30 and the third lead 50, so that the lead farther from the third lead 50 is the second lead 40, and the lead closer to the third lead 50 is the first lead 30.
In some embodiments, the flat portion 200 of the second lead 40 is spaced from the third lead 50 by a distance greater than the distance between the flat portion 200 of the first lead 30 and the third lead 50. This is because the resistance of the varistor changes with the voltage within a certain current-voltage range, and if a high voltage appears at the two ends of the second chip 10, arcing may occur and the device may be damaged, so that the distance between the straight section 200 of the second lead 40 and the third lead 50 is relatively large.
In some embodiments, the difference between the two pitches should be greater than 0.5mm and less than 5 mm. For example, the difference between the two spacings may be 1mm, 2mm, 3mm, 4mm or 5 mm. It should be noted that the difference between the two pitches is mainly for distinguishing the first wire 30 from the second wire 40, and therefore, the difference should be of a size that satisfies the minimum size requirement that can be recognized by a human or a machine.
In some embodiments, the first chip 10 and the second chip 20 are both in a circular sheet shape, the first electrode and the second electrode 11 are disposed at two axial ends of the first chip 10, and the third electrode 21 and the fourth electrode are disposed at two axial ends of the second chip 20.
In some embodiments, the radius of the second chip 20 is smaller than the radius of the first chip 10, and the axial center of the first chip 10 is not coincident with the axial center of the second chip 20. Illustratively, the radius of the first chip 10 is smaller than that of the second chip 20, the difference between the radii of the two is greater than 0.5mm and smaller than 7.5mm, and the two are eccentrically connected by soldering with solder paste or solder. This is because the lead connected to the common terminal is actually connected to the second electrode 11 of the second chip 20, and if the second chip 20 and the first chip 10 are coaxially disposed, the area of the second electrode 11 that can be connected to the lead is greatly reduced. For example, the radius of the second chip 20 is 6mm, the radius of the first chip 10 is 3.5mm, and after the second chip 20 is coaxially connected with the first chip 10, the width of the second electrode 11, which is only 1.25mm on the edge, is available for connecting leads, whereas when the second chip 20 is eccentrically connected with the first chip 10, the width of the second electrode 11, which is available for connecting leads, can be up to 2.5mm at most.
In some embodiments, the third lead 50 is connected to a side of the fourth electrode offset from the axis of the first chip 10. This is because the second electrode 11 has the largest width on the side deviated from the axis of the first chip 10, and the bonding of the wire thereto can ensure effective connection of the wire to the electrode.
In some embodiments, the bent section 100 and the corresponding straight section 200 are arranged in a "Z" shape.
In some embodiments, the bending section 100 includes a first bending section 110 and a second bending section 120, one end of the first bending section 110 is connected to the corresponding straight section 200, and the other end is connected to the second bending section 120.
In some embodiments, the coplanar planes of two of the straight sections 200 and the third lead 50 are parallel to the common end.
In some embodiments, the first chip 10 and the second chip 20 are located within an encapsulation layer 60. The encapsulating layer is formed by coating or injection molding of an insulating material, and the insulating material can be one or more of organic silicon resin, phenolic resin and epoxy resin.
In some embodiments, the first lead 30, the second lead 40, and the third lead 50 are round leads or flat leads, and the leads may be tinned copper clad steel wires, tinned copper wires, tinned iron sheets, tinned copper sheets, or the like.
In some embodiments, the first chip 10 is a thermistor chip and the second chip 20 is a varistor chip. In other embodiments, the first chip 10 and the second chip 20 may also be other composite chip combinations.
In order to further explain the technical scheme of the embodiment of the application, a phi 12 × 2.0mm varistor chip and a phi 7 × 5.0 thermistor chip are selected, and the manufacturing process of the composite electronic component is specifically explained.
Step one
The method is characterized in that tinned copper clad steel wires are used as leads of a composite electronic component, the leads are cut into a set length and straightened, every three leads form a group, the leads are arranged at a set interval and packaged in a braid packaging mode, as shown in fig. 7, in each group of leads, a third lead 50 is arranged between a first lead 30 and a second lead 40, the foot distance between the first lead 30 and the third lead 50 is 5mm, the foot distance between the second lead 40 and the third lead 50 is 3mm, the width of a paper tape 70 for packaging is 18mm, and the center hole distance is 15 mm.
Step two
And respectively carrying out Z-shaped bending treatment on the first lead 30 and the second lead 40 in each group of leads to obtain a first piece.
Step three
And coating a proper amount of tin paste on the position of one electrode surface of the piezoresistor chip deviated from the center, placing the thermistor chip on the electrode surface of the piezoresistor chip coated with the tin paste, and welding the piezoresistor chip and the electrode surface into a whole through reflow soldering to obtain a second part.
Step four
And (4) automatically taking and welding the first piece and the second piece by using automatic welding production equipment.
Step five
After the bonding, the organic silicon resin is coated and cured, and the varistor chip and the thermistor chip are encapsulated in the encapsulation layer, so that the composite electronic component described in the foregoing embodiment can be obtained.
The composite electronic component prepared by the method can be packed and transported together with the paper tape, which is beneficial to improving the packing efficiency and facilitating transportation.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A composite electronic component, comprising:
a first chip (10), the first chip (10) having opposing first and second electrodes (11);
the second chip (20) is provided with a third electrode (21) and a fourth electrode which are opposite, and the fourth electrode and the second electrode (11) are attached and connected to form a common end;
a first lead (30) connected to the first electrode;
a second lead (40) connected to the third electrode (21);
a third lead (50) connected to the common terminal;
the first lead (30) and the second lead (40) comprise bent sections (100) and flat sections (200), the bent sections (100) are connected to the welding connection positions of the leads and the electrode surfaces, and the two flat sections (200) and the third lead (50) are parallel and coplanar.
2. Composite electronic component according to claim 1, characterised in that said third lead (50) is interposed between two of said straight sections (200).
3. Composite electronic component according to claim 2, characterised in that the third lead (50) has a different pitch from the two straight sections (200).
4. A composite electronic component according to claim 3, characterized in that the straight section (200) of the second lead (40) is spaced from the third lead (50) by a distance greater than the distance between the straight section (200) of the first lead (30) and the third lead (50).
5. Composite electronic component according to claim 4, characterized in that the difference between the two pitches is greater than 0.5mm and less than 5 mm.
6. Composite electronic component according to claim 1, characterised in that said bent section (100) and the corresponding straight section (200) are connected in a "Z" configuration.
7. Composite electronic component according to claim 6, wherein said bent section (100) comprises a first bent section (110) and a second bent section (120), one end of said first bent section (110) being connected to the corresponding straight section (200) and the other end being connected to said second bent section (120).
8. A composite electronic component according to claim 1, wherein coplanar planes of the two straight sections (200) and the third lead (50) are parallel to the common end.
9. Composite electronic component according to claim 1, characterized in that the first chip (10) and the second chip (20) are located within an encapsulation layer (60).
10. Composite electronic component according to claim 1, characterised in that the first chip (10) is a thermistor chip and the second chip (20) is a varistor chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN202123240732.2U CN216648296U (en) | 2021-12-22 | 2021-12-22 | Composite electronic component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202123240732.2U CN216648296U (en) | 2021-12-22 | 2021-12-22 | Composite electronic component |
Publications (1)
Publication Number | Publication Date |
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CN216648296U true CN216648296U (en) | 2022-05-31 |
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Application Number | Title | Priority Date | Filing Date |
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CN202123240732.2U Active CN216648296U (en) | 2021-12-22 | 2021-12-22 | Composite electronic component |
Country Status (1)
Country | Link |
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CN (1) | CN216648296U (en) |
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2021
- 2021-12-22 CN CN202123240732.2U patent/CN216648296U/en active Active
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GR01 | Patent grant | ||
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PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Composite electronic components Granted publication date: 20220531 Pledgee: Bank of China Limited Xiamen hi tech Park sub branch Pledgor: XIAMEN SANBAO YINGKE ELECTRONICS CO.,LTD. Registration number: Y2024980027701 |
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