CN216623772U

CN216623772U - High-temperature test system for memory chip

Info

Publication number: CN216623772U
Application number: CN202122941192.4U
Authority: CN
Inventors: 张志强; 杨密凯; 李斌; 凡涛; 冯修圣
Original assignee: Shenzhen Hongwang Microelectronics Co ltd
Current assignee: Shenzhen Hongwang Microelectronics Co ltd
Priority date: 2021-11-29
Filing date: 2021-11-29
Publication date: 2022-05-27
Anticipated expiration: 2031-11-29

Abstract

The utility model discloses a high-temperature test system of a memory chip, which comprises a thermostat, a test component and a test host, wherein the test component comprises a test mainboard and a memory chip connecting plate, the test mainboard is electrically connected with the memory chip connecting plate and carries out data communication, the thermostat comprises a first data interface and a second data interface, the first data interface is arranged outside the thermostat, the second data interface is arranged inside the thermostat, and the first data interface is electrically connected with the second data interface, the improvement of the utility model is that the thermostat is fixedly provided with two data interfaces which are connected through a circuit embedded in the thermostat, the memory chip connecting plate is connected with the test mainboard through the two data interfaces and carries out data communication, the test data communication in the technical scheme is stable and can not receive interference, the technical scheme has the advantages of convenient operation, neat test environment and long service life.

Description

High-temperature test system for memory chip

Technical Field

The utility model relates to the technical field of high-temperature testing of memory chips, in particular to a high-temperature testing system of a memory chip.

Background

An IC chip (Integrated Circuit) is a chip formed by integrating a large number of microelectronic devices. The memory chip is an IC chip (such as a memory chip, also called "memory particle") having a memory function, the memory chip is the most core component in the memory device, and the quality of the memory chip can be directly related to the performance of the memory device. Therefore, the memory chip is subjected to a strict test before shipping, wherein the high temperature test is an important link of the memory chip test.

In the prior art, the high-temperature test of the memory chip is to place the memory chip and a test mainboard into a thermostat together for testing, and the test method is simple and quick, but has certain disadvantages. The test mainboard is repeatedly used in high-temperature test activities, the stability and the electrical parameters of the test mainboard are inevitably changed, and the failure rate is increased due to the change. And the failure of the test mainboard can be mistaken as a problem of the memory chip. Based on this prior art, a testing method for separating the testing motherboard from the memory chip is proposed, for example, in patent CN 214428332U.

In the above patent, a chip bonding board (on which a memory chip is disposed) is disposed separately from a test main board, the chip bonding board is placed in an oven, the test main board is outside the oven, and the chip bonding board and the test main board are connected by a data line and perform data communication. The technical solution described in this patent has some drawbacks: 1. the wire sheath of the data wire is easy to be damaged at high temperature; 2. the transmission signal of the data line is unstable in a high-temperature environment, is easily interfered and has influence on the test rate; 3. the wire passing hole of the thermostat influences the temperature field change of the thermostat and influences the test; 4. the data line is exposed to the outside, and the test environment is influenced.

SUMMERY OF THE UTILITY MODEL

Aiming at the defects of the prior art, the utility model discloses a high-temperature test system for a memory chip, the whole idea of the technical scheme is to separate the memory chip from a test mainboard, but the improvement of the technical scheme is as follows: two data interfaces are fixedly arranged on the thermostat, one data interface is fixedly arranged inside the thermostat, the other data interface is fixedly arranged outside the thermostat, the two data interfaces are connected through a circuit embedded into the thermostat, and the storage chip and the test mainboard are connected through the two data interfaces and carry out data communication. Data communication between memory chip and the test mainboard can not receive the interference among this technical scheme, and the connection convenient operation and test environment between memory chip and the test mainboard are very clean and tidy, and life is also longer than the form of data line.

The technical scheme is as follows:

the high-temperature testing system for the storage chip comprises a thermostat, a testing assembly and a testing host, wherein the testing assembly comprises a testing mainboard and a storage chip connecting plate, and the testing mainboard is electrically connected with the storage chip connecting plate and carries out data communication.

Furthermore, the incubator comprises a first data interface and a second data interface, the first data interface is arranged outside the incubator, the second data interface is arranged inside the incubator, and the first data interface is electrically connected with the second data interface.

Furthermore, the test host is electrically connected with the test mainboard and performs data communication.

Furthermore, the incubator also comprises a circuit module, the circuit module is embedded into the wall of the incubator, and the first data interface and the second data interface are electrically connected together through the circuit module.

Furthermore, the circuit module is a PCB board provided with a conducting circuit.

Furthermore, the test mainboard is connected with the first data interface in a pluggable manner; the storage chip connecting plate is placed in the chip high-temperature testing thermostat and connected with the second data interface in a pluggable mode.

Furthermore, the first data interface is a PCIe interface or a SATA interface; the second data interface is a PCIe interface or a SATA interface.

Furthermore, the test host is a PC computer.

The utility model relates to a high-temperature test system for a storage chip, which has the improvement that two data interfaces are fixedly arranged on a constant temperature box, one data interface is fixedly arranged inside the constant temperature box, the other data interface is fixedly arranged outside the constant temperature box, the two data interfaces are connected through a circuit embedded in the constant temperature box, a storage chip connecting plate is connected with a test mainboard through the two data interfaces and carries out data communication, the data communication between the storage chip connecting plate and the test mainboard in the technical scheme is stable and cannot be interfered, the connection operation between the storage chip connecting plate and the test mainboard is convenient, the test environment is neat, and the service life is long.

Drawings

FIG. 1 is a schematic structural diagram of a high temperature testing system for a memory chip according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

For the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; certain well-known structures in the drawings and omissions of their description may be apparent to those skilled in the art. The same or similar reference numerals correspond to the same or similar components.

The technical scheme is an improvement of the prior art, and can solve the common problems faced by the high-temperature test of the memory chip and improve the test efficiency of the memory chip.

This technical scheme is put storage chip and is carried out high temperature test in the thermostated container, and the test mainboard is put outside the thermostated container, and storage chip is connected and data communication through the circuit that sets up on the thermostated container with the test mainboard. Particularly, two data interfaces are fixedly arranged on the thermostat of the technical scheme, one data interface is fixedly arranged inside the thermostat, one data interface is fixedly arranged outside the thermostat, the two data interfaces are connected through a circuit embedded into the thermostat, the storage chip and the test mainboard are connected through the two data interfaces and carry out data communication, and the data communication between the storage chip and the test mainboard in the technical scheme is stable and can not be interfered.

The technical problems mainly solved by the technical scheme are as follows:

1. the test mainboard is arranged outside the thermostat in the test activity, the working parameters of the test mainboard cannot be damaged in the high-temperature environment, the fault rate of the test mainboard is reduced, and the service life of the test mainboard is prolonged.

2. The problems that in a similar scheme that the memory chip and the test mainboard are separately arranged, the line skin of the data line is easy to damage, the transmission signal of the data line is unstable, the interference is easy to occur and the test speed is not ideal in a high-temperature test when the memory chip and the test mainboard are connected in a data line mode are solved.

3. The problem of the line hole influence thermostated container temperature field change of crossing of thermostated container to produce the influence to the high temperature test is solved.

4. The problem of memory chip and test mainboard separation set up in the similar scheme, the data line is disorderly and has nothing to do all can, influences test environment is solved.

The embodiment of the technical scheme is as follows:

as shown in fig. 1, a high temperature testing system 1 for a memory chip in the present embodiment includes an oven 10, a testing component and a testing host 30, wherein the testing component includes a testing motherboard 21 and a memory chip connecting board 22, and the testing motherboard 21 is electrically connected to the memory chip connecting board 22 for data communication.

The memory chip connecting board 22 in this embodiment is designed to separate the memory chip from the test main board 21. During testing, the memory chip is fixed on the memory chip connecting plate 22 and then placed into the thermostat together for high-temperature testing, and data communication between the memory chip and the test mainboard 21 is realized through connection between the memory chip connecting plate 22 and the test mainboard 21. It should be noted that the memory chip is fixed on the memory chip connecting plate 22 by soldering, or fixed on the memory chip connecting plate 22 by using a chip fixture, such as a chip holder, etc., in this embodiment, the memory chip is preferably fixed by soldering.

In this embodiment, as shown in fig. 1, the oven 10 includes a first data interface 11 and a second data interface 12, the first data interface 11 is disposed outside the oven 10, the second data interface 12 is disposed inside the oven 10, and the first data interface 11 is electrically connected to the second data interface 12.

In this embodiment, the first data interface 11 is preferably a PCIe interface or an SATA interface; the second data interface 12 is preferably a PCIe interface or a SATA interface, and it should be noted that the first data interface 11 and the second data interface 12 are not limited to the PCIe interface or the SATA interface, and data interfaces that can achieve similar technical effects in the prior art may be applied to this technical solution, and are not described in detail in this embodiment.

In a more preferred technical solution of this embodiment, as shown in fig. 1, the oven 10 further includes a circuit module 13, the circuit module 13 is embedded in a wall of the oven 10, and the first data interface 11 and the second data interface 12 are electrically connected together through the circuit module 13.

It should be noted that in the present embodiment, the first data interface 11 and the second data interface 12 may be embedded in the wall of the oven 10, for example, the first data interface 11 is embedded in the outer wall of the oven 10, and the second data interface 12 is embedded in the bottom surface of the inside of the oven 10. The first data interface 11 and the second data interface 12 may be fixed to the oven 10 in other ways, for example, the first data interface 11 may be an interface module protruding from an outer wall of the oven 10, the second data interface 12 may be an interface module protruding from an inner bottom surface of the oven 10, and the like, and the present embodiment is not limited to the above two fixing ways.

The circuit module 13 is embedded in the bottom surface of the incubator 10 in a concealed manner, and two ends of the circuit module 13 are respectively connected with the first data interface 11 and the second data interface 12; the bottom surface of the oven 10 may also be provided with a groove, the circuit module 13 is accommodated in the groove, and two ends of the circuit module 13 are respectively connected to the first data interface 11 and the second data interface 12.

The circuit module 13 in this embodiment is preferably a PCB board provided with conductive traces. The PCB is high temperature resistant, is not easily influenced by external environment, and has stable parameters, but alternative schemes in other prior art do not exceed the recording range of the technical scheme, and are not described again here.

In this embodiment, the test motherboard 21 is connected to the first data interface 11 in a pluggable manner; the memory chip connecting board 22 is placed in the oven 10 and is connected to the second data interface 12 in a pluggable manner.

In this embodiment, it should be noted that the test motherboard 21 is provided with a data interface matching with the type of the first data interface 11, and the circuit connection can be completed only by plugging the test motherboard into the first data interface 11, which is very convenient.

The memory chip connecting plate 22 is provided with a data interface matched with the type of the second data interface 12, and the circuit connection can be completed only by correspondingly inserting the data interfaces together during testing. It should be noted that, when the memory chip connecting board 22 is placed in the incubator 10, the data interface of the second data interface 12 can be directly inserted into the second data interface 12, and at this time, the memory chip connecting board 22 and the second data interface 12 not only complete the circuit connection, but also the second data interface 12 plays a role in positioning and fixing the memory chip connecting board 22.

In a preferred embodiment of the present invention, the number of the second data interfaces 12 may be multiple, so that the present embodiment may measure multiple memory chip connection boards 22 simultaneously.

In this embodiment, the test host 30 is a PC computer, and the test host 30 is electrically connected to the test motherboard 21 for data communication.

It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A high-temperature test system for a storage chip comprises a thermostat, a test assembly and a test host, and is characterized in that the test assembly comprises a test mainboard and a storage chip connecting plate, and the test mainboard is electrically connected with the storage chip connecting plate and carries out data communication;

the incubator comprises a first data interface and a second data interface, the first data interface is arranged outside the incubator, the second data interface is arranged inside the incubator, and the first data interface is electrically connected with the second data interface;

the test host is electrically connected with the test mainboard and performs data communication.

2. The system for testing a memory chip at a high temperature as claimed in claim 1, wherein the oven further comprises a circuit module embedded in the wall of the oven, the first data interface and the second data interface being electrically connected together through the circuit module.

3. The high temperature testing system for memory chips as claimed in claim 2, wherein the circuit module is a PCB board provided with conductive traces.

4. The high temperature test system for memory chips of claim 2, wherein the test motherboard is pluggable to the first data interface; the storage chip connecting plate is placed in the chip high-temperature testing thermostat and connected with the second data interface in a pluggable mode.

5. The memory chip high temperature test system of claim 1,

the first data interface is a PCIe interface or a SATA interface;

the second data interface is a PCIe interface or a SATA interface.

6. The system for testing the memory chip at high temperature as claimed in claim 1, wherein the testing host is a PC computer.