CN216526801U - MCU of built-in double-circuit operational amplifier - Google Patents
MCU of built-in double-circuit operational amplifier Download PDFInfo
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- CN216526801U CN216526801U CN202122711740.4U CN202122711740U CN216526801U CN 216526801 U CN216526801 U CN 216526801U CN 202122711740 U CN202122711740 U CN 202122711740U CN 216526801 U CN216526801 U CN 216526801U
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Abstract
The utility model discloses an MCU with a built-in two-way operational amplifier, which comprises the following components: the inverting input of the first amplifier OPA0 is connected to a first data selector MUX 1; the non-inverting input terminal of the first amplifier OPA0 is connected to the second data selector MUX2 terminal; the inverting input of the second amplifier OPA1 is connected to a third data selector MUX 3; the non-inverting input of the second amplifier OPA1 is connected to a fourth data selector MUX 4; the output A0X of the first amplifier OPA0 is also connected to a third data selector MUX3 and a fourth data selector MUX 4. The utility model can be used for the analog signal processing specific to the user by arranging the double-path amplifier in the MCU; by setting the corresponding control register. Operational amplifiers can be enabled or disabled or implemented as followers, non-inverting amplifiers, inverting amplifiers or various filters, etc.; the flexibility of use is enhanced, and the method is suitable for various wide applications.
Description
Technical Field
The utility model belongs to the technical field of integrated circuits, and particularly relates to an MCU (microprogrammed control unit) with a built-in two-way operational amplifier.
Background
Operational amplifiers (Operational amplifiers) are widely used in integrated circuits, and Stability (Stability) is one of the important indicators of Operational amplifiers. For the operational amplifier adopting the fully differential input stage, the fully differential input stage comprises a pair of NMOS transistors and a pair of PMOS transistors, and the fully differential input stage can adapt to the input states of different input voltages.
As is known, the currents of the PMOS transistor and the NMOS transistor during conduction are different, and in order to adapt to the conduction operation of the NMOS transistor pair and the PMOS transistor pair in the fully differential input stage, the operating current of the whole operational amplifier may be based on the operating current of the NMOS transistor pair, but at this time, the PMOS transistor pair may cause the power consumption of the whole operational amplifier to be increased during operation, and may cause the operational amplifier to be unstable during operation. At present, the current of the NMOS transistor pair and the PMOS transistor pair can be adapted in other ways, and the operational amplifier has poor working stability, and the production and use costs of the operational amplifier can be increased, which is difficult to meet the requirements of modern production and life on the operational amplifier.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide an MCU with a built-in two-way operational amplifier, which can be used for processing analog signals specific to a user by arranging the two-way operational amplifier in the MCU; by setting the corresponding control register. Operational amplifiers can be enabled or disabled or implemented as followers, non-inverting amplifiers, inverting amplifiers or various filters, etc.; the flexibility of use is enhanced, and the method is suitable for various wide applications; the stability and the reliability of the whole operational amplifier are guaranteed, and meanwhile, the power consumption of the whole operational amplifier is not obviously increased, and the method is safe and reliable.
In order to solve the technical problems, the utility model is realized by the following technical scheme:
the utility model relates to an MCU with a built-in two-way operational amplifier, which comprises a first amplifier OPA0 and a second amplifier OPA 1; an inverting input of the first amplifier OPA0 is connected to an output of a first data selector MUX 1; the non-inverting input of the first amplifier OPA0 is connected to the output of the second data selector MUX 2; an inverting input of the second amplifier OPA1 is connected to an output of a third data selector MUX 3; the non-inverting input of the second amplifier OPA1 is connected to the output of a fourth data selector MUX 4; the output A0X of the first amplifier OPA0 is also coupled to inputs of a third data selector MUX3 and a fourth data selector MUX 4.
Further, the output terminal of the first data selector MUX1 is connected in series with a resistor R1, an adjustable resistor R2 and a switch A0SW2 to the output terminal of the first amplifier OPA 0;
the output of the first data selector MUX1 is connected in series with a switch A0SW0 and a switch A0SW1 to the output of the first amplifier OPA 0;
the middle connection point of the resistor R1 and the adjustable resistor R2 is connected with the middle connection point of the switch A0SW0 and the switch A0SW 1;
the inverting input of the first amplifier OPA0 is connected to the middle junction of the resistor R1 and the adjustable resistor R2.
Further, the output end of the third data selector MUX3 is connected in series with a resistor R3, an adjustable resistor R4 and a switch A1SW2 to the output end of the second amplifier OPA 1;
the output terminal of the third data selector MUX3 is connected in series with a switch A1SW0 and a switch A1SW1 to the output terminal of the second amplifier OPA 1;
the middle connection point of the resistor R3 and the adjustable resistor R4 is connected with the middle connection point of the switch A1SW0 and the switch A1SW 1;
the inverting input of the second amplifier OPA1 is connected to the middle junction of the resistor R3 and the adjustable resistor R4.
Further, the input terminals of the first data selector MUX1, the second data selector MUX2, the third data selector MUX3 and the fourth data selector MUX4 are all connected to a voltage source 0.5VDD, the ground terminal GND and the reference voltage source VREFH.
The utility model has the following beneficial effects:
the utility model can be used for the analog signal processing specific to the user by arranging the double-path amplifier in the MCU; by setting the corresponding control register. Operational amplifiers can be enabled or disabled or implemented as followers, non-inverting amplifiers, inverting amplifiers or various filters, etc.; the flexibility of use is enhanced, and the method is suitable for various wide applications; the stability and the reliability of the whole operational amplifier are guaranteed, and meanwhile, the power consumption of the whole operational amplifier is not obviously increased, and the method is safe and reliable.
Of course, it is not necessary for any product in which the utility model is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic block diagram of an MCU with a built-in two-way operational amplifier.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention is an MCU with a built-in dual-channel operational amplifier, including a first amplifier OPA0 and a second amplifier OPA 1;
the inverting input of the first amplifier OPA0 is connected to the output of the first data selector MUX 1; the non-inverting input of the first amplifier OPA0 is connected to the output of the second data selector MUX 2;
the output end of the first data selector MUX1 is connected in series with a resistor R1, an adjustable resistor R2 and a switch A0SW2 to the output end of the first amplifier OPA 0; the output of the first data selector MUX1 is connected in series with a switch A0SW0 and a switch A0SW1 to the output of the first amplifier OPA 0; the middle connection point of the resistor R1 and the adjustable resistor R2 is connected with the middle connection point of the switch A0SW0 and the switch A0SW 1; the inverting input end of the first amplifier OPA0 is connected to the middle connection point of the resistor R1 and the adjustable resistor R2;
the inverting input of the second amplifier OPA1 is connected to the output of the third data selector MUX 3; the non-inverting input of the second amplifier OPA1 is connected to the output of the fourth data selector MUX 4;
the output end of the third data selector MUX3 is connected in series with a resistor R3, an adjustable resistor R4 and a switch A1SW2 to the output end of the second amplifier OPA 1; the output of the third data selector MUX3 is connected in series with a switch A1SW0 and a switch A1SW1 to the output of the second amplifier OPA 1; the middle connection point of the resistor R3 and the adjustable resistor R4 is connected with the middle connection point of the switch A1SW0 and the switch A1SW 1; the inverting input end of the second amplifier OPA1 is connected to the middle connection point of the resistor R3 and the adjustable resistor R4;
the output A0X of the first amplifier OPA0 is also connected to inputs of a third data selector MUX3 and a fourth data selector MUX 4;
the input terminals of the first data selector MUX1, the second data selector MUX2, the third data selector MUX3 and the fourth data selector MUX4 are connected to a voltage source 0.5VDD, the ground terminal GND and the reference voltage source VREFH.
The first embodiment is as follows: the embodiment is a working principle of an MCU with a built-in two-way operational amplifier: the MCU of the application is internally provided with two OPA channels, each channel is provided with two input ends A0N serving as inverting input ends, an AOP serving as a non-inverting input end and an output end A0X, and the two-channel operational amplifier comprises a fully differential input stage circuit, a first current source circuit in adaptive connection with a PMOS (P-channel metal oxide semiconductor) transistor pair in the fully differential input stage circuit and a second current source circuit in adaptive connection with an NMOS (N-channel metal oxide semiconductor) transistor pair in the fully differential input stage circuit; the transmission connection circuit is connected with the compensation circuit, and the compensation circuit is connected with the amplification output stage circuit;
specifically, the two-way operational amplifier comprises a pair of NMOS transistors and a pair of PMOS transistors, wherein the pair of NMOS transistors form an NMOS transistor pair, and the pair of PMOS transistors form a PMOS transistor pair. The conduction voltage range of the PMOS tube is different from that of the NMOS tube, and when the PMOS tube is conducted, the current flowing through the PMOS tube is smaller than that when the NMOS tube is conducted. When the PMOS transistor pair in the fully differential input stage circuit is in a conducting state, the current transmission control circuit is in a non-working state, namely the whole operational amplifier is in a lower current working state; and only when the NMOS transistor pair in the fully-differential input stage circuit is in a conducting state, the current transmission control circuit is in a working state, and the current transmission control circuit can increase the current loaded to the NMOS transistor pair in the fully-differential input stage circuit by the second current source circuit so as to match the working current requirement of the NMOS transistor pair. When the PMOS transistor pair works, the working current of the whole operational amplifier is smaller than that of the NMOS transistor pair, so that the stability and the reliability of the whole operational amplifier are ensured, the power consumption of the whole operational amplifier is not obviously increased, and the operational amplifier is safe and reliable.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the utility model disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model. The utility model is limited only by the claims and their full scope and equivalents.
Claims (4)
1. An MCU with a built-in two-way operational amplifier is characterized by comprising a first amplifier OPA0 and a second amplifier OPA 1;
an inverting input of the first amplifier OPA0 is connected to an output of a first data selector MUX 1; the non-inverting input of the first amplifier OPA0 is connected to the output of the second data selector MUX 2;
an inverting input of the second amplifier OPA1 is connected to an output of a third data selector MUX 3; the non-inverting input of the second amplifier OPA1 is connected to the output of a fourth data selector MUX 4;
the output A0X of the first amplifier OPA0 is also coupled to inputs of a third data selector MUX3 and a fourth data selector MUX 4.
2. The MCU of claim 1, wherein the output terminal of the first data selector MUX1 is connected in series with a resistor R1, an adjustable resistor R2 and a switch A0SW2 to the output terminal of the first amplifier OPA 0;
the output of the first data selector MUX1 is connected in series with a switch A0SW0 and a switch A0SW1 to the output of the first amplifier OPA 0;
the middle connection point of the resistor R1 and the adjustable resistor R2 is connected with the middle connection point of the switch A0SW0 and the switch A0SW 1;
the inverting input of the first amplifier OPA0 is connected to the middle junction of the resistor R1 and the adjustable resistor R2.
3. The MCU of claim 1, wherein the output terminal of the third data selector MUX3 is connected in series with a resistor R3, an adjustable resistor R4 and a switch A1SW2 to the output terminal of the second amplifier OPA 1;
the output terminal of the third data selector MUX3 is connected in series with a switch A1SW0 and a switch A1SW1 to the output terminal of the second amplifier OPA 1;
the middle connection point of the resistor R3 and the adjustable resistor R4 is connected with the middle connection point of the switch A1SW0 and the switch A1SW 1;
the inverting input of the second amplifier OPA1 is connected to the middle junction of the resistor R3 and the adjustable resistor R4.
4. The MCU of claim 1, wherein the input terminals of the first data selector MUX1, the second data selector MUX2, the third data selector MUX3 and the fourth data selector MUX4 are connected to a voltage source 0.5VDD, ground GND and reference voltage VREFH.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122711740.4U CN216526801U (en) | 2021-11-08 | 2021-11-08 | MCU of built-in double-circuit operational amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122711740.4U CN216526801U (en) | 2021-11-08 | 2021-11-08 | MCU of built-in double-circuit operational amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216526801U true CN216526801U (en) | 2022-05-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122711740.4U Active CN216526801U (en) | 2021-11-08 | 2021-11-08 | MCU of built-in double-circuit operational amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216526801U (en) |
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2021
- 2021-11-08 CN CN202122711740.4U patent/CN216526801U/en active Active
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