CN216488097U

CN216488097U - Avalanche photoelectric detector

Info

Publication number: CN216488097U
Application number: CN202122405062.9U
Authority: CN
Inventors: 杨志茂; 王斌
Original assignee: Beijing Yingfurui Semiconductor Technology Co ltd
Current assignee: Beijing Yingfurui Semiconductor Technology Co ltd
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2022-05-10
Anticipated expiration: 2031-09-30

Abstract

The utility model discloses an avalanche photodetector which comprises a back electrode, an n-type InP substrate, an n-type InP buffer layer and In which are arranged from bottom to top In sequence_0.53Ga_0.47As absorption layer and In_xGa_1‑ _xAs_yP_1‑yA bandwidth gradient layer, an n-type InP charge control layer and an intrinsic InP multiplication layer arranged on the intrinsic InP multiplication layerThe solar photovoltaic component is provided with a p-type InP central collector region, a p-type InP electric field protection ring and an InP isolation layer, wherein the electric field protection ring surrounds the periphery of the central collector region, and the InP isolation layer is filled in a spacing region between the electric field protection ring and the central collector region and a region on the periphery of the electric field protection ring; an optical antireflection film with a metal contact window is arranged on the central collector region, the electric field protection ring and the InP isolation layer, an upper electrode with an optical incidence window is arranged on the optical antireflection film, and the upper electrode is in contact with the central collector region through the metal contact window on the optical antireflection film. The utility model can improve the response speed of the detector, reduce the probability of the edge of the detector being broken down and reduce the tunneling dark current of the edge.

Description

Avalanche photoelectric detector

Technical Field

The utility model belongs to the technical field of photoelectric detectors, and particularly relates to an avalanche photoelectric detector.

Background

The working principle of the avalanche photodetector is that under a high reverse bias electric field, photons are incident to an i region to enable electrons to jump from a valence band to a conduction band to form an electron-hole pair, and the electron-hole pair is accelerated under the action of a strong electric field and collides with other atoms to generate additional electron-hole pairs and continuously generate the electrons and the hole pairs. Because fewer photons and even single photon incidence can trigger the avalanche multiplication process to cause the change of current macroscopically, the avalanche photodetector has extremely high sensitivity and detection efficiency and has very high application prospect in the field of weak light detection and even single photon detection. Compared with the traditional silicon-based photoelectric detector, the avalanche photoelectric detector based on the III-V group compound semiconductor has higher sensitivity, can perform near-infrared weak light three-dimensional imaging with the wavelength of 1um or more, and has important application in the fields of biochemistry, quantum communication, laser radar and the like.

Most of the existing avalanche photodetectors are based on a separate absorption layer and multiplication layer Structure (SCAM), in which a narrow bandwidth ingaas (p) material is used as the light absorption layer and a high bandwidth InP or InAlAs material is used as the multiplication layer. The structure can effectively improve the breakdown voltage of the detector and reduce tunneling dark current. However, because a large bandwidth difference exists between the absorption layer and the multiplication layer, photogenerated carriers are easily accumulated at the interface of the absorption layer and the multiplication layer, and the response rate is reduced. In addition, the existing preparation methods of the avalanche photodetector are mainly divided into two types: (1) a table top type: the active area is corroded into a cylindrical table top, and the upper electrode and the lower electrode are respectively arranged at the top end of the table top and the lower part of the table top, so that the p area and the n area of the detector are electrically isolated. The preparation method can effectively reduce the parasitic capacitance of the detector, thereby improving the response speed of the detector, but the process flow is complex, particularly the side wall of the table top needs a special passivation process, and the dark current of the side wall of the table top is increased and the breakdown of the side wall of the table top is easily caused, thereby affecting the performance and the reliability of the detector; (2) plane diffusion type: a P-type metal contact layer is formed in a specific region in a Zn diffusion mode, and the non-diffused region is semi-insulating or weak n-type, so that the P region and the n region of the detector can be electrically isolated without mesa etching change. Because mesa etching is not needed, the preparation method can reduce the process complexity to a certain extent and reduce the problems of side wall leakage current and side wall breakdown caused by mesa etching. However, Zn diffusion is a process that is difficult to control accurately and varies widely. Instability of the Zn diffusion process causes inconsistency of the detector, and also reduces yield in production.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome the defects of the prior art and provides an avalanche photodetector.

The utility model is realized by the following technical scheme:

an avalanche photodetector comprises a back electrode, an n-type InP substrate, an n-type InP buffer layer, and In arranged from bottom to top_0.53Ga_0.47As absorption layer and In_xGa_1-xAs_yP_1-yThe band width gradient layer, the n-type InP charge control layer and the intrinsic InP multiplication layer are arranged on the intrinsic InP multiplication layer, a p-type InP central collector region, a p-type InP electric field protection ring and an InP isolation layer are arranged on the intrinsic InP multiplication layer, the p-type InP electric field protection ring surrounds the periphery of the p-type InP central collector region, a gap is reserved between the p-type InP electric field protection ring and the p-type InP central collector region, and the InP isolation layer is filled in a gap region between the p-type InP electric field protection ring and the p-type InP central collector region and a region on the periphery of the p-type InP electric field protection ring;

an optical antireflection film with a metal contact window is arranged on the p-type InP central collector region, the p-type InP electric field protection ring and the InP isolation layer, and the metal contact window is positioned on the p-type InP central collector region;

an upper electrode with an optical incidence window is arranged on the optical antireflection film, and the upper electrode is contacted with the p-type InP central collector region through a metal contact window on the optical antireflection film; an optical entrance window on the upper electrode is located above the optical antireflection film above the p-type InP central collector region.

In the technical scheme, SiO is also arranged between the InP isolation layer and the optical antireflection film₂An isolation layer; the above-mentionedThe upper electrode and the metal wiring board are connected together by evaporation; the metal wiring board is positioned on SiO₂The upper surface of the optical antireflection film on the spacer layer is made of SiO₂The isolation layer increases the distance between metal wiring board and the InP isolation layer to reduce the electric capacity, increase the response speed of detector.

In the above technical solution, the top surface of the InP isolation layer is flush with the top surfaces of the p-type InP central collector region and the p-type InP electric field guard ring; the depth of the bottom surface of the InP isolating layer exceeds the bottom surface of the p-type InP central collector region and the bottom surface of the p-type InP electric field protection ring.

In the above technical solution, the metal contact window is annular.

In the above technical scheme, the thickness of the n-type InP buffer layer is 0.1-1um, the thickness of the n-type InP charge control layer is 200-500nm, the thickness of the intrinsic InP multiplication layer is 300-800nm, and In is_0.53Ga_0.47The thickness of the As absorption layer is 1-5um, and the thickness of the InP barrier layer is 0.8-2 um.

In the above technical solution, the In_xGa_1-xAs_yP_1-yThe bandwidth gradient layer comprises N layers of In with gradually changed components_xGa_1- _xAs_yP_1-yLayer with N not less than 1, preferably 3 layers, each layer having a bandwidth of 0.75eV-1.35eV, In_xGa_1-xAs_yP_1-yThe bandwidth of each layer of the bandwidth gradual change layer is increased from bottom to top In sequence_0.53Ga_0.47The bandwidth of the As absorption layer gradually changes to the bandwidth of the n-type InP charge control layer, so that the accumulation of photon-generated carriers at the interface can be effectively reduced.

In the technical scheme, the p-type InP central collector region is circular, has the diameter of 50um and the thickness of 1um, adopts Zn in-situ heavy doping, forms ohmic contact with an upper electrode and plays a role of a window layer; the electric field protection rings surrounding the central collector region are annular, the thickness of each electric field protection ring is also 1um, the number of the electric field protection rings is 1 or more, the electric field protection rings are arranged at intervals, and InP isolation layers are filled in annular interval regions among the electric field protection rings; the electric field protection ring can effectively reduce the edge electric field of the p-type InP central collector region, thereby reducing the probability of edge breakdown and reducing tunneling dark current.

In the technical scheme, the InP blocking layer is semi-insulating or weak n-type, and forms a reverse bias PN junction potential barrier with the adjacent p-type InP central collector region and the p-type InP electric field protection ring, so that the collector region is electrically insulated from other regions.

In the above technical solution, the SiO₂The isolation layer is annular and has a thickness of 500nm to 1500 nm.

The utility model has the advantages and beneficial effects that:

1. in with multiple layers of different bandwidths_xGa_1-xAs_yP_1-yThe layer is used as a bandwidth gradual change layer and realizes In_0.53Ga_0.47The bandwidth between the As absorption layer and the InP charge control layer is smoothly transited, so that the accumulation of photon-generated carriers is reduced, and the response speed of the detector is improved.

2. The central collector region is used for forming ohmic contact with the upper electrode and simultaneously plays a role of a window layer. The electric field protection ring surrounding the central collector region can effectively reduce the electric field intensity at the edge of the collector region, reduce the probability of the edge of the detector being broken down and reduce the tunneling dark current at the edge.

And 3, the InP blocking layer is semi-insulating or weak n-type, and forms a reverse bias PN junction potential barrier with the adjacent p-type InP central collector region and the p-type InP electric field protection ring, so that the collector region is electrically insulated from other regions.

And 4, the thickness and doping of the n-type InP charge control layer and the intrinsic InP multiplication layer are accurately controlled by the first epitaxial growth, so that the problem of detector inconsistency caused by instability of a Zn diffusion process in a preparation method of a diffusion detector does not exist.

5. SiO with the thickness of 500nm to 1500nm is added between the upper electrode metal wiring board and the InP barrier layer₂The isolation layer effectively reduces the capacitance between the metal wiring board and the InP blocking layer, and improves the response speed of the detector.

Drawings

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a schematic flow diagram of the present invention.

Wherein:

1: an n-type InP substrate is provided,

2: an n-type InP buffer layer is formed,

3：In_0.53Ga_0.47an As absorption layer is arranged on the substrate,

4：In_xGa_1-xAs_yP_1-ya bandwidth gradual-change layer is arranged on the upper surface of the optical fiber,

5: an n-type InP charge control layer,

6: an intrinsic InP multiplication layer is formed on the substrate,

7: p-type InP central collector, 7.1: a p-type InP cap layer is formed,

8: a p-type InP electric field protection ring,

9: an InP barrier layer is formed on the substrate,

10：SiO₂the isolation layer is arranged on the substrate,

11: an optical anti-reflection film is provided,

12: the metal contact window of the optical antireflection film,

13: upper electrode, 13.1: a metal wire-striking plate is arranged on the base,

14: the optical entrance window of the upper electrode,

15: a back electrode.

For a person skilled in the art, other relevant figures can be obtained from the above figures without inventive effort.

Detailed Description

In order to make the technical solution of the present invention better understood, the technical solution of the present invention is further described below with reference to specific examples.

Example one

Referring to fig. 1, the present embodiment provides an avalanche photodetector, which includes a back electrode 15, an n-type InP substrate 1, an n-type InP buffer layer 2, In, which are sequentially disposed from bottom to top_0.53Ga_0.47As absorption layer 3, In_xGa_1-xAs_yP_1-yA bandwidth gradient layer 4, an n-type InP charge control layer 5 and an intrinsic InP multiplication layer 6, wherein a p-type InP central collector region 7, a p-type InP electric field protection ring 8 and an InP isolation layer are arranged on the intrinsic InP multiplication layer 6And 9, the p-type InP electric-field protection rings 8 surround the p-type InP central collector region 7 with a space therebetween, the number of the p-type InP electric-field protection rings is 1 or more, the number of the p-type InP electric-field protection rings is 1 in the present embodiment, and the InP isolation layer 9 fills the space region between the p-type InP electric-field protection rings 8 and the p-type InP central collector region 7 and the region around the p-type InP electric-field protection rings 8. If the electric field protection rings are a plurality of electric field protection rings, the electric field protection rings are arranged at intervals, and the annular interval area between the electric field protection rings is filled with an InP isolation layer.

The top surface of the InP isolation layer 9 is flush (i.e., flush) with the top surface of the p-InP central collector region 7 and the top surface of the p-InP electric-field protection ring 8, and the depth of the bottom surface of the InP isolation layer 9 is greater than the depth of the bottom surface of the p-InP central collector region 7 and the bottom surface of the p-InP electric-field protection ring 8.

An optical antireflection film 11 with a metal contact window 12 is arranged on the p-type InP central collector region 7, the p-type InP electric field protection ring 8 and the InP isolation layer 9, wherein the metal contact window 12 is annular and is positioned on the p-type InP central collector region 7.

An upper electrode 13 with an optical incident window 14 is arranged on the optical antireflection film 11, the upper electrode 13 is contacted with the p-type InP central collector region 7 through a metal contact window 12 on the optical antireflection film 11, and ohmic contact is formed through annealing; an optical entrance window 14 on the upper electrode 13 is located above the optical antireflection film 11 above the p-type InP central collector region 7.

In addition, SiO with a certain thickness is arranged between the InP isolation layer and the optical antireflection film 11 at the periphery of the electric field protection ring 8₂An isolation layer 10; the upper electrode 13 and the metal routing plate 13.1 are connected together through evaporation; the metal routing plate 13.1 is circular, has a diameter of 60um and is positioned on SiO₂The upper surface of the optical antireflection film 11 on the spacer layer 10 passes through SiO₂The distance between the metal routing plate 13.1 and the InP isolation layer is increased by the isolation layer 10, so that the capacitance is reduced, and the response speed of the detector is increased.

Example two

In addition to the first embodiment, the n-type InP substrate 1 is heavily doped and a back electrode15 form ohmic contacts. In this embodiment, the n-type InP buffer layer 2 has a thickness of 0.5um, and serves to better match the n-type InP substrate 1 with In_0.53Ga_0.47The difference of lattice constants between the As absorption layers 3 due to the difference of growth conditions ensures the growth quality of the epitaxial layers.

Further, In this embodiment, In_0.53Ga_0.47The thickness of the As absorption layer 3 is 2um, and the background doping concentration is less than 1 multiplied by 10¹⁵/cm³The layer is a photogenerated carrier generation layer and is designed to absorb photon energy with the wavelength of 1.0-1.7 um as far as possible.

Further, In this embodiment, In_xGa_1-xAs_yP_1-yThe bandwidth gradual change layer 4 comprises three layers, and the bandwidth of each layer is 0.95eV, 1.03eV and 1.13eV from bottom to top respectively; three layers of bandwidth graded layer In_0.53Ga_0.47The bandwidth of the As absorption layer 3 gradually changes to the bandwidth of the n-type InP charge control layer 5, and the accumulation of photon-generated carriers at the interface can be effectively reduced.

Further, in the present embodiment, the n-type InP charge control layer 5 has a thickness of 300nm and a doping concentration of 6 × 10¹⁶/cm³. The thickness and doping concentration of this layer determine the onset voltage of the detector avalanche effect.

Further, in the present embodiment, the thickness of the intrinsic InP multiplication layer 6 is 500nm, and the background doping concentration is less than 1 × 10¹⁵/cm³。

Further, in this embodiment, the p-type InP central collector region 7 is circular, has a diameter of 50um and a thickness of 1um, and is heavily doped with Zn in-situ to form ohmic contact with the upper electrode 13 and function as a window layer. The electric field protection ring 8 surrounding the central collector region 7 is of a circular ring shape, the thickness of the electric field protection ring is also 1um, the width of the electric field protection ring is 10um (namely the difference between the inner diameter and the outer diameter of the electric field protection ring is 10um), the distance between the electric field protection ring and the central collector region 7 is 15um, and the electric field protection ring 8 can effectively reduce the fringe electric field of the p-type InP central collector region 7, so that the probability of fringe breakdown is reduced, and tunneling dark current is reduced. The p-type InP central collector region 7 and the electric field guard ring 8 are formed by selectively etching the p-type InP cap layer and a part of the p-type InP cap layer remaining after the intrinsic InP multiplication layer 6, and the etching depth is 1.2um, and the 1.2um etching depth includes the 1um thick p-type InP cap layer and the 0.2um deep intrinsic InP multiplication layer below the p-type InP cap layer.

Further, in this embodiment, the InP barrier layer 9 has a thickness of 1.2um, and is formed by performing secondary epitaxial filling in the etched-off region. After the second epitaxy, the thickness of the filling-grown InP barrier layer 9 is the same as the thickness of the etched-off InP, thereby achieving a flat surface. The InP barrier layer 9 of the secondary epitaxy is semi-insulating or weak n-type, and forms a reverse bias PN junction potential barrier with the rest part of the adjacent p-type InP cover layer, so that the electrical insulation of the collector region and other regions is realized. In addition, because the InP barrier layer of the secondary epitaxy and the corroded material are InP base materials, the crystal quality of the secondary epitaxy is high, the defect density of an interface is reduced, and leakage current can be effectively reduced.

Further, in the present embodiment, the SiO₂The isolation layer 10 is annular, and thickness is 1 um.

EXAMPLE III

As shown in fig. 2, the present embodiment introduces a method for manufacturing the avalanche photodetector, which includes the following steps:

the method comprises the following steps: an n-type InP buffer layer 2 and In are sequentially grown on an n-type InP substrate 1_0.53Ga_0.47As absorption layer 3, In_xGa_1-xAs_yP_1-yA bandwidth gradient layer 4, an n-type InP charge control layer 5, an intrinsic InP multiplication layer 6 and a p-type InP cover layer 7.1.

Step two: using SiO₂Patterning the hard mask, and etching a p-type InP cover layer 7 and a part of an intrinsic InP multiplication layer 6 in a specific region by using an etching method, wherein the p-type InP cover layer 7.1 is 1um thick, the intrinsic InP multiplication layer 6 is 500nm thick, and the etching depth is 1.2um, namely the 1.2um etching depth comprises the 1um thick p-type InP cover layer and the 0.2um deep intrinsic InP multiplication layer below the p-type InP cover layer, and a central collector region 7 and an electric field protection ring 8 surrounding the central collector region are formed in the residual InP cover layer 7.1 after etching, wherein the p-type InP central collector region 7 is circular and 50um in diameterum, the electric field protection ring 8 is a circular ring, the number of the electric field protection rings 8 is one or more, the number of the electric field protection rings 8 is one in this embodiment, the width of the electric field protection ring 8 is 10um (i.e. the difference between the inner diameter and the outer diameter of the electric field protection ring is 10um), and the distance between the electric field protection ring 8 and the central collector region 7 is 15 um; if there are a plurality of field guard rings 8, then an annular space is left between each field guard ring 8.

Step three: using the same SiO as in step two₂A hard mask pattern, wherein an InP blocking layer 9 is generated in the etched area in the second step through secondary epitaxy, and the thickness of the InP blocking layer 9 subjected to secondary epitaxy is consistent with the thickness etched in the second step; after the second epitaxy, etching off SiO by using etching method₂Hard masking to obtain a flat surface that makes the top surface of the twice-epitaxial InP spacer 9, the top surface of the p-InP central collector region 7, and the top surface of the p-InP electric-field guard ring 8 flush.

Step four: depositing SiO on the flat surface obtained in step three₂Layer, then etching away partial region of SiO using a photoresist patterned mask₂So that a ring of SiO is formed on the InP isolation layer at the periphery of the electric field protection ring 8₂ Isolation layer 10, SiO₂The thickness of the isolation layer 10 is 1 um.

Step five: in the central collector region 7, the electric field protection ring 8, the InP isolation layer 9 of the secondary epitaxy, SiO₂An optical antireflection film 11 is deposited on the surface of the isolation layer 10, and an annular metal contact window 12 is formed on the optical antireflection film 11 above the central collector region 7 by using an etching method.

Step six: forming an upper electrode metal and metal wiring board graph by using photoresist, evaporating metal and carrying out metal stripping to obtain a graphical upper electrode 13 and a graphical metal wiring board 13.1; an upper electrode 13 is contacted with the p-type InP central collector region 7 through the metal contact window 12 in the fifth step, and ohmic contact is formed by annealing; the metal wiring board 13.1 is positioned on SiO₂Right above the isolation layer 10; the upper electrode 13 has an optical entrance window 14, and the optical entrance window 14 is above the central collector region 7.

Step seven: and thinning and polishing the back surface of the n-type InP substrate 1, preparing a back electrode 15 on the lower surface of the n-type InP substrate, and annealing to form ohmic contact.

The utility model has been described in an illustrative manner, and it is to be understood that any simple variations, modifications or other equivalent changes which can be made by one skilled in the art without departing from the spirit of the utility model fall within the scope of the utility model.

Claims

1. An avalanche photodetector, characterized by: comprises a back electrode, an n-type InP substrate, an n-type InP buffer layer, In_0.53Ga_0.47As absorption layer and In_xGa_1-xAs_yP_1-yThe band width gradient layer, the n-type InP charge control layer and the intrinsic InP multiplication layer are arranged on the intrinsic InP multiplication layer, a p-type InP central collector region, a p-type InP electric field protection ring and an InP isolation layer are arranged on the intrinsic InP multiplication layer, the p-type InP electric field protection ring surrounds the periphery of the p-type InP central collector region, a gap is reserved between the p-type InP electric field protection ring and the p-type InP central collector region, and the InP isolation layer is filled in a gap region between the p-type InP electric field protection ring and the p-type InP central collector region and a region on the periphery of the p-type InP electric field protection ring;

2. The avalanche photodetector of claim 1, wherein: SiO is arranged between the InP isolation layer and the optical antireflection film₂An isolation layer; the upper electrode and the metal wiring board are connected together through evaporation; the metal wiring board is positioned on SiO₂An upper surface of the optical antireflection film over the spacer layer.

3. The avalanche photodetector of claim 1, wherein: the top surface of the InP isolating layer is flush with the top surface of the p-type InP central collector region and the top surface of the p-type InP electric field protection ring.

4. The avalanche photodetector of claim 1, wherein: the depth of the bottom surface of the InP isolating layer exceeds the bottom surface of the p-type InP central collector region and the bottom surface of the p-type InP electric field protection ring.

5. The avalanche photodetector of claim 1, wherein: the metal contact window is annular.

6. The avalanche photodetector of claim 1, wherein: the thickness of the n-type InP buffer layer is 0.1-1um, the thickness of the n-type InP charge control layer is 200-500nm, the thickness of the intrinsic InP multiplication layer is 300-800nm, and In_0.53Ga_0.47The thickness of the As absorption layer is 1-5um, and the thickness of the InP barrier layer is 0.8-2 um.

7. The avalanche photodetector of claim 1, wherein: said In_xGa_1-xAs_yP_1-yThe bandwidth gradient layer comprises N layers of In with gradually changed components_xGa_1-xAs_yP_1-yLayer, N is greater than or equal to 1, the bandwidth of each layer is between 0.75eV and 1.35eV, In_xGa_1-xAs_yP_1-yThe bandwidth of each layer of the bandwidth gradual change layer is increased from bottom to top In sequence_0.53Ga_0.47The bandwidth of the As absorption layer gradually changes to the bandwidth of the n-type InP charge control layer.

8. The avalanche photodetector of claim 1, wherein: the p-type InP central collector region is circular, and forms ohmic contact with the upper electrode by adopting Zn in-situ heavy doping; the electric field protection rings surrounding the central collector region are annular, the number of the electric field protection rings is 1 or more, the electric field protection rings are arranged at intervals, and InP isolation layers are filled in annular interval regions among the electric field protection rings.

9. The avalanche photodetector of claim 1, wherein: the InP barrier layer is semi-insulating or weak n-type, and forms a reverse bias PN junction potential barrier with the adjacent p-type InP central collector region and the p-type InP electric field protection ring.

10. The avalanche photodetector of claim 2, wherein: the SiO₂The isolation layer is annular and has a thickness of 500nm to 1500 nm.