CN216390806U - Output peak current balance adjusting circuit - Google Patents
Output peak current balance adjusting circuit Download PDFInfo
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- CN216390806U CN216390806U CN202122196325.XU CN202122196325U CN216390806U CN 216390806 U CN216390806 U CN 216390806U CN 202122196325 U CN202122196325 U CN 202122196325U CN 216390806 U CN216390806 U CN 216390806U
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- 239000003990 capacitor Substances 0.000 claims description 22
- 230000003287 optical effect Effects 0.000 claims description 20
- 238000004804 winding Methods 0.000 claims description 12
- 238000010521 absorption reaction Methods 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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Abstract
The utility model relates to an output peak current balance regulating circuit, which comprises a power supply primary module and a direct current stabilized power supply module, wherein the direct current stabilized power supply module comprises a transformer, a main control circuit and a secondary rectifying circuit; the main control circuit comprises a control chip and a balance circuit, wherein the control chip is provided with a CS pin for detecting secondary voltage and realizing overload protection, and the balance circuit is connected with the CS pin of the control chip on one hand and is connected with the output anode of the power supply primary module on the other hand. Through the balance circuit, when input voltage is big more, make control chip's CS foot voltage also big more, and when control chip's CS foot voltage is close to the setting value that triggers overload protection, the big more will trigger control chip more soon of input voltage and protect, through the resistance of adjusting balance circuit, can realize that under different input voltages, the peak current of output keeps unanimous basically.
Description
Technical Field
The utility model relates to the technical field of switching power supplies, in particular to an output peak current balance adjusting circuit.
Background
In the application of the switching power supply, there is a problem that is difficult to solve: under different input conditions, the output peak current of the switching power supply is greatly different, which is generally represented by a product with a high input voltage and a large output peak current, such as 12V/2A, and assuming that the output peak current is 3.2A at the input of 100V, the output peak current is generally larger than 3.2A, and possibly 4.0A or even larger at the input of 240V.
Aiming at the problems, the feasible method is few if the peak currents output under different input voltages are required to be basically consistent, and the better method is to change the turn ratio of the transformer, but the performance of the whole switching power supply is possibly influenced after the transformer is changed, so that the method is troublesome.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, an object of the present invention is to provide an output peak current balance adjustment circuit, which can achieve substantially uniform output peak current at different input voltages.
In order to achieve the purpose, the utility model discloses an output peak current balance adjusting circuit which comprises a power supply primary module and a direct current stabilized power supply module, wherein the direct current stabilized power supply module comprises a transformer, a main control circuit and a secondary rectifying circuit, the power supply primary module, the transformer and the secondary rectifying circuit are sequentially connected, and the main control circuit is connected with a primary winding of the transformer; the main control circuit comprises a control chip and a balance circuit, wherein the control chip is provided with a CS pin for detecting secondary voltage and realizing overload protection, and the balance circuit is connected with the CS pin of the control chip on one hand and is connected with the output anode of the power supply primary module on the other hand.
Preferably, the balancing circuit comprises a resistor string, the resistor string comprises at least one resistor, one end of the resistor string is connected with the CS pin of the control chip, and the other end of the resistor string is connected with the output anode of the power supply primary module.
Preferably, the resistor string comprises at least one resistor with a large resistance value and at least one resistor with a small resistance value which are connected in series.
Preferably, the resistor string includes two resistors with a large resistance value and one resistor with a small resistance value.
Preferably, the resistance value of the large-resistance resistor is 2-5.1M omega, and the resistance value of the small-resistance resistor is 0-10K omega.
Preferably, the resistor is a patch resistor.
Preferably, the dc regulated power supply module further includes an optical coupler feedback circuit, and the optical coupler feedback circuit is connected to the secondary rectification circuit on one hand and the main control circuit on the other hand; the emitter of an optical coupler PH1 in the optical coupler feedback circuit is grounded on one hand, and on the other hand, the emitter is connected with a CS pin of a control chip through a resistor R15.
Preferably, in the optical coupler feedback circuit, an anode of the optical coupler PH1 is connected with an output anode of the secondary rectification circuit through a resistor R19, and is connected with a cathode of the optical coupler PH1, one end of a capacitor C5 and a cathode of a voltage stabilizing source IC2 through a resistor R20; the other end of the capacitor C5 is connected with one end of a resistor RA1, one end of a resistor R21 and a reference electrode of a voltage-stabilizing source IC2, and the other end of the resistor RA1 and the anode of the voltage-stabilizing source IC2 are connected with the output negative electrode of the secondary rectifying circuit; the other end of the resistor R21 is connected with the output anode of the secondary rectifying circuit.
Preferably, in the master control circuit, pin 2 of the control chip IC1 is connected to one end of a capacitor C3 and a collector of the optocoupler PH1, and the other end of the capacitor C3 is grounded; the pin 3 of the control chip IC1 is grounded with the pin 1 of the control chip IC1 after passing through the resistor R9; a pin 5 of the control chip IC1 is connected with the anode of the electrolytic capacitor EC2, the cathode of the diode D2 and one end of the resistor RA2 after passing through the resistor R8, the cathode of the electrolytic capacitor EC2 is grounded, the anode of the diode D2 is connected with one end of the auxiliary winding of the transformer T1, and the other end of the resistor RA2 is connected with the output anode of the power primary module; a pin 6 of the control chip IC1 is connected with the cathode of the diode D3 and one end of the resistor R10, the anode of the diode D3 is connected with the other end of the resistor R10, one end of the resistor R6 and the gate of the MOS transistor Q1, and the other end of the resistor R6 and the source of the MOS transistor Q1 are connected with a pin CS of the control chip IC 1; the drain of the MOS transistor Q1 is connected to the output terminal of the primary winding of the transformer T1.
Preferably, the primary winding of the transformer is also connected in parallel with an RCD absorption circuit for absorbing leakage inductance.
The utility model has the following beneficial effects:
according to the utility model, the voltage of the CS pin of the control chip is larger when the input voltage is larger, and the control chip is triggered to be protected when the voltage of the CS pin of the control chip is close to a set value for triggering overload protection, the larger the input voltage is, and the output peak current can be basically kept consistent under different input voltages by adjusting the resistance value of the balancing circuit. Compared with the method for changing the turn ratio of the transformer, the method for adjusting the resistance value of the balancing circuit is undoubtedly simpler, and is smaller in workload and lower in cost.
Drawings
Fig. 1 is a schematic connection diagram of a balancing circuit.
FIG. 2 is a schematic diagram of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments.
As shown in fig. 1 and 2, the present invention discloses an output peak current balance adjusting circuit, which comprises a power supply primary module and a dc stabilized power supply module, wherein the dc stabilized power supply module comprises a transformer T1, a main control circuit, a secondary rectifying circuit and an optocoupler feedback circuit, the power supply primary module, the transformer and the secondary rectifying circuit are connected in sequence, and the main control circuit is connected with a primary winding of the transformer. The main control circuit comprises a control chip IC1 and a balancing circuit, and a control chip IC1 is provided with a CS pin for detecting a secondary voltage and realizing overload protection. The optical coupling feedback circuit is connected with the secondary rectifying circuit on one hand and the main control circuit on the other hand; the emitter of an optical coupler PH1 in the optical coupler feedback circuit is grounded on one hand, and on the other hand, the emitter is connected with a CS pin of a control chip IC1 through a resistor R15. The balancing circuit comprises a resistor string, at least one resistor is arranged in the resistor string, one end of the resistor string is connected with a CS pin of the control chip IC1, and the other end of the resistor string is connected with an output anode of the power supply primary module. The control chip IC1 may be a common power management chip, such as KP201, OB2281AMP, etc.
Preferably, the resistor string comprises at least one resistor with a large resistance value and at least one resistor with a small resistance value which are connected in series, and the resistor with the small resistance value is used for trimming the current. In addition, the resistor is preferably a chip resistor, and the chip resistor has the advantages of small size, small temperature coefficient, high reliability, low assembly cost and the like. Specifically, the resistor string comprises two resistors with large resistance and one resistor with small resistance (the resistors R101/R102/R103 are respectively), the resistance of the resistor with large resistance is 2-5.1M omega, the resistance of the resistor with small resistance is 0-10K omega, the resistances of the resistor string formed by the three resistors are relatively better matched, and the replacement is more convenient and flexible.
L, N in the power supply primary module is connected with commercial power, enters an EMI filter circuit consisting of a capacitor CX1, a resistor R1/R2 and a filter LF1 after passing through a fuse F1 and a voltage dependent resistor VR, is filtered, is rectified into direct current through a rectifier bridge BR1 and is sent to a transformer, energy is coupled to the secondary side of the transformer under the control of a main control circuit, and finally the stable direct current is output after rectification and filtering through a secondary rectifier circuit (consisting of a diode D4/D5, a capacitor C4/C7, an electrolytic capacitor EC3/EC4 and a resistor R16). In order to absorb leakage inductance and prevent a spike voltage generated by the leakage inductance from causing avalanche breakdown of a MOS (metal oxide semiconductor) tube built in a control chip IC1, an RCD absorption circuit (composed of resistors R3/R3A/R4/R5, a capacitor C2 and a diode D1) is connected in parallel to a primary winding of a transformer T1.
In the optical coupler feedback circuit, the anode of an optical coupler PH1 is connected with the output anode of a secondary rectification circuit through a resistor R19 on one hand, and is connected with the cathode of the optical coupler PH1, one end of a capacitor C5 and the cathode of a voltage-stabilizing source IC2 through a resistor R20 on the other hand; the other end of the capacitor C5 is connected with one end of a resistor RA1, one end of a resistor R21 and a reference electrode of a voltage-stabilizing source IC2, and the other end of the resistor RA1 and the anode of the voltage-stabilizing source IC2 are connected with the output negative electrode of the secondary rectifying circuit; the other end of the resistor R21 is connected with the output anode of the secondary rectifying circuit.
In the master control circuit, a pin 2 of a control chip IC1 is connected with one end of a capacitor C3 and a collector of an optocoupler PH1, and the other end of the capacitor C3 is grounded; the pin 3 of the control chip IC1 is grounded with the pin 1 of the control chip IC1 after passing through the resistor R9; a pin 5 of the control chip IC1 is connected with the anode of the electrolytic capacitor EC2, the cathode of the diode D2 and one end of the resistor RA2 after passing through the resistor R8, the cathode of the electrolytic capacitor EC2 is grounded, the anode of the diode D2 is connected with one end of the auxiliary winding of the transformer T1, and the other end of the resistor RA2 is connected with the output anode of the power primary module; pin 6 of the control chip IC1 is connected to the cathode of the diode D3 and one end of the resistor R10, the anode of the diode D3 is connected to the other end of the resistor R10, one end of the resistor R6 and the gate of the MOS transistor Q1, and the other end of the resistor R6 and the source of the MOS transistor Q1 are connected to pin CS (pin 4) of the control chip IC 1; the drain of the MOS transistor Q1 is connected to the output terminal of the primary winding of the transformer T1.
Without a balancing circuit, the control chip IC1 has the control principle of detecting the voltage of the CS pin of the control pin to realize the output overload protection function, i.e. when the output power is gradually increased, the current flowing through the resistor R15 is gradually increased, the voltage V1 of the CS pin of the control chip IC1 is also gradually increased, and when V1 is increased to the set protection value (usually 0.5 or 0.7V) of the control chip IC1, the control chip IC1 triggers protection. When the output is no load, the current flowing through R15 is nearly zero, i.e., the voltage V1 of the CS pin of the control chip IC1 is nearly zero when the output is no load.
After the balance circuit is connected, three resistors R101/R102/R103 are connected in series with the output anode of the power primary module to the CS pin of the control chip IC1, when the power is switched on (the output is no load), the voltage of the output anode of the power primary module forms a loop through the resistor R101, the resistor R102, the resistor R103 and the resistor R15, and current flows through R15, namely the voltage V1 of the CS pin of the IC1 is not zero. Under the same condition, the larger the input voltage is, the larger the voltage flowing through R15 is, and the larger V1 is. At this time, when the input voltage is gradually increased, since the voltage of V1 is increased as the input voltage is increased when there is no load, the protection is triggered more quickly as the input voltage is increased when V1 approaches the set trigger value.
Since the output peak current of the general switching power supply is larger when the input voltage is larger, the application can quicken the protection when the input voltage is higher. By adjusting the resistance values of the resistors R101/R102/R103, the input peak current can be basically kept consistent under different input voltage conditions.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. An output peak current balance adjustment circuit, characterized in that: the direct-current stabilized power supply comprises a power supply primary module and a direct-current stabilized power supply module, wherein the direct-current stabilized power supply module comprises a transformer, a main control circuit and a secondary rectification circuit, the power supply primary module, the transformer and the secondary rectification circuit are sequentially connected, and the main control circuit is connected with a primary winding of the transformer; the main control circuit comprises a control chip and a balance circuit, wherein the control chip is provided with a CS pin for detecting secondary voltage and realizing overload protection, and the balance circuit is connected with the CS pin of the control chip on one hand and is connected with the output anode of the power supply primary module on the other hand.
2. The output peak current balance adjustment circuit according to claim 1, characterized in that: the balancing circuit comprises a resistor string, at least one resistor is arranged in the resistor string, one end of the resistor string is connected with a CS pin of the control chip, and the other end of the resistor string is connected with an output anode of the power supply primary module.
3. The output peak current balance adjustment circuit according to claim 2, characterized in that: the resistor string comprises at least one resistor with a large resistance value and at least one resistor with a small resistance value which are connected in series.
4. The output peak current balance adjustment circuit according to claim 3, characterized in that: the resistor string comprises two resistors with large resistance values and a resistor with a small resistance value.
5. The output peak current balance adjustment circuit according to claim 4, wherein: the resistance value of the large-resistance resistor is 2-5.1M omega, and the resistance value of the small-resistance resistor is 0-10K omega.
6. The output peak current balance adjustment circuit according to any one of claims 2 to 5, wherein: the resistor is a chip resistor.
7. The output peak current balance adjustment circuit according to claim 1, characterized in that: the direct current stabilized voltage supply module further comprises an optical coupler feedback circuit, and the optical coupler feedback circuit is connected with the secondary rectification circuit on one hand and the main control circuit on the other hand; the emitter of an optical coupler PH1 in the optical coupler feedback circuit is grounded on one hand, and on the other hand, the emitter is connected with a CS pin of a control chip through a resistor R15.
8. The output peak current balance adjustment circuit according to claim 7, characterized in that: in the optical coupler feedback circuit, an anode of an optical coupler PH1 is connected with an output anode of a secondary rectification circuit through a resistor R19 on one hand, and is connected with a cathode of the optical coupler PH1, one end of a capacitor C5 and a cathode of a voltage-stabilizing source IC2 through a resistor R20 on the other hand; the other end of the capacitor C5 is connected with one end of a resistor RA1, one end of a resistor R21 and a reference electrode of a voltage-stabilizing source IC2, and the other end of the resistor RA1 and the anode of the voltage-stabilizing source IC2 are connected with the output negative electrode of the secondary rectifying circuit; the other end of the resistor R21 is connected with the output anode of the secondary rectifying circuit.
9. The output peak current balance adjustment circuit according to claim 7, characterized in that: in the master control circuit, a pin 2 of a control chip IC1 is connected with one end of a capacitor C3 and a collector of an optocoupler PH1, and the other end of the capacitor C3 is grounded; the pin 3 of the control chip IC1 is grounded with the pin 1 of the control chip IC1 after passing through the resistor R9; a pin 5 of the control chip IC1 is connected with the anode of the electrolytic capacitor EC2, the cathode of the diode D2 and one end of the resistor RA2 after passing through the resistor R8, the cathode of the electrolytic capacitor EC2 is grounded, the anode of the diode D2 is connected with one end of the auxiliary winding of the transformer T1, and the other end of the resistor RA2 is connected with the output anode of the power primary module; a pin 6 of the control chip IC1 is connected with the cathode of the diode D3 and one end of the resistor R10, the anode of the diode D3 is connected with the other end of the resistor R10, one end of the resistor R6 and the gate of the MOS transistor Q1, and the other end of the resistor R6 and the source of the MOS transistor Q1 are connected with a pin CS of the control chip IC 1; the drain of the MOS transistor Q1 is connected to the output terminal of the primary winding of the transformer T1.
10. The output peak current balance adjustment circuit according to claim 1, characterized in that: and the primary winding of the transformer is also connected with an RCD absorption circuit for absorbing leakage inductance in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122196325.XU CN216390806U (en) | 2021-09-10 | 2021-09-10 | Output peak current balance adjusting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122196325.XU CN216390806U (en) | 2021-09-10 | 2021-09-10 | Output peak current balance adjusting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216390806U true CN216390806U (en) | 2022-04-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122196325.XU Active CN216390806U (en) | 2021-09-10 | 2021-09-10 | Output peak current balance adjusting circuit |
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| CN (1) | CN216390806U (en) |
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2021
- 2021-09-10 CN CN202122196325.XU patent/CN216390806U/en active Active
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Address after: 361000 Xiamen Torch High tech Zone (Xiang'an) Industrial Zone, Xianghai Second Road, Xiamen City, Fujian Province, China, Accelerator Phase III, Building 3 Patentee after: XIAMEN XUNHENG ELECTRONICS TECH Co.,Ltd. Country or region after: China Address before: Room 3047, Xuanye building, Chuangye Park, torch high tech Zone, Xiamen City, Fujian Province Patentee before: XIAMEN XUNHENG ELECTRONICS TECH Co.,Ltd. Country or region before: China |