CN216350808U

CN216350808U - Master-slave board test system for collecting multiple station resources

Info

Publication number: CN216350808U
Application number: CN202122377577.2U
Authority: CN
Inventors: 董秦博; 杨宏斌; 牟云飞; 刘伟锋; 李黎斌; 吴美均
Original assignee: Xi'an Xigu Microelectronics Co ltd
Current assignee: Xi'an Xigu Microelectronics Co ltd
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2022-04-19
Anticipated expiration: 2031-09-29

Abstract

The utility model relates to the technical field of mixed signal testing, in particular to a master-slave board testing system for collecting a plurality of station resources, which comprises a testing mother board arranged horizontally and a testing daughter board arranged at the top of the testing mother board in a connecting way, and comprises: the seat head is fixedly connected with the center of the top of the test mother board; the direct current resource sockets are distributed on two sides of the socket head; the alternating current resource socket is fixedly arranged on the left side of the socket head; the relay group is fixedly arranged on the test motherboard through pins; and the bottom of the test daughter board is provided with a connecting contact corresponding to the socket head, and each connecting contact penetrates through the test daughter board and is electrically connected with the test part at the top. The utility model realizes dual purposes by reasonably distributing resources, improves the testing efficiency, realizes the floating precision measurement and greatly improves the stability and the reliability.

Description

Master-slave board test system for collecting multiple station resources

Technical Field

The utility model relates to the technical field of mixed signal testing, in particular to a master-slave board testing system for collecting a plurality of station resources.

Background

The STS8205 mixed signal test system is one of STS8200 series test products, and is provided with an STS8200 platform application most classical floating voltage current source (VI source for short) FPVI and FOVI. In order to make the compatibility of all kinds of boards and adapters of the original STS8105 series to the maximum extent and simplify the use of floating sources, the floating sources are connected into common ground source use in the standard configuration of the STS 8205. Thus, on the AD/DA class boards, the analog switch class boards, the operational amplifier class boards, the voltage regulator class boards, the pulse width modulator class boards, and the integrated class boards, the FPVI and FOVI provide technicians with the "high end" of the floating source, and the "low end" of the floating source is connected to AGND.

However, the above convenience is brought, and the flexible application of the floating source is limited to a certain extent. In addition, although the number of sockets of the load board is large, many resources are not selected and matched, and a relay assembly is not attached, so that the testing requirements can be met only by performing post processing on the load board by a tester, and therefore the problem of poor usability exists, and the like, and a mother board and a test daughter board need to be redesigned.

SUMMERY OF THE UTILITY MODEL

The utility model provides a mother-son board test system for collecting a plurality of station resources, which realizes dual purposes by reasonably distributing the resources, improves the test efficiency, realizes floating precision measurement and greatly improves the stability and the reliability.

In order to achieve the purpose, the utility model provides the following technical scheme: a master-slave board test system for collecting a plurality of station resources comprises a horizontally arranged test mother board and a test daughter board which is connected and arranged at the top of the test mother board, and comprises: the socket head is fixedly connected with the center of the top of the test mother board through pins, and the test daughter board is in adaptive connection with the top of the socket head through the bottom; the direct current resource sockets are arranged in a plurality of ways and distributed on two sides of the socket head at intervals, and each direct current resource socket is fixedly connected with the test motherboard through pins; the direct current resource socket is composed of a high-power resource FPVI socket and a low-power resource FOVI socket, the high-power resource FPVI socket is arranged on the left side of the test motherboard, and the low-power resource FOVI socket is arranged on the upper side of the test motherboard; the alternating current resource socket is fixedly arranged between the left side of the socket head and the high-power resource FPVI socket through pins; the relay group is fixedly arranged on the test motherboard through pins; the seat head is composed of a first connecting seat and a second connecting seat which is arranged in parallel with the first connecting seat at intervals; the first connecting seat comprises a first pin area, a second pin area and a third pin area, and the second connecting seat comprises a fourth pin area, a fifth pin area and a sixth pin area; the second pin area and the fourth pin area are respectively electrically connected with the high-power resource FPVI socket through leads; the third pin area is electrically connected with the alternating current resource socket through a lead; the first pin area and the fifth pin area are electrically connected with the low-power resource FOVI socket through leads; the sixth pin area is electrically connected with the relay set through a lead; and the bottom of the test daughter board is provided with a connecting contact corresponding to the socket head, and each connecting contact penetrates through the test daughter board and is electrically connected with the test part at the top.

Preferably, the high-power resource FPVI socket is connected with the socket head through a full floating connection method, 3 pins are used for FORCE, and one pin is used for SENSE; the low-power resource FOVI socket is connected with the socket head through a common ground connection method, positive FORCE and SENSE of each path are in short circuit at the socket head, negative FORCE of all channels is in short circuit with AGND, and all negative SENSE are in short circuit with DGS.

Preferably, each resource in the ac resource socket connects two adjacent pins.

Preferably, the relay group comprises 16 first relays and 4 second relays, every four first relays are in one group, each first relay COM in the same group is in short circuit, and NC and NO are led out; COM, NC and NO are respectively led out of the second relay.

Preferably, the first connecting seat and the second connecting seat both adopt 80-pin spring pin seats.

Preferably, the top of the test motherboard is provided with cover plates at intervals, and the cover plates are fixedly connected with the test motherboard through bolts.

The utility model has the beneficial effects that: the testing mother board and the testing daughter board are used for reasonably distributing resources, so that the dual-purpose of one machine is realized, the testing efficiency is improved, the floating V/I source meter technology of four-wire Kelvin output is adopted, the voltage sources can be connected in series, the current sources can be connected in parallel, the floating precision measurement can be realized, part of high-precision sources are directly connected, and the testing precision can be greatly improved without an internal relay. The resources are rearranged in a distributed arrangement, and the number of FOVI and FPVI sources is increased, so that the margin is provided for the test process. The relays are rearranged and preassembled, so that the testing process is easy to operate, the layout of the relays does not need to be independently reprogrammed and adjusted, and the stability and the reliability are greatly improved. The test daughter board is in contact fit with the spring needle seat, so that the test daughter board does not need to be welded in the test process, the time and the cost are saved, and the reliability is improved. The cover plate protects the test mother board and prevents devices and sundries from being left on the mother board to damage equipment and devices.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a connection mode of a test motherboard according to the present invention;

FIG. 2 is a schematic view of the connection status of the daughter board of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

According to fig. 1 and fig. 2, a daughter board test system for collecting a plurality of station resources includes a horizontally arranged test mother board 1, and a test daughter board 2 connected to the top of the test mother board 1, which includes: the socket head 3 is fixedly connected with the center of the top of the test mother board 1 through pins, and the test daughter board 2 is in adaptive connection with the top of the socket head 3 through the bottom; the direct current resource sockets are arranged in a plurality of ways and distributed on two sides of the socket head 3 at intervals, and each direct current resource socket is fixedly connected with the test mother board 1 through pins; the direct current resource socket is composed of a high-power resource FPVI socket 4 and a low-power resource FOVI socket 5, the high-power resource FPVI socket 4 is arranged on the left side of the test motherboard 1, and the low-power resource FOVI socket 5 is arranged on the upper side of the test motherboard 1; the alternating current resource socket 6 is fixedly arranged between the left side of the socket head 3 and the high-power resource FPVI socket 4 through pins; the relay group 7 is fixedly arranged on the test mother board 1 through pins; the seat head 3 is composed of a first connecting seat 8 and a second connecting seat 9 which is arranged in parallel with the first connecting seat 8 at intervals; the first connecting seat 8 comprises a first pin area 10, a second pin area 11 and a third pin area 12, and the second connecting seat 9 comprises a fourth pin area 13, a fifth pin area 14 and a sixth pin area 15; the second pin area 11 and the fourth pin area 13 are electrically connected to the high-power resource FPVI socket 4 through leads, respectively; the third pin area 12 is electrically connected with the ac resource socket 6 through a lead; the first pin area 10 and the fifth pin area 14 are electrically connected with the low-power-resource FOVI socket 5 through leads; the sixth pin area 15 is electrically connected with the relay unit 7 through a lead; and the bottom of the test daughter board 2 is provided with a connecting contact corresponding to the socket head 3, and each connecting contact penetrates through the test daughter board 2 and is electrically connected with the test part at the top.

Through the test mother board 1 and the test daughter board 2 which are arranged, resources are reasonably distributed, so that the dual-purpose of one machine is realized, the test efficiency is improved, the floating V/I source meter technology of four-wire Kelvin output is adopted, the voltage sources can be connected in series, the current sources can be connected in parallel, the floating precision measurement can be realized, part of high-precision sources are directly connected, and the test precision can be greatly improved without an internal relay.

The high-power resource FPVI socket 4 is connected with the socket head 3 through a full-floating connection method, 3 pins are used for FORCE, and one pin is used for SENSE; the low-power resource FOVI socket 5 is connected with the socket head 3 through a common ground connection method, positive FORCE and SENSE of each path are in short circuit at the socket head 3, negative FORCE of all channels is in short circuit with AGND, and negative SENSE of all channels is in short circuit with DGS. Each resource in the ac resource socket 6 connects two adjacent pins.

The resources are distributed and arranged again through the arrangement, the number of FOVI and FPVI sources is increased, and a margin is provided for a test process.

The relay group 7 comprises 16 first relays and 4 second relays, wherein every four first relays are in one group, each first relay COM in the same group is in short circuit, and NC and NO are led out; COM, NC and NO are respectively led out of the second relay.

Through the arrangement, the relays are rearranged and preassembled, so that the testing process is easy to operate, the layout of the relays does not need to be independently reprogrammed and adjusted, and the stability and the reliability are greatly improved.

The first connecting seat 8 and the second connecting seat 9 both adopt 80-needle spring needle seats. The test motherboard 1 is characterized in that cover plates are arranged at intervals on the top of the test motherboard 1 and fixedly connected with the test motherboard 1 through bolts.

Through the arrangement, the test sub-board 2 is in contact fit with the spring needle seat, so that the test sub-board is not required to be welded in the test process, the time and the cost are saved, and the reliability is improved. The cover plate protects the test mother board 1, and devices and sundries are prevented from being left on the mother board to damage equipment and the devices.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The utility model provides a master-slave board test system of a plurality of station resources of set, includes the test mother board of level setting to and connect the setting and be in the test daughter board at test mother board top, its characterized in that:

the socket head is fixedly connected with the center of the top of the test mother board through pins, and the test daughter board is in adaptive connection with the top of the socket head through the bottom;

the direct current resource sockets are arranged in a plurality of ways and distributed on two sides of the socket head at intervals, and each direct current resource socket is fixedly connected with the test motherboard through pins;

the direct current resource socket is composed of a high-power resource FPVI socket and a low-power resource FOVI socket, the high-power resource FPVI socket is arranged on the left side of the test motherboard, and the low-power resource FOVI socket is arranged on the upper side of the test motherboard;

the alternating current resource socket is fixedly arranged between the left side of the socket head and the high-power resource FPVI socket through pins;

the relay group is fixedly arranged on the test motherboard through pins;

the seat head is composed of a first connecting seat and a second connecting seat which is arranged in parallel with the first connecting seat at intervals; the first connecting seat comprises a first pin area, a second pin area and a third pin area, and the second connecting seat comprises a fourth pin area, a fifth pin area and a sixth pin area; the second pin area and the fourth pin area are respectively electrically connected with the high-power resource FPVI socket through leads; the third pin area is electrically connected with the alternating current resource socket through a lead; the first pin area and the fifth pin area are electrically connected with the low-power resource FOVI socket through leads; the sixth pin area is electrically connected with the relay set through a lead;

and the bottom of the test daughter board is provided with a connecting contact corresponding to the socket head, and each connecting contact penetrates through the test daughter board and is electrically connected with the test part at the top.

2. The daughter board test system for aggregating multiple station resources of claim 1, wherein: the high-power resource FPVI socket is connected with the socket head through a full-floating connection method, 3 pins are used for FORCE, and one pin is used for SENSE; the low-power resource FOVI socket is connected with the socket head through a common ground connection method, positive FORCE and SENSE of each path are in short circuit at the socket head, negative FORCE of all channels is in short circuit with AGND, and all negative SENSE are in short circuit with DGS.

3. The daughter board test system for aggregating multiple station resources of claim 2, wherein: each resource in the alternating current resource socket is connected with two adjacent pins.

4. A daughter board test system according to claim 3, wherein: the relay group comprises 16 first relays and 4 second relays, wherein every four first relays are in one group, each first relay COM in the same group is in short circuit, and NC and NO are led out; COM, NC and NO are respectively led out of the second relay.

5. The daughter board test system for aggregating multiple station resources of claim 4, wherein: the first connecting seat and the second connecting seat are both 80-pin spring pin seats.

6. The daughter board test system for aggregating multiple station resources of claim 5, wherein: the top of the test motherboard is provided with cover plates at intervals, and the cover plates are fixedly connected with the test motherboard through bolts.