CN216313265U - Dual-storage CMOS image sensor circuit - Google Patents

Dual-storage CMOS image sensor circuit Download PDF

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CN216313265U
CN216313265U CN202122797985.3U CN202122797985U CN216313265U CN 216313265 U CN216313265 U CN 216313265U CN 202122797985 U CN202122797985 U CN 202122797985U CN 216313265 U CN216313265 U CN 216313265U
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circuit
transistor
reset
source follower
source
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郭亚炜
郭小林
惠志达
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Wuxi Bixing Semiconductor Co ltd
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Wuxi Bixing Semiconductor Co ltd
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Abstract

The utility model discloses a double-storage CMOS image sensor circuit, which relates to the field of image sensors and comprises a pixel circuit, a differential sampling circuit and a reading circuit which are sequentially connected, wherein the pixel circuit is used for acquiring a signal level and a reset level, and the differential sampling circuit is used for storing a voltage signal and a reset level signal and outputting the voltage signal and the reset level signal to a bus through the reading circuit; the reading circuit comprises two source followers and two selection switches, the grids of the first source follower and the second source follower are used as input ends of the reading circuit and are respectively connected with output ends of the differential sampling circuit, the first selection switch is arranged between a drain electrode of the first source follower and a first power supply, the second selection switch is arranged between a drain electrode of the second source follower and the first power supply, and source electrodes of the first source follower and the second source follower are respectively connected into a bus, so that one-time voltage drop on the reading circuit is avoided, and nonlinearity of the reading signal level of the reading circuit is remarkably reduced.

Description

Dual-storage CMOS image sensor circuit
Technical Field
The utility model relates to the field of image sensors, in particular to a double-storage CMOS image sensor circuit.
Background
The CMOS image sensor is divided into a rolling shutter (rolling shutter) and a global shutter (global shutter) according to different control modes of the electronic shutter. In order to obtain ultra-high speed images at speeds greater than 1000fps, a global shutter must be employed.
In a conventional global shutter CMOS image sensor readout circuit, a source follower is usually connected in series with a gate switch and then connected to a bus output. When a high readout speed is required, the bias current of the source follower is large, and the bias current thereof also needs to flow through a gate switch, which causes a non-negligible voltage drop on the channel of the gate switch, so that the signal level of the CMOS image sensor has severe nonlinearity when being output to the bus line via a source follower and the gate switch.
SUMMERY OF THE UTILITY MODEL
The present inventors have addressed the above-mentioned problems and needs in the art by providing a dual memory CMOS image sensor circuit. The severe non-linearity of the signal level readout is reduced due to the improved readout circuitry.
The technical scheme of the utility model is as follows:
a dual-storage CMOS image sensor circuit comprises a pixel circuit, a differential sampling circuit and a reading circuit which are sequentially connected, wherein the pixel circuit is used for acquiring a signal level and a reset level, and the differential sampling circuit is used for storing the signal level and the reset level and outputting the signal level and the reset level to a bus through the reading circuit;
the reading circuit comprises a first source follower, a second source follower, a first selection switch and a second selection switch, wherein the grid electrode of the first source follower is used as a first input end of the reading circuit, the grid electrode of the second source follower is used as a second input end of the reading circuit, the grid electrodes of the first source follower and the second source follower are respectively connected with the output end of the differential sampling circuit, the drain electrode of the first source follower is connected with the drain electrode of the first selection switch, the drain electrode of the second source follower is connected with the drain electrode of the second selection switch, the source electrodes of the first selection switch and the second selection switch are respectively connected with a first power supply, the source electrodes of the first source follower and the second source follower are respectively connected with a bus, and the grid electrodes of the first selection switch and the second selection switch are respectively connected with a controller.
The pixel circuit comprises a bundled photodiode, a transmission transistor, a reset transistor, a suspended diffusion area capacitor and a third source electrode follower; the anode of the photodiode is connected with a second power supply, the cathode of the photodiode is connected with the source electrode of the transmission transistor, the drain electrode of the transmission transistor is respectively connected with the source electrode of the reset transistor and the grid electrode of the third source follower, one end of a floating diffusion region capacitor is also connected between the source electrode of the reset transistor and the grid electrode of the third source follower, the other end of the floating diffusion region capacitor is grounded, the drain electrode of the reset transistor is connected with the third power supply, the drain electrode of the third source follower is connected with the first power supply, the source electrode of the third source follower is used as the output end of the pixel circuit and is connected with the input end of the differential sampling circuit, and the grid electrodes of the transmission transistor and the reset transistor are respectively connected with the controller;
when the reset transistor is conducted, the voltage of the floating diffusion region capacitor is reset, and the reset voltage is used as a reset level; when the transfer transistor is turned on, the charges accumulated in the photodiode are transferred to the floating diffusion region capacitor, and the voltage of the floating diffusion region capacitor is used as a signal level.
The pixel circuit further comprises a pixel reset transistor, wherein the source electrode of the pixel reset transistor is connected with the cathode of the photodiode, the drain electrode of the pixel reset transistor is connected with a fourth power supply, and the grid electrode of the pixel reset transistor is connected with the controller; when the pixel reset transistor is turned on, the voltage of the photodiode is reset.
The differential sampling circuit comprises a first sampling transistor, a second sampling transistor, a first storage capacitor and a second storage capacitor; the source electrodes of the first sampling transistor and the second sampling transistor are used as the input ends of the differential sampling circuit and are respectively connected with the output end of the pixel circuit, the drain electrode of the first sampling transistor is used as the first output end of the differential sampling circuit and is respectively connected with one end of the first storage capacitor and the first input end of the reading circuit, the drain electrode of the second sampling transistor is used as the second output end of the differential sampling circuit and is respectively connected with one end of the second storage capacitor and the second input end of the reading circuit, the other ends of the first storage capacitor and the second storage capacitor are grounded, and the grid electrodes of the first sampling transistor and the second sampling transistor are respectively connected with the controller;
when the first sampling transistor is conducted, the reset level output by the pixel circuit is stored in the first storage capacitor; when the second sampling transistor is conducted, the signal level output by the pixel circuit is stored in the second storage capacitor.
The further technical scheme is that the floating diffusion region capacitor is one or a combination of a MOS capacitor, an MIM capacitor and an inter-metal line interdigital capacitor.
The beneficial technical effects of the utility model are as follows:
the CMOS image sensor circuit with the two storage nodes supports a global shutter, and a selection switch of a source follower in a reading circuit is arranged between a drain electrode of the source follower and a power supply, so that one-time voltage drop on the reading circuit is avoided, and the nonlinearity of the reading signal level of the reading circuit is obviously reduced; a pixel reset transistor is arranged between the cathode of the photodiode and a power supply, the voltage of the photodiode is reset, residual electrons of the photodiode are removed completely, and the exposure time of the photodiode can be adjusted by changing the high-level pulse width of the pixel reset transistor through a controller.
Drawings
Fig. 1 is a circuit diagram of a dual-memory CMOS image sensor according to an embodiment of the present application.
Fig. 2 shows the level states of the transistors according to an embodiment of the present application.
Fig. 3 is a circuit diagram of a dual memory CMOS image sensor according to another embodiment of the present application.
Fig. 4 is a level state of each transistor provided in another embodiment of the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
In one embodiment, the dual-storage CMOS image sensor circuit includes a pixel circuit, a differential sampling circuit, and a readout circuit, which are connected in sequence, where the pixel circuit is configured to obtain a signal level and a reset level, and the differential sampling circuit is configured to store a voltage signal and a reset level signal, and output the voltage signal and the reset level signal to a bus through the readout circuit, and a specific circuit structure is as follows.
As shown in FIG. 1, the pixel circuit comprises a photodiode PPD and a transfer transistor MTXReset transistor MRSA floating diffusion region capacitor FD and a third source follower MSF. The anode of the photodiode PPD is connected with a second power supply VSUBCathode connected to pass transistor MTXSource of (2), pass transistor MTXAre respectively connected with a reset transistor MRSSource and third source follower MSFGate of (3), reset transistor MRSSource and third source follower MSFThe other end of the floating diffusion region capacitor FD is connected to the ground, and a reset transistor MRSIs connected to a third power supply Vpix, a third source follower MSFIs connected to a first power supply VDD, a third source follower MSFThe source electrode of the differential sampling circuit is used as the output end of the pixel circuit and is connected with the input end of the differential sampling circuit, and the transmission transistor MTXGate TG and reset transistor MRSAre connected to the controller respectively.
Optionally, the floating diffusion region capacitor is one or more of a MOS capacitor, an MIM capacitor, and an inter-metal line interdigital capacitor, and the actual situation is determined according to the corresponding semiconductor process characteristics.
The differential sampling circuit comprises a first sampling transistor S1A second sampling transistor S2A first storage capacitor C1And a second storage capacitor C2. A first sampling transistor S1And a second sampling transistor S2The source electrodes of the differential sampling circuit are respectively connected with the output end of the pixel circuit as the input end of the differential sampling circuit, namely connected with a third source electrode follower MSFA first sampling transistor S1The drain electrodes of the differential sampling circuit are used as first output ends of the differential sampling circuit and are respectively connected with a first storage capacitor C1And a first input terminal of the read-out circuit, a second sampling transistor S2The drain electrodes of the differential sampling circuit are used as second output ends of the differential sampling circuit and are respectively connected with the second output endsStorage capacitor C2And a second input terminal of the read-out circuit, a first storage capacitor C1And a second storage capacitor C2Are all grounded, a first sampling transistor S1And a second sampling transistor S2The gates SS of (1) are respectively connected to the controller.
The readout circuit includes a first source follower M1A second source follower M2A first selection switch N1And a second selection switch N2First source follower M1As a first input terminal of the read-out circuit, a second source follower M2As a second input terminal of the readout circuit, respectively connected to the output terminal of the differential sampling circuit, i.e. the first source follower M1Is connected to the first sampling transistor S1Of the second source follower M2Is connected to the second sampling transistor S2The first source follower M1Is connected with the first selection switch N1Of the second source follower M2Is connected with the second selection switch N2The first selection switch N1And a second selection switch N2The source electrodes of the first and second source electrode followers M are all connected with a first power supply VDD1Source access bus RBUS, second source follower M2The source electrode of the first selection switch N is connected to the bus SBUS1、N2The gates read _ n of (1) are respectively connected with the controller.
The working principle of the double-storage CMOS image sensor circuit is as follows:
in the correlated double sampling process, as shown in fig. 2, M is added before the end of each pixel integrationRSThe voltage of FD is reset at the time when the voltage of FD is equal to Vpix voltage and is taken as the reset level. After the RESET is finished (after the RESET signal changes from high to low), S is closed1Storing reset level of FD in C1In (1). At S1After disconnection, M isTXSet the TG terminal of the first transistor to a high level and set a proper conduction time to enable MTXOn, the charge accumulated by PPD (under the condition of illumination, the charge accumulated by PPD is electrons) passes through MTXIs totally produced fromAnd shifts to FD, where the voltage of FD serves as the signal level. Closed S2Storing the signal level of FD in C2In (1).
After the above actions are completed, C1And C2The upper stored voltage is respectively a reset value and a signal value, the related double sampling is completed, and the difference between the two values can eliminate MSFDetuning and flicker noise. Will N1、N2A low level pulse, C, is applied to the read _ n terminal1Voltage of (1) through M1Output to bus RBUS, C2Voltage of (1) through M2Output to bus SBUS. Due to the source follower M1、M2Selection switch N1、N2The voltage drop preventing circuit is arranged between the drain electrode of the source follower and a power supply VDD, one more voltage drop on a reading circuit is avoided, and nonlinearity of the reading signal level of the reading circuit is obviously reduced.
In order to improve the use effect of a photodiode in a pixel circuit, another embodiment is provided in the present application, in which a dual-storage CMOS image sensor circuit still includes a pixel circuit, a differential sampling circuit, and a readout circuit, which are connected in sequence, and the connection relationship of the other circuits is not changed, and the pixel circuit is mainly described below.
As shown in FIG. 3, the pixel circuit comprises a photodiode PPD and a transfer transistor MTXPixel reset transistor MPRReset transistor MRSA floating diffusion region capacitor FD and a third source follower MSF. The anode of the photodiode PPD is connected with a second power supply VSUBThe cathodes of the transistors are respectively connected with a transmission transistor MTXAnd a pixel reset transistor MPRSource electrode of (1), pixel reset transistor MPRIs connected to a fourth power supply Vpr, a pass transistor MTXAre respectively connected with a reset transistor MRSSource and third source follower MSFGate of (3), reset transistor MRSSource and third source follower MSFThe other end of the floating diffusion region capacitor FD is connected to the ground, and a reset transistor MRSIs connected to a third power supply Vpix, a third source follower MSFIs connected to a first power supply VDD and a third sourcePole follower MSFThe source electrode of the pixel circuit is used as the output end of the pixel circuit and is connected with the input end of the differential sampling circuit, and the pixel reset transistor MPRGate PR of the transfer transistor MTXGate TG and reset transistor MRSAre connected to the controller respectively.
Optionally, the floating diffusion region capacitor is one or more of a MOS capacitor, an MIM capacitor, and an inter-metal line interdigital capacitor, and the actual situation is determined according to the corresponding semiconductor process characteristics.
The working principle of the double-storage CMOS image sensor circuit is as follows:
in the correlated double sampling process, as shown in fig. 4, M is set before the end of each pixel integrationRSThe voltage of FD is reset at the time when the voltage of FD is equal to Vpix voltage and is taken as the reset level. After the RESET is finished (after the RESET signal changes from high to low), S is closed1Storing reset level of FD in C1In (1). At S1After disconnection, M isTXSet the TG terminal of the first transistor to a high level and set a proper conduction time to enable MTXOn, the charge accumulated by PPD (under the condition of illumination, the charge accumulated by PPD is electrons) passes through MTXAnd completely transferred to the FD with the voltage of the FD as the signal level. Closed S2Storing the signal level of FD in C2In (1).
At S2When closed, M is put inPRThe PR terminal of the PPD is changed to high level, the voltage of the PPD is reset, and residual electrons are removed. The level of the reset voltage is determined by Vpr, and Vpr and Vpix may be connected together. The exposure time of PPD can be adjusted by the controller changing the high level pulse width at the PR terminal.
After the above actions are completed, C1And C2The upper stored voltage is respectively a reset value and a signal value, the related double sampling is completed, and the difference between the two values can eliminate MSFDetuning and flicker noise. Will N1、N2A low level pulse, C, is applied to the read _ n terminal1Voltage of (1) through M1Output to bus RBUS, C2Voltage of (1) through M2Output to bus SBUS. Due to the source follower M1、M2Selection switch N1、N2The voltage drop preventing circuit is arranged between the drain electrode of the source follower and a power supply VDD, one more voltage drop on a reading circuit is avoided, and nonlinearity of the reading signal level of the reading circuit is obviously reduced.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (5)

1. A double-storage CMOS image sensor circuit is characterized by comprising a pixel circuit, a differential sampling circuit and a reading circuit which are sequentially connected, wherein the pixel circuit is used for acquiring a signal level and a reset level, and the differential sampling circuit is used for storing the signal level and the reset level and outputting the signal level and the reset level to a bus through the reading circuit;
the reading circuit comprises a first source follower, a second source follower, a first selection switch and a second selection switch, the grid of the first source follower is used as the first input end of the reading circuit, the grid of the second source follower is used as the second input end of the reading circuit, the grid of the first source follower is respectively connected with the output end of the differential sampling circuit, the drain of the first source follower is connected with the drain of the first selection switch, the drain of the second source follower is connected with the drain of the second selection switch, the sources of the first selection switch and the second selection switch are respectively connected with a first power supply, the sources of the first source follower and the second source follower are respectively connected into a bus, and the grids of the first selection switch and the second selection switch are respectively connected with a controller.
2. The dual-storage CMOS image sensor circuit of claim 1, wherein the pixel circuit comprises a photodiode, a transfer transistor, a reset transistor, a floating diffusion capacitance, and a third source follower; the anode of the photodiode is connected with a second power supply, the cathode of the photodiode is connected with the source electrode of the transmission transistor, the drain electrode of the transmission transistor is respectively connected with the source electrode of the reset transistor and the grid electrode of the third source electrode follower, one end of the floating diffusion region capacitor is also connected between the source electrode of the reset transistor and the grid electrode of the third source electrode follower, the other end of the floating diffusion region capacitor is grounded, the drain electrode of the reset transistor is connected with a third power supply, the drain electrode of the third source electrode follower is connected with a first power supply, the source electrode of the third source electrode follower is used as the output end of the pixel circuit and is connected with the input end of the differential sampling circuit, and the grid electrodes of the transmission transistor and the reset transistor are respectively connected with a controller;
when the reset transistor is conducted, the voltage of the floating diffusion region capacitor is reset, and the reset voltage is used as the reset level; when the transmission transistor is conducted, the charges accumulated by the photodiode are transferred to the floating diffusion region capacitor, and the voltage of the floating diffusion region capacitor is used as the signal level.
3. The dual-storage CMOS image sensor circuit of claim 2, wherein the pixel circuit further comprises a pixel reset transistor, wherein a source of the pixel reset transistor is connected to a cathode of the photodiode, a drain of the pixel reset transistor is connected to a fourth power supply, and a gate of the pixel reset transistor is connected to the controller; when the pixel reset transistor is conducted, the voltage of the photodiode is reset.
4. The dual-storage CMOS image sensor circuit of claim 1, wherein the differential sampling circuit comprises a first sampling transistor, a second sampling transistor, a first storage capacitor, and a second storage capacitor; the source electrodes of the first sampling transistor and the second sampling transistor are used as the input ends of the differential sampling circuit and are respectively connected with the output end of the pixel circuit, the drain electrode of the first sampling transistor is used as the first output end of the differential sampling circuit and is respectively connected with one end of the first storage capacitor and the first input end of the readout circuit, the drain electrode of the second sampling transistor is used as the second output end of the differential sampling circuit and is respectively connected with one end of the second storage capacitor and the second input end of the readout circuit, the other ends of the first storage capacitor and the second storage capacitor are grounded, and the grid electrodes of the first sampling transistor and the second sampling transistor are respectively connected with the controller;
when the first sampling transistor is conducted, the reset level output by the pixel circuit is stored in the first storage capacitor; when the second sampling transistor is conducted, the signal level output by the pixel circuit is stored in the second storage capacitor.
5. The dual-storage CMOS image sensor circuit of claim 2 or 3, wherein the floating diffusion region capacitance is one or more combination of MOS capacitance, MIM capacitance and inter-metal finger capacitance.
CN202122797985.3U 2021-11-15 2021-11-15 Dual-storage CMOS image sensor circuit Active CN216313265U (en)

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