CN216311775U - 封装测试用的集成电路载板构造 - Google Patents

封装测试用的集成电路载板构造 Download PDF

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CN216311775U
CN216311775U CN202122467705.2U CN202122467705U CN216311775U CN 216311775 U CN216311775 U CN 216311775U CN 202122467705 U CN202122467705 U CN 202122467705U CN 216311775 U CN216311775 U CN 216311775U
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施鸿贵
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Jingyun Technology Co ltd
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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Abstract

本实用新型关于一种封装测试用的集成电路载板构造，包含一基材层，为玻璃、石英、蓝宝石或陶瓷所制成；一介质层，结合于该基材层的表面；至少一绝缘层，结合于该介质层的表面，该绝缘层、该介质层及该基材层上分别钻穿有复数贯穿电性导通孔，所述各贯穿电性导通孔内连通形成有复数线路。借以使集成电路载板上可大面积加工，并制作出更多的线路，并于高温下不易变形，具有极佳的抗电磁波干扰及可提升散热效率。

Description

封装测试用的集成电路载板构造
技术领域
本实用新型有关于一种可以大面积加工，并制作出更多线路的晶圆封装测试用的集成电路载板。
背景技术
目前一般常见的晶圆于封装完成后，必须要再经过封装测试，以确保晶圆的合格率。进行晶圆的测试时，主要利用测试设备的晶圆探针卡的探针，刺入晶粒上的接点垫而构成电性接触，再将经由探针所测得的测试讯号送往自动测试设备做分析与判断，借此可取得晶圆上的每颗晶粒的电性特性测试结果。
晶圆的测试设备，如中国台湾2007年12月11日所公告的新型第M323619号「IC测试载板免焊接组装结构」专利案，其揭露：应用长金属凸块方式嵌入IC测试母板(Probe CardPCB)上，以凸块取代植锡球、回焊(reflow)的连接组装，其包括有：一IC探针卡；一金属凸块；一IC测试载板；一螺丝；一螺丝座；以及一弹簧。螺丝串过该螺丝座，配合该螺丝孔利用该螺丝将IC探针卡置于IC测试载板上。螺丝串过该弹簧，借由调整弹簧和螺丝的高度控制该IC测试载板的平坦度。
又有中国台湾2014年10月1日所公告的发明第I454710号「探针卡及其制造方法」专利案，其揭露：用以与复数个探针接抵；该探针卡包含有一基板、至少两个IC载板以及复数个探针垫；其中，该等IC载板设于该基板上，且间隔一预定距离；各IC载板上具有复数个导接点；该等探针垫分别镀设于该等IC载板上，且分别与各导接点连接，而遮蔽各导接点，并于各IC载板上围成一布针区；该等探针垫用以分别与各探针接抵。
惟上述该等专利前案的测试设备中，所使用的集成电路载板(Substrate)，又简称为IC载板，该IC载板主要功能为承载IC做为载体之用，并以IC基板内部线路连接芯片与印刷电路板(PCB)之间的讯号，主要为保护电路、固定线路与导热，在封装制程中的关键零件，占封装制程30~50％成本，随晶圆制程技术演进，对于晶圆布线密度、传输速率及讯号干扰等效能需求提高，使得IC基板需求逐渐增加。IC载板的基板类似于PCB的铜箔基板，主要材质可区分为硬质基板(含ABF)、柔性薄膜基板和共烧陶瓷基板三大种类。惟不论是硬质基板、柔性薄膜基板或共烧陶瓷基板，均会有尺寸大时不易加工，而且容易翘曲变形，抗电磁干扰性不佳，以及高温时散热不易等缺点，因此于使用上不尽理想。
实用新型内容
本实用新型为解决晶圆封装测试设备所使用的集成电路载板具有上述的缺点。故本实用新型提供一种封装测试用的集成电路载板构造，设有一基材层，为玻璃、石英、蓝宝石或陶瓷所制成；一介质层，结合于该基材层的表面；至少一绝缘层，结合于该介质层的表面，该绝缘层、该介质层及该基材层上分别钻穿有复数贯穿电性导通孔，所述各贯穿电性导通孔内连通形成有复数线路。
上述陶瓷为氧化铝或氮化铝的材质所制成。
上述基材层的厚度为0.4至1.2mm。
上述介质层的厚度为0.01至0.03μm。
上述介质层为钛或铜的材质所制成。
上述绝缘层为陶瓷材质所制成。
上述陶瓷材质为氧化铝或氮化铝的材质所制成。
上述绝缘层的数量为1层至6层之间。
上述绝缘层的厚度为0.1至0.3mm。
利用激光钻孔方式以形成所述各贯穿电性导通孔。
上述贯穿电性导通孔的孔径为0.025至0.15mm。
利用激光蚀刻或黄光蚀刻方式形成有所述各线路。
上述技术特征具有下列的优点：
1.利用基材为玻璃、石英、蓝宝石或陶瓷所制成，因此可以大面积加工，并制作出更多的线路，借以减少绝缘层的层数，以达到更佳的测试效率。
2.由于玻璃、石英、蓝宝石或陶瓷的热膨胀系数小，因此在高温下不易变形翘曲，而容易加工。
3.又玻璃、石英、蓝宝石或陶瓷制成的基材层具有极佳的抗电磁波干扰的特性。
4.配合绝缘层为陶瓷或氧化铝、氮化铝，故可以有效的提升散热的效率。
附图说明
图1为本实用新型实施例正面的立体外观图；
图2为本实用新型实施例背面的立体外观图；
图3为本实用新型实施例的组合剖视图；
图4为本实用新型实施例使用于打线封装BGA模式的示意图；
图5为本实用新型实施例使用于覆晶封装BGA模式的示意图；
图6为本实用新型实施例使用于打线封装QFN模式的示意图；
图7为本实用新型实施例使用于覆晶封装QFN模式的示意图。
符号说明：
1:集成电路载板
2:基材层
3:介质层
4:绝缘层
5:贯穿电性导通孔
6:线路
A:裸晶
B:封胶
C:打线
D:锡球
E:凸块
F:导电块。
具体实施方式
请参阅图1、图2及图3所示，本实用新型实施例的集成电路载板1包含有：基材层2、介质层3及至少一绝缘层4，其中：
基材层2，其为玻璃、石英、蓝宝石或陶瓷所制成，该陶瓷为氧化铝或氮化铝的材质所制成。该基材层2的厚度为0.4至1.2mm。
介质层3，其结合于该基材层2的表面。该介质层3为钛或铜的材质所制成。该介质层3的厚度为0.01至0.03μm。
至少一绝缘层4，其结合于该介质层3的表面，该绝缘层4通过该介质层3的帮助，使该绝缘层4可以与该基材层2达到异材结合的作用。该绝缘层4为陶瓷材质所制成，该陶瓷材质为氧化铝或氮化铝的材质所制成。该绝缘层4的数量包含有1层至6层之间。又该绝缘层4的厚度为0.1至0.3mm。又该绝缘层4可根据晶圆测试电路的不同，利用激光钻孔方式，于该绝缘层4、该介质层3及该基材层2上分别钻穿有复数贯穿电性导通孔5，所述各贯穿电性导通孔5的孔径为0.025至0.15mm。最后再利用激光蚀刻或黄光蚀刻的方式，借以于该贯穿电性导通孔5内连通形成有复数线路6。所述各线路6可导通于该基材层2及绝缘层4的两面。
本实用新型的集成电路载板1，于进行晶圆封装的测试时，可适合于各种不同的封装模式使用。如图4所示，为一种打线封装(Wire bonding)的BGA模式（Ball Grid Array，焊球阵列封装），其是于该集成电路载板1的其中一面结合有裸晶A，再利用封胶B予以完整包覆。再于该集成电路载板1与该裸晶A之间连接有打线C，又该集成电路载板1的另一面结合有锡球D做为引脚，如此，则可供做为晶圆的测试使用。
如图5所示，为一种覆晶封装(Flip Chip)的BGA模式，其是将裸晶A的连接点设有凸块E(bump)，然后将裸晶A翻转过来使凸块E与该集成电路载板1直接连结，再利用封胶B予以完整包覆，又该集成电路载板1的另一面结合有锡球D做为引脚。如此，同样可供做为晶圆的测试使用。
如图6所示，为一种打线封装(Wire bonding)的QFN模式（Quad Flat No-leadsPackage，方形扁平无引脚封装），其是于该集成电路载板1的其中一面结合有裸晶A，再利用封胶B予以完整包覆。再于该集成电路载板1与该裸晶A之间连接有打线C，又该集成电路载板1贯穿结合有导电块F做为引脚，如此，则可供做为晶圆的测试使用。
如图7所示，为一种覆晶封装(Flip Chip)的QFN模式，其是将裸晶A的连接点设有凸块E，然后将裸晶A翻转过来使凸块E与该集成电路载板1直接连结，再利用封胶B予以完整包覆，又该集成电路载板1贯穿结合有导电块F做为引脚。如此，同样可供做为晶圆的测试使用。
因此，本实用新型的基材层2为玻璃材质所制成，因此可以在较小的面积上，制作出更多的线路6，借以减少绝缘层4的层数，以能达到更佳的测试效率。由于玻璃的热膨胀系数小，因此在高温下不易变形翘曲，而容易加工。又玻璃制成的基材层2抗电磁波佳，不易被干扰。再配合绝缘层4为陶瓷材质或氧化铝、氮化铝，故可以有效的提升散热效率。
又印刷电路板(PCB)、玻璃、氮化铝及氧化铝等四种材质经测试，其介电常数于相同频率下，印刷电路板为4.2至4.4之间，玻璃则为6.17，氮化铝则为8.7，氧化铝则为9.5。因此本实用新型的基材层2及绝缘层4为玻璃材质或陶瓷材质所制成，因此本实用新型的集成电路载板1于长期使用下，则不易被烧毁或短路故障。
综合上述实施例的说明，当可充分了解本实用新型的操作、使用及本实用新型产生的功效，惟以上所述实施例仅为本实用新型的较佳实施例，当不能以此限定本实用新型实施的范围，即依本实用新型申请专利范围及创作说明内容所作简单的等效变化与修饰，皆属本实用新型涵盖的范围内。

Claims (12)

1.一种封装测试用的集成电路载板构造，其特征在于，包含有：
一基材层，为玻璃、石英、蓝宝石或陶瓷所制成；
一介质层，结合于该基材层的表面；
至少一绝缘层，结合于该介质层的表面，该绝缘层、该介质层及该基材层上分别钻穿有复数贯穿电性导通孔，所述各贯穿电性导通孔内连通形成有复数线路。
2.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述陶瓷为氧化铝或氮化铝的材质所制成。
3.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述基材层的厚度为0.4至1.2mm。
4.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述介质层的厚度为0.01至0.03μm。
5.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述介质层为钛或铜的材质所制成。
6.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述绝缘层为陶瓷材质所制成。
7.根据权利要求6所述的封装测试用的集成电路载板构造，其特征在于：所述陶瓷材质为氧化铝或氮化铝的材质所制成。
8.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述绝缘层的数量为1层至6层之间。
9.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述绝缘层的厚度为0.1至0.3mm。
10.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：利用激光钻孔方式以形成所述各贯穿电性导通孔。
11.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：所述各贯穿电性导通孔的孔径为0.025至0.15mm。
12.根据权利要求1所述的封装测试用的集成电路载板构造，其特征在于：利用激光蚀刻或黄光蚀刻方式形成有所述各线路。
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