CN216290860U - Reset circuit and application circuit of IMAX8 chip - Google Patents
Reset circuit and application circuit of IMAX8 chip Download PDFInfo
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- CN216290860U CN216290860U CN202122553453.5U CN202122553453U CN216290860U CN 216290860 U CN216290860 U CN 216290860U CN 202122553453 U CN202122553453 U CN 202122553453U CN 216290860 U CN216290860 U CN 216290860U
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Abstract
The utility model discloses a reset circuit and application. The reset circuit comprises an AND gate and an inverting branch, and the inverting branch is used for carrying out non-operation on an input signal; the reset output end of the power management integrated circuit PMIC is connected with the first input end of the AND gate; the reset output end of the controller MCU is connected with the second input end of the AND gate through the inverting branch; and the output end of the AND gate is connected with the reset end of the SOC integrated chip. The reset state of the SOC integrated chip is controlled through the MCU and the PMIC together, the MCU can monitor the working state of the SOC integrated chip according to specific application scenes and design requirements, and when the SOC integrated chip breaks down, the reset is controlled.
Description
Technical Field
The utility model relates to the field of integrated circuits, in particular to a reset circuit and an application circuit of an IMAX8 chip.
Background
With the rapid development of integrated circuits, the technical maturity of integrated chip SOC is gradually enhanced. The number of products in which the integrated chip SOC is applied to the vehicle is increasing, and the reset circuit is an important component of the SOC integrated chip.
The reset circuit is used for ensuring that the SOC and related peripheral equipment can be normally restored to an initial state under the condition of power-on or abnormity of the SOC, but in practical product application, the reset circuit carried by the system is reset according to only one signal, special requirements of products and some specific working environments are not considered, for example, the condition of comprehensively judging and determining whether to reset a plurality of signals is considered, and therefore the circuit needs to be improved and optimized.
Disclosure of Invention
The utility model aims to overcome the defect that a reset circuit carried by a system in the prior art is reset only according to one signal, and provides a reset circuit for controlling the reset state through an MCU and a PMIC together and an application circuit of an IMAX8 chip.
In order to realize the purpose of the utility model, the utility model provides the following technical scheme:
a reset circuit comprises an AND gate and an inverting branch, wherein the inverting branch is used for carrying out non-operation on an input signal; the reset output end of the power management integrated circuit PMIC is connected with the first input end of the AND gate; the reset output end of the controller MCU is connected with the second input end of the AND gate through the inverting branch; and the output end of the AND gate is connected with the reset end of the SOC integrated chip.
Preferably, the inverting branch comprises a first resistor, a second resistor, a third resistor and an NPN triode; the reset output end of the controller MCU is respectively connected with one end of a third resistor and the base electrode of the NPN triode through a second resistor; the other end of the third resistor is grounded; the collector of the NPN triode is respectively connected with the second input end of the AND gate and one end of the first resistor; the emitter of the NPN triode is grounded; the other end of the first resistor is connected with a power supply.
Preferably, the and gate has a model number of 74AUP1G08, and the fifth pin is connected to the power supply and one end of the first capacitor, respectively; the other end of the first capacitor is grounded; the third pin is grounded.
Preferably, the output end of the and gate is further connected with a reset end of an external starting device.
An application circuit of an IMAX8 chip is provided, wherein a reset circuit of the IMAX8 chip is the reset circuit.
Compared with the prior art, the utility model has the beneficial effects that: the reset state of the SOC integrated chip is controlled by the MCU and the PMIC together, the MCU can monitor the working state of the SOC integrated chip according to specific application scenes and design requirements, and when the SOC integrated chip breaks down, the reset is controlled.
Description of the drawings:
fig. 1 is a circuit diagram of a reset circuit of exemplary embodiment 1 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to test examples and specific embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
Example 1
As shown in fig. 1, the present embodiment provides a reset circuit, which includes an and gate and an inverting branch, where the inverting branch is used to perform a non-operation on an input signal; the reset output end of the power Management integrated circuit PMIC (Power Management IC) is connected with the first input end of the AND gate; the reset output end of the controller MCU is connected with the second input end of the AND gate through the inverting branch; and the output end of the AND gate is connected with the reset end of the SOC integrated chip.
A RESET signal output by a RESET output end of the power management integrated circuit PMIC is recorded as PMIC _ REST, and a RESET signal output by a RESET output end of the controller MCU is recorded as MCU _ RESET; and the signal output by the output end of the AND gate is recorded as EMMC _ FLASH _ RESET.
When PMIC _ REST is in high level and MCU _ RESET is in low level or suspended, the EMMC _ FLASH _ RESET signal output by the output end of the AND gate is in high level, and at the moment, the SOC integrated chip works normally; in other cases, namely, when PMIC _ REST is low or MCU _ RESET is high, the SOC integrated chip is in a RESET state. In the embodiment, the reset state of the SOC integrated chip is controlled by the MCU and the PMIC together, the MCU can monitor the operating state of the SOC integrated chip according to specific application scenarios and design requirements, and the reset is controlled when the SOC integrated chip fails (e.g., communication error, abnormal power-on, etc.).
Specifically, the inverting branch comprises a first resistor R1, a second resistor R2, a third resistor R3 and an NPN transistor Q1; the reset output end of the controller MCU is respectively connected with one end of a third resistor R3 and the base electrode of an NPN triode Q1 through a second resistor R2; the other end of the third resistor R3 is grounded; a collector of the NPN triode Q1 is connected to the second input terminal of the and gate and one end of the first resistor R1, respectively; the emitter of the NPN triode Q1 is grounded; the other end of the first resistor R1 is connected to a power supply. When the MCU _ RESET is at a high level, the NPN triode Q1 is in saturated conduction, and a signal input by the second input end of the AND gate is at a low level; when the MCU _ RESET is low or floating, the NPN transistor Q1 turns off, and the signal input from the second input terminal of the and gate is high. Because the high-low level signal output by the MCU is not necessarily matched with the high-low level signal of the and gate (the high level output by the MCU may damage the and gate), and the signal is unstable and susceptible to interference when the MCU is floating, the signal received at the input end of the and gate is stable by using the NPN transistor Q1, etc., thereby improving the stability of the reset operation.
Specifically, the and gate has a model number of 74AUP1G08, and the fifth pin is connected to a power supply and one end of a first capacitor C1; the other end of the first capacitor C1 is grounded; the third pin is grounded.
Specifically, the output end of the and gate is further connected with a reset end of the peripheral starting device. Meanwhile, the related peripheral starting equipment of the SOC integrated chip is controlled to reset, and the control efficiency is improved. Such as controlling the resetting of DRAM, TFT, and EMMC devices.
Example 2
An application circuit of an IMAX8 chip, wherein a reset circuit of the application circuit is the reset circuit of embodiment 1. Embodiment 1 the reset circuit described above is applied to an IMAX8 chip. The IMAX8 chip is an SOC integrated chip of NXP company and is widely used in the fields of automobiles, industry and the like.
The foregoing is merely a detailed description of specific embodiments of the utility model and is not intended to limit the utility model. Various alterations, modifications and improvements will occur to those skilled in the art without departing from the spirit and scope of the utility model.
Claims (5)
1. The reset circuit is characterized by comprising an AND gate and an inverting branch, wherein the inverting branch is used for carrying out non-operation on an input signal; the reset output end of the power management integrated circuit PMIC is connected with the first input end of the AND gate; the reset output end of the controller MCU is connected with the second input end of the AND gate through the inverting branch; and the output end of the AND gate is connected with the reset end of the SOC integrated chip.
2. The reset circuit of claim 1, wherein the inverting branch comprises a first resistor, a second resistor, a third resistor and an NPN transistor; the reset output end of the controller MCU is respectively connected with one end of a third resistor and the base electrode of the NPN triode through a second resistor; the other end of the third resistor is grounded; the collector of the NPN triode is respectively connected with the second input end of the AND gate and one end of the first resistor; the emitter of the NPN triode is grounded; the other end of the first resistor is connected with a power supply.
3. The reset circuit of claim 1, wherein the and gate has a model 74AUP1G08, and the fifth pin is connected to a power supply and one end of the first capacitor, respectively; the other end of the first capacitor is grounded; the third pin is grounded.
4. The reset circuit of claim 1, wherein the output of the and gate is further coupled to a reset terminal of a peripheral activation device.
5. An application circuit of an IMAX8 chip, wherein the reset circuit of the IMAX8 chip is the reset circuit of any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122553453.5U CN216290860U (en) | 2021-10-22 | 2021-10-22 | Reset circuit and application circuit of IMAX8 chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122553453.5U CN216290860U (en) | 2021-10-22 | 2021-10-22 | Reset circuit and application circuit of IMAX8 chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216290860U true CN216290860U (en) | 2022-04-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122553453.5U Active CN216290860U (en) | 2021-10-22 | 2021-10-22 | Reset circuit and application circuit of IMAX8 chip |
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| Country | Link |
|---|---|
| CN (1) | CN216290860U (en) |
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2021
- 2021-10-22 CN CN202122553453.5U patent/CN216290860U/en active Active
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Effective date of registration: 20231214 Address after: 401147 Building 5-1, No. 24 Changhui Road, Yuzui Town, Liangjiang New Area, Yubei District, Chongqing Patentee after: Chongqing Lilong Zhongbao Intelligent Technology Co.,Ltd. Address before: 404100 No.4 diance village, Jiangbei District, Chongqing Patentee before: Chongqing Lilong technology industry (Group) Co.,Ltd. |
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