CN216290715U - Semiconductor circuit having a plurality of transistors - Google Patents
Semiconductor circuit having a plurality of transistors Download PDFInfo
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- CN216290715U CN216290715U CN202122642177.XU CN202122642177U CN216290715U CN 216290715 U CN216290715 U CN 216290715U CN 202122642177 U CN202122642177 U CN 202122642177U CN 216290715 U CN216290715 U CN 216290715U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000003292 glue Substances 0.000 claims description 14
- 102100027206 CD2 antigen cytoplasmic tail-binding protein 2 Human genes 0.000 claims description 9
- 101100181929 Caenorhabditis elegans lin-3 gene Proteins 0.000 claims description 9
- 101000914505 Homo sapiens CD2 antigen cytoplasmic tail-binding protein 2 Proteins 0.000 claims description 9
- 101000922137 Homo sapiens Peripheral plasma membrane protein CASK Proteins 0.000 claims description 9
- 101000739160 Homo sapiens Secretoglobin family 3A member 1 Proteins 0.000 claims description 9
- 102100031166 Peripheral plasma membrane protein CASK Human genes 0.000 claims description 9
- 102100037268 Secretoglobin family 3A member 1 Human genes 0.000 claims description 9
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000011265 semifinished product Substances 0.000 description 16
- 238000001514 detection method Methods 0.000 description 10
- 239000000047 product Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000012360 testing method Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 238000010009 beating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000011895 specific detection Methods 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
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Abstract
The utility model discloses a semiconductor circuit which comprises a substrate and an inversion module, wherein the inversion module comprises a U-phase unit, a V-phase unit and a W-phase unit, the U-phase unit comprises a U-phase upper bridge arm and a U-phase lower bridge arm, the U-phase upper bridge arm comprises a first driving chip and a first insulated gate bipolar transistor, the first driving chip is electrically connected with the first insulated gate bipolar transistor, and the first driving chip is arranged on the surface of an E pole of the first insulated gate bipolar transistor in a fit manner; the U-phase lower bridge arm comprises a second driving chip and a second insulated gate bipolar transistor, the second driving chip is electrically connected with the second insulated gate bipolar transistor, the second driving chip is arranged on the surface of the E pole of the second insulated gate bipolar transistor in a fitting mode, and the V-phase unit and the W-phase unit are consistent with the U-phase unit in structure. The utility model is beneficial to reducing the volume of the semiconductor circuit.
Description
Technical Field
The utility model relates to the technical field of semiconductor circuits, in particular to a semiconductor circuit and a manufacturing method thereof.
Background
The semiconductor circuit is a power driving product combining power electronics and integrated circuit technology, integrates an intelligent control IC, high-power devices such as an insulated gate bipolar transistor, a MOSFET (metal-oxide-semiconductor field effect transistor), an FRD (fast recovery diode) and the like for power output and some resistance-capacitance elements, and the components are welded on an aluminum substrate through tin-based solder.
The conventional semiconductor circuit generally uses one driving chip to simultaneously drive the U-phase unit, the V-phase unit and the W-phase unit in the inverter module. However, in this driving method, the driving chip, the U-phase unit, the V-phase unit, and the W-phase unit are all mounted on the substrate, which results in a large volume of the conventional semiconductor circuit.
SUMMERY OF THE UTILITY MODEL
The present invention is directed to a semiconductor circuit to solve the problems set forth in the background art.
In order to achieve the above purpose, the semiconductor circuit provided by the utility model comprises a substrate and an inverter module arranged on the substrate, wherein the inverter module comprises a U-phase unit, a V-phase unit and a W-phase unit, the U-phase unit comprises a U-phase upper bridge arm and a U-phase lower bridge arm, the U-phase upper bridge arm comprises a first driving chip and a first insulated gate bipolar transistor, the first driving chip is electrically connected with the first insulated gate bipolar transistor, the first driving chip is arranged on the surface of an E pole of the first insulated gate bipolar transistor in an attaching manner, and the first insulated gate bipolar transistor is electrically connected; the U-phase lower bridge arm comprises a second driving chip and a second insulated gate bipolar transistor, the second driving chip is electrically connected with the second insulated gate bipolar transistor, the second driving chip is arranged on the surface of the E pole of the second insulated gate bipolar transistor in a fit mode, and the V-phase unit and the W-phase unit are consistent with the U-phase unit in structure.
Preferably, the first driving chip is provided with a first VCC pin, a HIN pin, a first GND pin, a VB pin, an HO pin and a VS pin, a G pole of the first insulated gate bipolar transistor is electrically connected with the HO pin, and an E pole of the first insulated gate bipolar transistor is electrically connected with the VS pin; the second driving chip is provided with a second VCC pin, a LIN pin, a second GND pin and an LO pin, the G pole of the second insulated gate bipolar transistor is electrically connected with the LO pin, and the C pole of the second insulated gate bipolar transistor is electrically connected with the E pole of the first insulated gate bipolar transistor.
Preferably, a plurality of pins are sequentially arranged on one side surface of the substrate, and the pins are respectively and electrically connected with the U-phase unit, the V-phase unit and the W-phase unit.
Preferably, the first driving chip is adhered to the surface of the E pole of the first insulated gate bipolar transistor through glue.
Preferably, the second driving chip is adhered to the surface of the E-pole of the second igbt through glue.
Preferably, the pins include a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, -a UVW pin, a LIN3 pin, a LIN2 pin, a LIN1 pin, a HIN3 pin, a HIN2 pin, a HIN1 pin, a VCC pin, and a GND pin, which are sequentially arranged, the P pin is electrically connected to a C electrode of the first igbt, the VB1 pin is electrically connected to a VB pin of the first driver chip, the U pin is electrically connected to an E electrode of the first igbt, the-UVW pin is electrically connected to an E electrode of the second igbt, the LIN1 pin is electrically connected to the LIN pin, the HIN1 pin is electrically connected to the HIN pin, the VCC pin is respectively connected to the first VCC pin and the second VCC circuit, and the GND pin is respectively connected to the first GND circuit and the second GND circuit, the V-phase unit is electrically connected with the P pin, the VB2 pin, the V pin, -the UVW pin, the LIN2 pin, the HIN2 pin, the VCC pin and the GND pin respectively, and the W-phase unit is electrically connected with the P pin, the VB3 pin, the W pin, -the UVW pin, the LIN3 pin, the HIN3 pin, the VCC pin and the GND pin respectively.
Preferably, the P pin, the VB1 pin, the U pin, the VB2 pin, the V pin, the VB3 pin and the W pin are all strong current pins, the-UVW pin, the LIN3 pin, the LIN2 pin, the LIN1 pin, the HIN3 pin, the HIN2 pin, the HIN1 pin, the VCC pin and the GND pin are weak current pins, and the W pin is spaced from the-UVW pin by a distance greater than or equal to 4 mm.
Preferably, the U-phase unit, the V-phase unit and the W-phase unit are sequentially arranged along the arrangement direction of the pins, the U-phase lower bridge arm is arranged close to the pins, and the U-phase upper bridge arm is positioned on one side of the U-phase lower bridge arm away from the pins.
According to the semiconductor circuit provided by the embodiment of the utility model, the first insulated gate bipolar transistor is driven by the first driving chip alone, the first driving chip is arranged on the surface of the E pole of the first insulated gate bipolar transistor in an attaching manner, the second insulated gate bipolar transistor is driven by the second driving chip alone, and the second driving chip is arranged on the surface of the E pole of the second insulated gate bipolar transistor in an attaching manner, so that the area occupied by the U-phase unit on the substrate is further reduced under the condition of controlling the output of the U-phase voltage.
Drawings
FIG. 1 is a schematic diagram of a semiconductor circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a portion of the semiconductor circuit shown in FIG. 1;
fig. 3 is a circuit diagram of the semiconductor circuit shown in fig. 1.
Description of the reference numerals
| Reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | |
110 | |
| 200 | Inversion module | 210 | |
| 211 | U-phase |
212 | U-phase lower bridge arm |
| 220 | V-phase unit | 230 | W-phase unit |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
It will also be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The semiconductor circuit provided by the utility model is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like together and is sealed and packaged on the outer surface, and is widely applied to the field of power electronics, such as the fields of frequency converters of driving motors, various inversion voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuit herein may be referred to by various other names, such as a Modular Intelligent Power System (MIPS), an Intelligent Power Module (IPM), or a hybrid integrated circuit, a Power semiconductor module, a Power module, and so on. In the following embodiments of the present invention, collectively referred to as a Modular Intelligent Power System (MIPS).
The utility model provides a modular intelligent power system, as shown in fig. 1 and 2, the modular intelligent power system comprises a substrate 100 and an inverter module 200 arranged on the substrate 100, the inverter module 200 comprises a U-phase unit 210, a V-phase unit 220 and a W-phase unit 230, the U-phase unit 210 comprises a U-phase upper bridge arm 211 and a U-phase lower bridge arm 212, the U-phase upper bridge arm 211 comprises a first driving chip U1 and a first insulated gate bipolar transistor IGBT1, the first driving chip U1 is electrically connected with the first insulated gate bipolar transistor IGBT1, and the first driving chip U1 is attached to and arranged on the surface of the E-pole of the first insulated gate bipolar transistor IGBT 1; the U-phase lower bridge arm 212 includes a second driving chip U2 and a second insulated gate bipolar transistor IGBT2, the second driving chip U2 is electrically connected to the second insulated gate bipolar transistor IGBT2, the second driving chip U2 is attached to and arranged on the surface of the E-pole of the second insulated gate bipolar transistor IGBT2, and the V-phase unit 220 and the W-phase unit 230 are consistent in structure with the U-phase unit 210.
Since the U-phase unit 210, the V-phase unit 220, and the W-phase unit 230 have the same structure, the U-phase unit 210 is specifically described, and the V-phase unit 220 and the W-phase unit 230 may be arranged with reference to the U-phase unit 210. Specifically, the first driving chip U1 and the second driving chip U2 adopt single-channel chips, that is, the first driving chip U1 drives the first insulated gate bipolar transistor IGBT1 alone, and the second driving chip U2 drives the second insulated gate bipolar transistor IGBT2 alone to control the U-phase voltage. Meanwhile, the first driving chip U1 is adhered to the surface of the E electrode of the first insulated gate bipolar transistor IGBT1 by glue, and the second driving chip U2 is adhered to the surface of the E electrode of the second insulated gate bipolar transistor IGBT2 by glue, so that the first driving chip U1 and the second driving chip U2 are fixed conveniently, and the first driving chip U1 and the second driving chip U2 are prevented from moving in the subsequent manufacturing process. In this embodiment, the first driver chip U1 is used to separately drive the first IGBT1, the first driver chip U1 is attached to and disposed on the surface of the E-pole of the first IGBT1, the second driver chip U2 is used to separately drive the second IGBT2, and the second driver chip U2 is attached to and disposed on the surface of the E-pole of the second IGBT2, so that the area occupied by the U-phase unit 210 on the substrate 100 is further reduced under the condition of controlling the output of the U-phase voltage, and the V-phase unit 220 and the W-phase unit 230 are structurally identical to the U-phase unit 210, which is beneficial to reducing the area occupied by the inverter module 200 on the substrate 100, thereby reducing the volume of the modular intelligent power system.
In a preferred embodiment, as shown in fig. 3, it is preferable that the first driving chip U1 has a first VCC pin, a HIN pin, a first GND pin, a VB pin, a HO pin and a VS pin, the G pole of the first IGBT1 is electrically connected to the HO pin, and the E pole of the first IGBT1 is electrically connected to the VS pin; the second driver chip U2 has a second VCC pin, a LIN pin, a second GND pin, and an LO pin, the G-pole of the second IGBT2 is electrically connected to the LO pin, and the C-pole of the second IGBT2 is electrically connected to the E-pole of the first IGBT 1. In this embodiment, the first driving chip U1 is electrically connected to the first IGBT1 in the above manner, and the second driving chip U2 is electrically connected to the second IGBT2 in the above manner, so that the output of the U-phase voltage is controlled.
In a preferred embodiment, as shown in fig. 1, a plurality of pins 110 are preferably arranged on one side of the substrate 100 in sequence, and the plurality of pins 110 are electrically connected to the U-phase unit 210, the V-phase unit 220, and the W-phase unit 230, respectively. The number of the pins 110 can be set according to actual conditions, and if a temperature control module is required to be added, the pins 110 are correspondingly added. At this time, it is preferable to separately arrange the strong current pin and the weak current pin in the pin 110, such as arranging the weak current pin at one end and the strong current pin at the other end. In this embodiment, compared with the existing method of designing the strong current pin on one side of the substrate 100 and the weak current pin on the other side of the substrate 100, however, since the pins are designed on both sides, no matter from the etching process or the stamping process, the processing of the pins needs the material forming of a larger area, the cost of the separation scheme is relatively high, the material is wasted, and the environmental pollution is caused, and in the scheme, the pins 110 are arranged on the same side of the substrate 100, and the strong current pin and the weak current pin in the pins 110 are separately arranged, so that the simplification of the module circuit and the miniaturization of the module volume are realized, the strong current and the weak current of the pins 110 are separated, the interference is reduced, the EMI performance is improved, and the design of the peripheral circuit is facilitated.
In a preferred embodiment, as shown in fig. 1 and 3, preferably, the plurality of pins 110 include a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, -a UVW pin, an LIN3 pin, an LIN2 pin, an LIN1 pin, an HIN3 pin, an HIN2 pin, an HIN1 pin, a VCC pin, and a GND pin, which are sequentially arranged, the P pin is electrically connected to a C electrode of the first IGBT1, the VB1 pin is electrically connected to a VB pin of the first driver chip U1, the U pin is electrically connected to an E electrode of the first IGBT1, the W pin is electrically connected to an E electrode of the second IGBT2, the LIN1 pin is electrically connected to the LIN pin, the HIN1 pin is electrically connected to the HIN pin, the pin is respectively connected to a first VCC pin and a second VCC pin, the pin is respectively connected to a first VCC circuit, the first GND circuit pin and a second GND circuit, and the V-phase unit 220 is respectively connected to the P pin and the GND circuit 220 The VB2 pin, the V pin, -the UVW pin, the LIN2 pin, the HIN2 pin, the VCC pin, and the GND pin are electrically connected, and the W-phase unit 230 is electrically connected to the P pin, the VB3 pin, the W pin, -the UVW pin, the LIN3 pin, the HIN3 pin, the VCC pin, and the GND pin, respectively. The pin P, the pin VB1, the pin U, the pin VB2, the pin V, the pin VB3 and the pin W are all strong current pins, and the pin UVW, the pin LIN3, the pin LIN2, the pin LIN1, the pin HIN3, the pin HIN2, the pin HIN1, the pin VCC and the pin GND are weak current pins. At this time, the pins 110 are preferably arranged in sequence from left to right, and the W pin is preferably spaced from the UVW pin by a distance equal to 4mm, so as to satisfy creepage performance.
In a preferred embodiment, as shown in fig. 1 and fig. 2, U-phase unit 210, V-phase unit 220, and W-phase unit 230 are sequentially arranged along the arrangement direction of pin 110, U-phase lower arm 212 is arranged close to pin 110, and U-phase upper arm 211 is located on a side of U-phase lower arm 212 away from pin 110. Here, the upper and lower arms of the V-phase unit 220 and the W-phase unit 230 are also arranged with reference to the U-phase unit 210 so as to electrically connect the respective elements by a jumper wire or an etched circuit on the substrate 100.
In this embodiment, the modular smart power system may be manufactured specifically according to the following steps:
step one, the substrate is placed in a cleaning device for cleaning.
And secondly, placing the cleaned substrate on a solder paste printer to print solder paste to form a first semi-finished product.
Step three, placing the first semi-finished product in first DA equipment, and attaching the insulated gate bipolar transistor and the pins to the substrate to form a second semi-finished product;
placing the second semi-finished product on glue dispensing equipment, and coating glue on the surface of an E pole of the insulated gate bipolar transistor to form a third semi-finished product;
placing the third semi-finished product in second DA equipment, and adhering a driving chip on the surface of an E electrode of the insulated gate bipolar transistor to form a fourth semi-finished product;
sixthly, placing the fourth semi-finished product in reflow soldering equipment, and soldering the insulated gate bipolar transistor and the pins on the substrate to form a fifth semi-finished product;
step seven, placing the fifth semi-finished product on first detection equipment for first detection;
placing the fifth semi-finished product after the first detection on a wire bonding machine for wire bonding to form a sixth semi-finished product;
step nine, placing the sixth semi-finished product on second detection equipment for second detection;
step ten, placing the sixth semi-finished product after the second detection in packaging equipment for packaging to form a seventh semi-finished product;
and step eleven, placing the seventh semi-finished product in a curing device for curing to form a finished product.
In this embodiment, can be the production that utilizes the form of production line to accomplish modularization intelligent power system automatically, like cleaning equipment, solder paste printing machine, first DA equipment, some adhesive equipment, second DA equipment, reflow soldering equipment, first check out test set, wire bonder, second check out test set, encapsulation equipment and the solidification equipment of butt joint in proper order to only need can control the base plate after placing the base plate that cuts in cleaning equipment and flow in proper order in above-mentioned equipment, in order to accomplish each process steps automatically. The cleaning equipment preferably adopts an ultrasonic cleaning mode, and the solder paste printer coats solder paste on a specific position of the substrate according to a design drawing; then, placing each element at a position correspondingly coated with the solder paste by using first DA equipment, wherein the element can be only an insulated gate bipolar transistor and a pin, and can also be used for mounting a bootstrap capacitor, a sampling resistor and the like according to an actual design drawing; then, the substrate with the attached element is placed on dispensing equipment, glue is automatically coated on the surfaces of E electrodes of the six insulated gate bipolar transistors through a dispensing machine, the type of the glue can be selected according to the characteristics of the driving chip, if the drive chip needs to be electrically conducted, silver glue is adopted, and if the drive chip does not need to be electrically conducted, red glue is adopted; then, automatically placing the six driving chips on the corresponding insulated gate bipolar transistors respectively by using second DA equipment, so that the driving chips are adhered to the insulated gate bipolar transistors; then, elements such as the insulated gate bipolar transistor, the pin and the like are welded by reflow soldering equipment, and the glue solidification can be accelerated by the high temperature in the reflow soldering, so that the glue solidification time can be shortened conveniently; then, detecting by using first detection equipment, wherein the specific detection mode can be an AOI (automated optical inspection) detection mode so as to obtain whether the substrate is subjected to missing pasting or wrong pasting; then, carrying out jumper connection operation on each element by using a wire bonder according to a design drawing, specifically, preferably finishing the fine jumper and the thick jumper twice, namely respectively carrying out jumper connection by using two wire bonders; then, carrying out secondary detection by using second detection equipment to obtain the conditions of missed beating and mistaken beating of the jumper; and then packaging by using packaging equipment, and finally curing the packaging material of the curing equipment to obtain a finished product. Compared with the existing technical scheme, the method has the main difference that the steps of gluing and secondary mounting are added, and the rest steps can be set according to the existing scheme.
In a preferred embodiment, after the step eleven, the method further comprises the following steps:
and step twelve, placing the finished product on laser equipment for recording information. In this embodiment, the information can be recorded in a manner of recording a number or two-dimensional code and other information corresponding to the product.
In a preferred embodiment, after the step eleven, the method further comprises the following steps:
and step thirteen, placing the finished product on the testing equipment for parameter confirmation. In this embodiment, the test mode of the finished product may be to test whether the output voltage parameter and the signal parameter of the product are correct through the test equipment, so as to determine whether the product is a qualified product.
The above is only a part or preferred embodiment of the present invention, and neither the text nor the drawings should limit the scope of the present invention, and all equivalent structural changes made by the present specification and the contents of the drawings or the related technical fields directly/indirectly using the present specification and the drawings are included in the scope of the present invention.
Claims (8)
1. A semiconductor circuit is characterized by comprising a substrate and an inverter module arranged on the substrate, wherein the inverter module comprises a U-phase unit, a V-phase unit and a W-phase unit, the U-phase unit comprises a U-phase upper bridge arm and a U-phase lower bridge arm, the U-phase upper bridge arm comprises a first driving chip and a first insulated gate bipolar transistor, the first driving chip is electrically connected with the first insulated gate bipolar transistor, the first driving chip is arranged on the surface of an E pole of the first insulated gate bipolar transistor in a fit manner, and the first insulated gate bipolar transistor is electrically connected; the U-phase lower bridge arm comprises a second driving chip and a second insulated gate bipolar transistor, the second driving chip is electrically connected with the second insulated gate bipolar transistor, the second driving chip is arranged on the surface of the E pole of the second insulated gate bipolar transistor in a fit mode, and the V-phase unit and the W-phase unit are consistent with the U-phase unit in structure.
2. The semiconductor circuit according to claim 1, wherein the first driver chip has a first VCC pin, a HIN pin, a first GND pin, a VB pin, an HO pin, and a VS pin thereon, the G-pole of the first igbt is electrically connected to the HO pin, and the E-pole of the first igbt is electrically connected to the VS pin; the second driving chip is provided with a second VCC pin, a LIN pin, a second GND pin and an LO pin, the G pole of the second insulated gate bipolar transistor is electrically connected with the LO pin, and the C pole of the second insulated gate bipolar transistor is electrically connected with the E pole of the first insulated gate bipolar transistor.
3. The semiconductor circuit according to claim 2, wherein a plurality of pins are arranged in sequence on one side of the substrate, and the plurality of pins are electrically connected to the U-phase unit, the V-phase unit, and the W-phase unit, respectively.
4. The semiconductor circuit according to claim 1, wherein the first driver chip is attached to an E-pole surface of the first igbt by glue.
5. The semiconductor circuit according to claim 1, wherein the second driver chip is attached to an E-pole surface of the second igbt by glue.
6. The semiconductor circuit according to claim 3, wherein the plurality of pins include a P pin, a VB1 pin, a U pin, a VB2 pin, a V pin, a VB3 pin, a W pin, -a UVW pin, an LIN3 pin, an LIN2 pin, an LIN1 pin, an HIN3 pin, an HIN2 pin, an HIN1 pin, a VCC pin and a GND pin, the P pin is electrically connected with a C electrode of the first IGBT, the VB1 pin is electrically connected with a VB pin of the first driver chip, the U pin is electrically connected with an E electrode of the first IGBT, the-UVW pin is electrically connected with an E electrode of the second IGBT, the LIN1 pin is electrically connected with the LIN pin, the HIN1 pin is electrically connected with the HIN pin, and the VCC pins are respectively electrically connected with the first VCC pin and the second VCC pin, the GND pin is respectively in circuit connection with the first GND pin and the second GND pin, the V-phase unit is respectively in electric connection with the P pin, the VB2 pin, the V pin, -the UVW pin, the LIN2 pin, the HIN2 pin, the VCC pin and the GND pin, and the W-phase unit is respectively in electric connection with the P pin, the VB3 pin, the W pin, -the UVW pin, the LIN3 pin, the HIN3 pin, the VCC pin and the GND pin.
7. The semiconductor circuit according to claim 6, wherein the P pin, the VB1 pin, the U pin, the VB2 pin, the V pin, the VB3 pin and the W pin are all strong current pins, the-UVW pin, the LIN3 pin, the LIN2 pin, the LIN1 pin, the HIN3 pin, the HIN2 pin, the HIN1 pin, the VCC pin and the GND pin are weak current pins, and the W pin is spaced from the-UVW pin by a distance of 4mm or more.
8. The semiconductor circuit according to claim 3, wherein the U-phase unit, the V-phase unit and the W-phase unit are sequentially arranged along an arrangement direction of the pins, the U-phase lower bridge arm is arranged close to the pins, and the U-phase upper bridge arm is arranged on a side of the U-phase lower bridge arm away from the pins.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122642177.XU CN216290715U (en) | 2021-10-29 | 2021-10-29 | Semiconductor circuit having a plurality of transistors |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122642177.XU CN216290715U (en) | 2021-10-29 | 2021-10-29 | Semiconductor circuit having a plurality of transistors |
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| CN216290715U true CN216290715U (en) | 2022-04-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114121911A (en) * | 2021-10-29 | 2022-03-01 | 广东汇芯半导体有限公司 | Semiconductor circuit and method for manufacturing the same |
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- 2021-10-29 CN CN202122642177.XU patent/CN216290715U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114121911A (en) * | 2021-10-29 | 2022-03-01 | 广东汇芯半导体有限公司 | Semiconductor circuit and method for manufacturing the same |
| CN114121911B (en) * | 2021-10-29 | 2024-07-30 | 广东汇芯半导体有限公司 | Semiconductor circuit and method for manufacturing the same |
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