CN216285573U - Chip testing device, testing head and chip testing system - Google Patents

Abstract

The application relates to a chip testing device, a testing head and a chip testing system, wherein the chip testing device comprises a control module, an output module and an input module; the control module is respectively electrically connected with the output module and the input module and is used for carrying out test operation and/or burning operation on the chip to be tested; the input module comprises a first interface chip, the first interface chip comprises a first physical interface and a first output port, the first physical interface is electrically connected with an external terminal or an external power supply, and the first output port is electrically connected with the control module; the first interface chip is used for supplying power to the control module when the first physical interface is electrically connected with an external power supply, and transmitting data transmitted by the external terminal to the control module when the first physical interface is electrically connected with the external terminal. Through the application, the problem that the chip testing device cannot give consideration to both power supply and data transmission functions in the related technology is solved, and the technical effect that the chip testing device can give consideration to both the power supply and the data transmission functions is achieved.

Description

Chip testing device, testing head and chip testing system

Technical Field

The embodiment of the application relates to the technical field of chip testing, in particular to a chip testing device, a testing head and a chip testing system.

Background

The consumable chip is a chip which is arranged on a printing consumable and used for storing information related to the printing consumable, such as information of consumable model, production date, residual amount, printing number of pages and the like, and the read-write treatment of the consumable chip before leaving factory is an important treatment link for ensuring the quality of the chip.

At present, before or after a consumable chip or a regenerative chip of a printer is mounted on a finished product, a chip read-write processing device needs to be in butt joint with the chip for burning and testing. The chip read-write processing device in the related art often comprises a power interface and a USB interface, wherein the power interface is used for supplying power to the chip read-write processing device and supporting the chip read-write processing device to burn and test a chip; the USB interface is used for data transmission and is used for transmitting data transmitted by an external terminal to the chip read-write processing device.

However, in such schemes, the chip read/write processing device often can only solve the power supply problem or the data transmission problem in a single way, and the single use of one interface cannot achieve both the power supply function and the data transmission function.

At present, no effective solution is provided for the problem that the chip testing device in the related technology cannot give consideration to both the power supply and the data transmission function.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a chip testing device, which is used for at least solving the problem that the chip testing device in the related technology can not give consideration to both power supply and data transmission functions.

In a first aspect, an embodiment of the present application provides a chip testing apparatus, which is applied to testing and/or burning a chip, and includes a control module, an output module, and an input module; the control module is respectively electrically connected with the output module and the input module and is used for carrying out test operation and/or burning operation on the chip to be tested when the output module is detected to be connected with the chip to be tested; the input module comprises a first interface chip, wherein the first interface chip comprises a first physical interface and a first output port, the first physical interface is electrically connected with an external terminal or an external power supply, and the first output port is electrically connected with the control module; the first interface chip is used for supplying power to the control module when the first physical interface is electrically connected with the external power supply, and transmitting data transmitted by the external terminal to the control module when the first physical interface is electrically connected with the external terminal.

In some embodiments, the output module includes a second interface chip, an input port of the second interface chip is electrically connected to one end of an external test head, and the other end of the external test head is electrically connected to the chip to be tested.

In some embodiments, the input port of the second interface chip comprises a first TYPE-C interface, and one end of the external test head comprises a second TYPE-C interface; wherein, first TYPE-C interface with second TYPE-C interface passes through TYPE-C2C data line electrical connection.

In some embodiments, the first physical interface comprises a data transmission terminal electrically connected with an external terminal and a power supply terminal electrically connected with an external terminal or an external power supply; the first interface chip is used for supplying power to the control module when the power supply terminal is electrically connected with the external power supply or the external terminal, and transmitting data transmitted by the external terminal to the control module when the data transmission terminal is electrically connected with the external terminal.

In some of these embodiments, the first physical interface comprises a third TYPE-C interface.

In some embodiments, the first interface chip is further configured to send a first control signal to the control module when detecting that both the CC1 pin and the CC2 pin in the first interface chip are low; the control module is further used for carrying out test operation on the chip to be tested under the condition of receiving the first control signal.

In some embodiments, the first interface chip is further configured to send a second control signal to the control module when detecting that both the CC1 pin and the CC2 pin in the first interface chip are at a high level; and the control module is also used for carrying out burning operation on the chip to be tested according to the data transmitted by the external terminal under the condition of receiving the second control signal.

In a second aspect, an embodiment of the present application provides a test head, which is applied to the chip testing apparatus as described in the first aspect above, one end of the test head includes a second TYPE-C interface, one end of the test head is electrically connected to the chip testing apparatus, and the other end of the test head is electrically connected to a chip to be tested.

In some embodiments, the other end of the test head includes a plurality of probes, and the chip testing apparatus is configured to perform a testing operation and/or a burning operation on the chip to be tested after detecting that the probes contact the code writing and reading contacts of the chip to be tested.

In a third aspect, embodiments of the present application provide a chip testing system, which includes the chip testing apparatus according to the first aspect, and the testing head according to the second aspect.

Compared with the related art, the chip testing device provided by the embodiment of the application can supply power to the control module through the first output port when the first physical interface of the input module is connected with the external power supply, so that the chip testing device is supported to test the chip to be tested; when the first physical interface of the input module is connected with the external terminal, the data transmitted by the external terminal can be transmitted to the control module through the first output port, and meanwhile, after the external terminal stops transmitting the data, the chip testing device can be supported to test the chip to be tested, so that the problem that the chip testing device cannot give consideration to both power supply and data transmission functions in the related technology is solved, and the technical effect of ensuring that the chip testing device can give consideration to both the power supply and data transmission functions is realized.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of other features, objects, and advantages of the embodiments of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the embodiments of the application and are not intended to limit the embodiments of the application in any way. In the drawings:

FIG. 1 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of an input module of a chip testing apparatus according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of an output module of the chip testing apparatus according to the embodiment of the present application;

FIG. 4 is a schematic diagram of a test head according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a chip test system according to an embodiment of the present application.

Reference numerals: 10. a housing; 20. a control module; 30. an output module; 40. an input module; 41. a first physical interface; 42. a data transmission terminal; 43. a power supply terminal; 44. a first output port; 50. a chip to be tested; 60. an external terminal; 70. an external power supply; 80. a test head; 81. one end of the test head; 82. the other end of the test head; 90. a chip testing device.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more clearly understood, the embodiments of the present application are described and illustrated below with reference to the accompanying drawings and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of the application and are not intended to limit the embodiments of the application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments provided in the present application without any creative effort belong to the protection scope of the embodiments of the present application.

It should be apparent that the drawings in the following description are only examples or embodiments of the present application, and it is obvious for a person skilled in the art that the embodiments of the present application can be applied to other similar scenarios according to the drawings without inventive effort. Moreover, it should be further appreciated that such a development effort might be complex and tedious, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure, and it should be understood that the present disclosure is not limited to the particular embodiments described herein.

Reference in the embodiments of the present application to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the embodiments of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one of ordinary skill in the art that the embodiments described in the embodiments of this application can be combined with other embodiments without conflict.

Unless otherwise defined, technical or scientific terms referred to in the embodiments of the present application shall have the ordinary meaning as understood by those having ordinary skill in the art to which the embodiments of the present application belong. Reference to "a," "an," "the," and similar terms in the embodiments of the application are not intended to be limiting, but may refer to the singular or the plural. Reference to the terms "comprise," "include," "have" and any variations thereof in the embodiments of the present application, are intended to cover non-exclusive inclusions; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or elements, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in connection with embodiments of the present application is not intended to be limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The embodiments of the present application refer to "a plurality" or "a plurality". "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. Reference to the terms "first," "second," "third," and the like in the embodiments of the application are merely used to distinguish similar objects and do not denote a particular ordering for the objects.

The embodiment provides a chip testing device, which is applied to testing and/or burning a chip, wherein the testing of the chip includes but is not limited to at least one of the following: compatible code writing, compatible detection, regeneration reset, regeneration detection, chip data upgrading and the like. Fig. 1 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present application, and as shown in fig. 1, the chip testing apparatus includes: a control module 20, an output module 30, and an input module 40; the control module 20 is electrically connected to the output module 30 and the input module 40, respectively, and is configured to perform a test operation and/or a burning operation on the chip 50 to be tested when it is detected that the output module 30 is connected to the chip 50 to be tested; the input module 40 includes a first interface chip, where the first interface chip includes a first physical interface 41 and a first output port 44, the first physical interface 41 is electrically connected to the external terminal 60 or the external power source 70, the first output port 44 is electrically connected to the control module 20, and the first interface chip is configured to supply power to the control module 20 when the first physical interface 41 is electrically connected to the external power source 70, and transmit data transmitted by the external terminal 60 to the control module 20 when the first physical interface 41 is electrically connected to the external terminal 60.

In this embodiment, the control module 20, the output module 30 and the input module 40 are disposed in the housing 10 of the chip testing apparatus, the chip 50 to be tested may include a consumable chip and a regeneration chip of a printer, and when the first physical interface 41 of the input module 40 is connected to the external power supply 70 through the first interface chip, the control module 20 can be powered through the first output port 44, so as to support the chip testing apparatus to perform a testing operation on the chip 50 to be tested; when the first physical interface 41 of the input module 40 is connected to the external terminal 60, the data transmitted by the external terminal 60 can be transmitted to the control module 20 through the first output port 44, and after the external terminal 60 stops transmitting the data, the power supply provided by the external terminal 60 can be used for supplying power to the control module 20, thereby supporting the chip testing device to perform the testing operation on the chip 50 to be tested.

In the above embodiment, the external terminal 60 may include a Personal Computer (PC), a tablet PC or other mobile terminal devices, the external power source 70 may include an externally provided power source, a mobile power source, or a mobile device such as a mobile phone for power output, and the power output is performed through the Personal Computer, that is, when the input module 40 is connected to the external terminal 60, the external terminal 60 (PC, mobile phone, etc.) may obtain transmitted data or power from the external terminal 60.

The chip testing device in the related art often includes a power supply interface and a USB interface, where the power supply interface is used to connect an external power supply to supply power to the chip testing device, and the USB interface is used to connect an external terminal to enter a data transmission mode. In such a technical solution, two types of data lines with different functions are often used, for example, a power line is used to connect with an external power supply, the chip testing device is supported to perform a testing operation on a chip to be tested, a USB data line is used to connect with an external terminal, and the external terminal transmits data to the chip testing device. Meanwhile, when the USB data line is used independently, the test mode of the chip test device cannot be entered.

Through the above embodiments, in the chip testing apparatus provided in this embodiment, when detecting that the output module 30 is connected to the chip 50 to be tested, the control module 20 performs a testing operation and/or a burning operation on the chip 50 to be tested, the first physical interface 41 in the first interface chip is electrically connected to the external terminal 60 or the external power supply 70, the first output port 44 in the first interface chip is electrically connected to the control module 20, and when the first physical interface 41 of the input module 40 is connected to the external power supply 70, the control module 20 can be powered through the first output port 44, so as to support the chip testing apparatus to perform a testing operation on the chip 50 to be tested; when the first physical interface 41 of the input module 40 is connected to the external terminal 60, the data transmitted by the external terminal 60 can be transmitted to the control module 20 through the first output port 44, which solves the problem that the chip testing device in the related art cannot give consideration to both the power supply function and the data transmission function, and achieves the technical effect of ensuring that the chip testing device can give consideration to both the power supply function and the data transmission function.

The present application is described and illustrated below by means of preferred embodiments.

Fig. 2 is a schematic structural diagram of an input module 40 of a chip testing apparatus according to an embodiment of the present application, and as shown in fig. 2, in some embodiments, the first physical interface 41 includes a third TYPE-C interface, and the first physical interface 41 includes a data transmission terminal 42 and a power supply terminal 43.

As shown in fig. 2, in the present embodiment, the power supply terminal 43 includes a VBUS pin of the first interface chip, wherein the VBUS pin is electrically connected to the external terminal 60 or the external power supply 70 through a TYPE-C data line. When the first physical interface 41 is a TYPE-C interface, the first interface chip includes two connection surfaces, i.e., an a surface and a B surface, each connection surface has 12 pins, the two connection surfaces are symmetrical with respect to the center of the pins, the VBUS pins may include the a9 pin of the a surface of the first interface chip and the B9 pin of the B surface, and at the same time, the first interface chip further includes a GND pin, which includes the a12 pin of the a surface of the first interface chip and the B12 pin of the B surface.

As shown in fig. 2, in the present embodiment, the data transmission terminal 42 includes a CC1 pin and a CC2 pin of the first interface chip; the first interface chip is configured to receive data transmitted by the external terminal 60 through the data transmission terminal 42 and transmit the data transmitted by the external terminal 60 to the control module 20 through the first output port 44 when detecting that the pin CC1 and the pin CC2 are both at a high level; the first interface chip is configured to obtain power from the external terminal 60 or the external power source 70 through the power supply terminal 43 and supply power to the control module 20 through the first output port 44 when detecting that the pin CC1 and the pin CC2 are both at a low level.

In the above embodiments, the CC1 pin includes the a 5pin of the a side of the first interface chip, and the CC2 pin includes the B5 pin of the B side of the first interface chip, at this time, the CC1 pin and the CC2 pin may be respectively converted into the USB D + pin and the USB D-pin for data transmission. After the TYPE-C data line is independently used to be connected with the external terminal 60, the external terminal 60 can transmit data to the chip testing device, and the chip testing device can burn the chip based on the transmitted data; the external terminal 60 can perform an operation of the working mode, for example, the external terminal 60 can exit the data transmission mode, i.e., enter the chip test mode, corresponding to the level changes of the pin CC1 and the pin CC2, at this time, the pin CC1 and the pin CC2 are both at a low level, and the power supply terminal 43 is used to obtain power from the external terminal 60 or the external power supply 70, and the first output port 44 is used to supply power to the control module 20.

In this embodiment, the first interface chip is further configured to send a first control signal to the control module 20 when detecting that the pin CC1 and the pin CC2 are both at a low level; the control module 20 is further configured to perform a test operation on the chip 50 to be tested in case of receiving the first control signal; the first interface chip is further configured to send a second control signal to the control module 20 when detecting that the pin CC1 and the pin CC2 are both at a high level; the control module 20 is further configured to perform a burning operation on the chip 50 to be tested according to the data transmitted by the external terminal 60 when receiving the second control signal.

In the above embodiment, the first interface chip may detect the level changes of the CC1 pin and the CC2 pin, and send different control signals to the control module 20 according to the level changes of the CC1 pin and the CC2 pin, so that the control module 20 performs a test operation or a burning operation on the chip 50 to be tested, and meanwhile, the TYPE-C data line manufactured by a user or a manufacturer may be used to perform the test operation or the burning operation on the chip 50 to be tested, and the data line may be inserted and pulled randomly without directional limitation, so that the compatibility is stronger, and the reliability of the chip testing apparatus is improved.

Fig. 3 is a schematic structural diagram of an output module 30 of a chip testing apparatus according to an embodiment of the present disclosure, and as shown in fig. 3, in some embodiments, the output module 30 includes a second interface chip, an input port of the second interface chip is electrically connected to one end of an external testing head, and the other end of the external testing head is electrically connected to a chip 50 to be tested.

In this embodiment, the input port of the second interface chip includes a first TYPE-C interface, and one end of the external test head includes a second TYPE-C interface; wherein, first TYPE-C interface with second TYPE-C interface passes through TYPE-C2C data line electrical connection.

The output module 30 of the chip testing apparatus in the related art usually includes 9 pins, and the 9 pins are respectively connected with 9 test head cables by welding, so that the test head can be held by hand to align with the chip for burning operation and testing operation.

In this embodiment, the input port of the second interface chip and one end of the external test head may be a TYPE-C interface female socket, and are defined uniformly, the output module 30 and the external test head may be electrically connected through a TYPE-C2C data line, the TYPE-C interface female socket is divided into two AB faces, each face has 12 output definitions, and pins corresponding to the a face and the B face are connected, that is, a1-B1, a2-B2 … a 12-12.

In the above embodiment, a1/B1 and a12/B12 may be defined as GND pins, a4/B4 and a9/B9 may be defined as power-on pins, a2/B2 may be defined as DAT pins, A3/B3 may be defined as CLK pins, a5/B5 may be defined as VDD pins, A6/B6 may be defined as CE pins, a7/B7 may be defined as SEN pins, A8/B8 may be defined as CHK pins, a10/B10 may be defined as DBD pins, and a11/B11 may be defined as DBC pins, so that the output module 30 and the input port of TYPE-C can correspond to a 9-bit test head.

In this embodiment, since the input port of the second interface chip and one end of the external test head are both TYPE-C TYPE interface sockets, the chip test device and the external test head can be connected without direction division through the TYPE-C2C data line.

In other embodiments, the input port of the second interface chip may further include one of: similarly, the first end of the external test head electrically connected to the input port of the second interface chip may include one of the following: b-5Pin type interface, B-4Pin type interface, B-8Pin-2 x 4 type interface, Micro USB type interface, Lightning type interface, to meet different requirements of users.

The embodiment provides a test head, which is applied to the chip testing device according to the above embodiment, fig. 4 is a schematic structural diagram of the test head according to the embodiment of the present application, as shown in fig. 4, one end 81 of the test head 80 includes a second TYPE-C interface, one end 81 of the test head 80 is electrically connected to the chip testing device 90, and the other end 82 of the test head is electrically connected to a chip to be tested.

In some embodiments, the other end 82 of the test head includes a plurality of probes, and the chip testing apparatus is configured to perform a testing operation and/or a burning operation on the chip to be tested after detecting that the probes contact the code writing and reading contacts of the chip to be tested.

The test head 80 in the related art often includes a terminal and a plurality of probes, wherein the terminal is inserted into the chip testing device 90 in a fixed direction and connected to a control module in the chip testing device 90, a data line at the other end of the terminal is soldered to a probe definition pin sleeve, and a user holds the completed contact by hand to perform burning operation and test operation on the chip.

However, in the above solution, the data line output by the chip testing device 90 needs to be soldered to the probe manually, and due to the short service life of the soldered flat cable, the short cable and the failure of testing may occur during the use of the testing head 80, and meanwhile, the common flat cable without the shielding cable may easily affect the data detection effect, and the inserted sheet may also easily have a definition error to affect the testing result, so that the burning error and the testing error may often occur.

In the above embodiment, since the input port of the second interface chip and one end of the external test head are both TYPE-C interface female sockets, the chip test device and the external test head can be connected in different directions through the TYPE-C2C data line, so as to avoid the above burning errors and test errors, improve the accuracy of the chip test result and the burning result, and improve the reliability of the chip test system.

The present embodiment provides a chip testing system, and fig. 5 is a schematic structural diagram of the chip testing system according to the embodiment of the present application, and as shown in fig. 5, the chip testing system includes: a chip testing apparatus 90 as in the previous embodiment, and a test head 80 as in the previous embodiment.

It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementations, and details are not described again in this embodiment.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express a few embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the appended claims.

Claims (10)

1. A chip testing device is applied to testing and/or burning a chip and is characterized by comprising a control module, an output module and an input module; wherein the content of the first and second substances,

the control module is respectively electrically connected with the output module and the input module and is used for carrying out test operation and/or burning operation on the chip to be tested when the output module is detected to be connected with the chip to be tested;

the input module comprises a first interface chip, wherein the first interface chip comprises a first physical interface and a first output port, the first physical interface is electrically connected with an external terminal or an external power supply, and the first output port is electrically connected with the control module;

the first interface chip is used for supplying power to the control module when the first physical interface is electrically connected with the external power supply, and transmitting data transmitted by the external terminal to the control module when the first physical interface is electrically connected with the external terminal.

2. The chip testing apparatus of claim 1, wherein the output module comprises a second interface chip, an input port of the second interface chip is electrically connected to one end of an external testing head, and the other end of the external testing head is electrically connected to the chip to be tested.

3. The chip test apparatus of claim 2, wherein the input port of the second interface chip comprises a first TYPE-C interface, and one end of the external test head comprises a second TYPE-C interface; wherein, first TYPE-C interface with second TYPE-C interface passes through TYPE-C2C data line electrical connection.

4. The chip testing apparatus according to claim 1, wherein the first physical interface includes a data transmission terminal electrically connected to an external terminal and a power supply terminal electrically connected to an external terminal or an external power supply;

the first interface chip is used for supplying power to the control module when the power supply terminal is electrically connected with the external power supply or the external terminal, and transmitting data transmitted by the external terminal to the control module when the data transmission terminal is electrically connected with the external terminal.

5. The chip test apparatus of claim 4, wherein the first physical interface comprises a third TYPE-C interface.

6. The chip testing device according to claim 4, wherein the first interface chip is further configured to send a first control signal to the control module when detecting that both the pin CC1 and the pin CC2 in the first interface chip are low;

the control module is further used for carrying out test operation on the chip to be tested under the condition of receiving the first control signal.

7. The chip testing apparatus according to claim 4, wherein the first interface chip is further configured to send a second control signal to the control module when detecting that both the pin CC1 and the pin CC2 in the first interface chip are high;

and the control module is also used for carrying out burning operation on the chip to be tested according to the data transmitted by the external terminal under the condition of receiving the second control signal.

8. A test head for use in a chip testing device according to any one of claims 1 to 7, wherein one end of the test head comprises a second TYPE-C interface, one end of the test head is electrically connected to the chip testing device, and the other end of the test head is electrically connected to a chip to be tested.

9. The test head as claimed in claim 8, wherein the other end of the test head comprises a plurality of probes, and the chip testing apparatus is configured to perform a test operation and/or a burn-in operation on the chip to be tested after detecting that the probes contact with the code writing and reading contacts of the chip to be tested.

10. A chip test system, comprising: the chip testing device of any one of claims 1 to 7, and the test head of any one of claims 8 to 9.

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