CN216216832U

CN216216832U - Dual-input signal synchronous detection circuit

Info

Publication number: CN216216832U
Application number: CN202121561556.XU
Authority: CN
Inventors: 张明艳; 李永江
Original assignee: Lishen Qingdao New Energy Co Ltd
Current assignee: Lishen Qingdao New Energy Co Ltd
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2022-04-05
Anticipated expiration: 2031-07-09

Abstract

The utility model discloses a double-input signal synchronous detection circuit, which comprises a signal input module; the input end IN1 and the input end IN2 of the signal input module are respectively connected with a first detection signal output end and a second detection signal output end of the external electronic circuit; the power supply input end VDD1 of the signal input module is connected with the power supply output end of the first power supply module; the output end Z1 of the signal input module is connected with the input end 1 of the signal output module; the output end of the signal input module is connected with the input end 2 of the signal output module; the output end Z3 of the signal input module is connected with the input end 3 of the signal output module; the power supply input end VDD2 of the signal output module is connected with the power supply output end of the second power supply module; the output end OUT of the signal output module is connected with one input/output port of the detection chip; the utility model can represent four combined states of two input signals through one output port, thereby saving precious hardware resources of the detection chip.

Description

Dual-input signal synchronous detection circuit

Technical Field

The utility model relates to the technical field of electronic circuits, in particular to a double-input signal synchronous detection circuit.

Background

At present, the input signals of electronic circuits usually comprise multiple signals, and an independent signal detection circuit is arranged for each input signal. Each signal detection circuit is provided with a signal output port for outputting a signal to the detection chip, the output signal normally having only two states of high level and low level.

When the number of input signals is large and the number of output signals is correspondingly increased, the resources of the input/output ports of the detection chip are in shortage, even the resources of the ports are insufficient.

Therefore, there is an urgent need to develop a technology that enables an existing detection chip (e.g., a single chip) to simultaneously detect a larger number of input signals under the existing port resources.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a double-input signal synchronous detection circuit aiming at the technical defects in the prior art.

Therefore, the utility model provides a double-input signal synchronous detection circuit, which comprises a signal input module, a signal output module, a first power supply module, a second power supply module and a detection chip, wherein:

the input end IN1 of the signal input module is connected with the first detection signal output end of the external electronic circuit and is used for receiving an input signal S1 provided by the external electronic circuit;

the input end IN2 of the signal input module is connected with the second detection signal output end of the external electronic circuit and is used for receiving an input signal S2 provided by the external electronic circuit;

the power supply input end VDD1 of the signal input module is connected with the power supply output end of the first power supply module and is used for receiving a direct-current power supply VDD 1;

the output end Z1 of the signal input module is connected with the input end 1 of the signal output module and is used for controlling whether current flows through the input end 1 of the signal output module by adjusting the state of the output end Z1;

the output end Z2 of the signal input module is connected with the input end 2 of the signal output module and is used for controlling the state change of the detection output signal OUT of the signal output module by adjusting the state of the output end Z2;

the output end Z3 of the signal input module is connected with the input end 3 of the signal output module and is used for controlling whether current flows through the first input end of the signal output module by adjusting the state of the output end Z3;

the power supply input end VDD2 of the signal output module is connected with the power supply output end of the second power supply module and is used for receiving a direct-current power supply VDD 2;

the output end OUT of the signal output module is connected with one input/output port of the detection chip and is used for providing a detection output signal OUT for the detection chip;

the detection output signal OUT has four states: high level a1, low level a2, high level B1, and low level B2.

Preferably, the detection chip is configured to pre-store and set correspondence between the detection output signal OUT in four different states and different state combinations that the two input signals S1 and S2 have, and to correspondingly determine and detect the states of the two input signals S1 and S2 according to the state of the currently received detection output signal OUT.

Preferably, in order of their voltage amplitude: low B2 < low a2 < high B1 < high a 1.

Preferably, the signal input module includes: resistors R1-R6, resistors R14-R15, voltage-stabilizing tube D1, switching tubes Q1-Q2 and optocouplers Q6-Q7, wherein:

a1 st pin of the resistor R1, which is an input terminal IN1 of the signal input module, is connected to a first detection signal output terminal of the external electronic circuit, and is configured to receive an input signal S1 provided by the external electronic circuit;

the 2 nd pin of the resistor R1 is respectively connected with the 1 st pin of the resistor R2 and the grid G of the switching tube Q1;

the 2 nd pins of the resistor R2 and the resistor R14 are respectively connected to a ground terminal GND1, and the ground terminal GND1 is the negative terminal of the power supply output of the first power supply module;

the source S of the switch tube Q1 is connected with the ground end GND 1;

the drain electrodes D of the switching tubes Q1 are respectively connected with the No. 2 pin of the optocoupler Q6;

the 1 st pin of the optocoupler Q6 is respectively connected with the 2 nd pin of the resistor R5 and the 1 st pin of the resistor R14;

a 3 rd pin of the optical coupler Q6 is used as an output end Z1 of the signal input module and is connected with a1 st pin of a resistor R7 in the signal output module;

a 4 th pin of the optical coupler Q6 is used as an output end Z2 of the signal input module and is connected with a1 st pin of a resistor R12 in the signal output module;

the 4 th pin of the optocoupler Q6 is also connected with the cathode of a voltage regulator tube D1;

the anode of the voltage regulator tube D1 is used as the output end Z3 of the signal input module and is connected with the 2 nd pin of the resistor R12 in the signal output module;

the anode of the voltage regulator tube D1 is also connected with the 3 rd pin of the optocoupler Q7;

a 4 th pin of the optical coupler Q7 is connected with a ground terminal GND2, and GND2 is a negative terminal of the power output end of the second power module;

the 1 st pin of the optocoupler Q7 is respectively connected with the 2 nd pin of the resistor R6 and the 1 st pin of the resistor R15;

the 2 nd pin of the optocoupler Q7 is connected with the drain D of the switch tube Q2;

the source S of the switch tube Q2 is connected with the ground end GND 1;

a gate G of the switching tube Q2, which is respectively connected with the 1 st pin of the resistor R4 and the 2 nd pin of the resistor R3;

the 2 nd pins of the resistor R4 and the resistor R15 are respectively connected with a ground terminal GND 1;

a1 st pin of the resistor R3, which is an input terminal IN2 of the signal input module, is connected to a second detection signal output terminal of the external electronic circuit, and is used for receiving an input signal S2 provided by the external electronic circuit;

the 1 st pin of the resistor R6 and the resistor R5, which is used as the power input terminal VDD1 of the signal input module, is connected to the power output terminal of the first power module and is used for receiving the DC power VDD 1.

Preferably, the signal output module includes: the resistor R7-R13, the capacitor C1 and the switch tube Q3-Q5, wherein:

a2 nd pin of the resistor R13, which is a power input terminal VDD2 of the signal output module, is connected to a power output terminal of the second power module, and is configured to receive a dc power supply VDD 2;

the 2 nd pin of the resistor R13 is also respectively connected with the emitter E of the switching tube Q3 and the 1 st pin of the resistor R10;

the 1 st pin of the resistor R13 is used as the input end 1 of the signal output module and is connected with the output end Z1 of the signal input module;

the 1 st pin of the resistor R13 is also connected with the 1 st pin of the resistor R7;

the 2 nd pin of the resistor R7 is connected with the collector C of the switch tube Q3;

the base B of the switching tube Q3 is connected with the 1 st pin of the resistor R9;

the 2 nd pin of the resistor R9 is connected with the Z4 end;

the Z4 end is also connected with the 2 nd pin of the resistor R10, the drain D of the switch tube Q5 and the source S of the switch tube Q4 respectively;

a gate G of the switching tube Q5, serving as the input end 2 of the signal output module, is connected to the output end Z2 of the signal input module, and is configured to receive the voltage and current input from the output end Z2 of the signal input module;

the grid G of the switching tube Q5 is also connected with the 1 st pin of the resistor R11 and the resistor R12 respectively;

the source S of the switching tube Q5 is used as the input end 3 of the signal output module and is connected with the output end Z3 of the signal input module;

the source S of the switch tube Q5 is also respectively connected with the gate G of the switch tube Q4 and the 2 nd pin of the resistor R12;

the 2 nd pin of the resistor R11 is used as the output end OUT of the signal output module, and is used for outputting four detection output signals OUT in different states to the detection chip;

the 2 nd pin of the resistor R11 is also connected with the 1 st pin of the capacitor C11, the 1 st pin of the resistor R8 and the drain D of the switch tube Q4 respectively;

the 2 nd pin of the capacitor C1 is connected with a ground terminal GND 2;

the 2 nd pin of the resistor R8 is connected to the ground GND 2.

Compared with the prior art, the double-input signal synchronous detection circuit has the advantages that the design is scientific, the semaphore with four states at one output port can be realized, the four combined states of two input signals can be represented through one output port, the number of the input and output ports of a detection chip which need to be occupied can be remarkably reduced (only one input and output port needs to be occupied), the precious hardware resources of the detection chip are saved, and the double-input signal synchronous detection circuit has great production practice significance.

For the utility model, the voltage amplitude of the high and low level of the output port can be flexibly adjusted according to the actual requirement, which is not only convenient for the chip to identify the signal state, but also beneficial to reducing the number of the input and output ports of the detection chip (such as a singlechip) which needs to be occupied.

For the technical scheme of the utility model, the hardware circuit design is scientific, the electronic components are of common application models, the model selection is easy, and the components are low in price, so that the technical scheme of the utility model has very high practical value and market popularization value.

Drawings

Fig. 1 is a block diagram of a dual-input signal synchronous detection circuit according to the present invention;

fig. 2 is a specific schematic diagram of a dual-input signal synchronous detection circuit according to the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to fig. 1 and fig. 2, the present invention provides a dual-input signal synchronous detection circuit, including a signal input module 10, a signal output module 20, a first power module 30, a second power module 40, and a detection chip 50, wherein:

an input terminal IN1 of the signal input module 10, connected to a first detection signal output terminal of the external electronic circuit, for receiving an input signal S1 provided by the external electronic circuit;

it should be noted that the external electronic circuit and the signal input module 10 of the present invention are connected to the same ground, i.e., both powered by the same dc power supply VDD 1. The input signals S1 and S2 provided by the external electronic circuit include three states, i.e., a high level, a low level, and a high impedance state, wherein the voltage amplitudes of the high level and the low level need to be set according to the power VDD1, and the high impedance state indicates that the input signals S1 and S2 are not connected.

In specific implementation, the external electronic circuit may be any one of the existing circuits capable of providing a tri-state signal (i.e., a signal including three basic logic states, i.e., a high level, a low level, and a high impedance state).

An input terminal IN2 of the signal input module 10, connected to a second detection signal output terminal of the external electronic circuit, for receiving an input signal S2 provided by the external electronic circuit;

the power input end VDD1 of the signal input module 10 is connected to the power output end of the first power module 30, and is configured to receive a dc power VDD 1;

the output terminal Z1 of the signal input module 10 is connected to the input terminal 1 of the signal output module 20, and is used for controlling whether current flows through the input terminal 1 of the signal output module 20 by adjusting the state of the output terminal Z1, so as to control the state change of the output terminal Z2 of the signal input module 10 and the change of the detection output signal OUT of the signal output module 20 respectively;

it should be noted that the state of the output terminal Z1 includes: the circuit comprises a high-resistance state and a conducting state, wherein the high-resistance state means that the output ends Z1 and Z2 are not electrically connected, and the resistance between the two ends Z1 and Z2 is infinite; the on state means that the output terminals Z1 and Z2 are electrically connected, and the voltage difference between the two terminals Z1 and Z2 is about 0.3V.

The output end Z2 of the signal input module 10 is connected to the input end 2 of the signal output module 20, and is used for controlling the state change of the detection output signal OUT of the signal output module 20 by adjusting the state of the output end Z2;

it should be noted that the output terminal Z2 has three states: a high impedance state, an on-state 1 and an on-state 2, wherein the high impedance state means that the output terminal Z2 is not electrically connected with the output terminals Z1 and Z3; the on-state 1 means that the output terminal Z2 is electrically connected with the output terminal Z1, but not electrically connected with the output terminal Z3, a voltage difference (e.g., about 0.3V) exists between the two ends of Z1 and Z2, and the resistance between the two ends of Z2 and Z3 is infinite; in the on state 2, the output terminal Z1 is electrically connected with the output terminals Z2 and Z3, and when the current flowing through the output terminals Z1, Z2 and Z3 is large enough, the voltage regulator tube D1 (see fig. 2) connected in series between the output terminal Z2 and the output terminal Z3 is broken down, so that the voltage regulator value of the voltage regulator tube D1 is set at the terminal Z2.

The output terminal Z3 of the signal input module 10 is connected to the input terminal 3 of the signal output module 20, and is used for controlling whether current flows through the first input terminal of the signal output module 20 by adjusting the state of the output terminal Z3, so as to control the state change of the output terminal Z2 of the signal input module 10 and the change of the detection output signal OUT of the signal output module 20 respectively;

the states of the output terminal Z3 include a high resistance state and an on state, where the high resistance state means that the output terminal Z3 is not electrically connected to the ground terminal GND (see fig. 2) of the third power module 50, and the resistance between the two terminals Z3 and GND is infinite; the on state means that the output terminal Z3 is electrically connected to the ground terminal GND (see fig. 2) of the third power module 50, and a voltage difference, such as about 0.3V, exists between the two terminals Z3 and GND.

The power input end VDD2 of the signal output module 20 is connected to the power output end of the second power module 40, and is configured to receive a dc power VDD 2;

the output end OUT of the signal output module 20 is connected to an input/output port of the detection chip 50 (e.g., a single chip microcomputer MCU), and is configured to provide a detection output signal OUT for the detection chip 50 (e.g., the single chip microcomputer MCU), where the detection output signal OUT has four states: the high level a1, the low level a2, the high level B1 and the low level B2 facilitate the detection of the identification of the signal state by the chip 50.

In the present invention, the correspondence between the four states of the output signal OUT and the different state combinations that the input signals S1 and S2 have is detected as follows:

1, when the input signals S1 and S2 are both low level, the output signal OUT is low level B2;

2, when the input signals S1 and S2 are both at high level, the output signal OUT is at high level B1;

3, when the input signal S1 is low and the input signal S2 is high, the output signal OUT is high a 1;

4, when the input signal S1 is high and the input signal S2 is low, the output signal OUT is at a low level a 2;

sequencing by voltage amplitude: low level B2 < low level a2 < high level B1 < high level a1, where low level B2 is 0V and high level a1 is close to the power supply VDD2 voltage;

it should be noted that the detection chip 50 is configured to store and set correspondence relationships between the detection output signal OUT in four different states and different state combinations of the two input signals S1 and S2 in advance, and correspondingly determine states of the two input signals S1 and S2 according to a state of the currently received detection output signal OUT.

In the present invention, it should be noted that, in terms of specific implementation, the single chip in the detection chip 50 may adopt a currently commonly used brand, series and model, such as the MC9S12 series of engimo, and the model of the detection chip 50 and the single chip thereof is out of the protection scope of the present invention.

In the present invention, it should be noted that, in terms of specific implementation, the first power module 30 and the second power module 40 may adopt an existing power module, for example, a power circuit commonly used in the technical scheme of the existing battery management system BMS, so that a technician can easily obtain and apply the power circuit without innovation, and the technical scheme thereof does not belong to the technical scheme of the present invention, and therefore, the detailed explanation is not provided herein.

Referring to fig. 1, the specific operation principle of the dual-input signal synchronous detection circuit provided by the present invention is as follows:

when the external electronic circuit does not provide the input signal S1 and the input signal S2, so that the input terminals IN1 and IN2 of the signal input module 10 are both IN a high-impedance state (suspended state), or the input signal S1 and the input signal B are both IN a low level, the VDD1 power supply current output by the first power supply module 30 is controlled not to flow through the signal input module 10, so that the output terminals Z1, Z2, and Z3 of the signal input module 10 are all IN a high-impedance state (three terminals are not electrically connected to each other), then the VDD2 power supply current output by the second power supply module 40 cannot flow through the output terminals Z1 to Z3 of the signal input module 10 through the input terminal 1 of the signal output module 20, so that the output terminal OUT of the signal output module 20 is at a low level B2, and the voltage amplitude thereof is 0V;

under this condition, the detecting chip 50 can correspondingly determine whether the input signals S1 and S2 are in the high impedance state or the low level according to the state of the output signal OUT at the low level B2.

Secondly, when the input signals S1 and S2 provided by the external electronic circuit are both high level, so that the input terminals IN1 and IN2 of the signal input module 10 are both high level, the VDD1 power current output by the first power module 30 is controlled to flow through the signal input module 10, so that the output terminal Z1 of the signal input module 10 is IN on-state (there is electrical communication between the output terminals Z1 and Z2), the output terminal Z2 is IN on-state 2 (there is a voltage stabilizing value of a voltage stabilizing tube D1 between the output terminals Z2 and Z3), and the output terminal Z3 is IN on-state (there is electrical communication between the output terminals Z3 and GND), so that the VDD2 power current output by the second power module 40 can flow through the output terminals Z1 to Z3 of the signal input module 10 through the input terminal 1 of the signal output module 20, so that the output terminal OUT of the signal output module 20 is high level B1, its voltage amplitude is greater than low level A2 and less than high level A1;

under this condition, the detecting chip 50 can determine that the input signals S1 and S2 are both high according to the high B1 state of the detecting output signal OUT.

When the input signal S1 provided by the external electronic circuit is at a low level and the input signal S2 is at a high level, the input terminal IN1 of the signal input module 10 is at a low level and the input terminal IN2 is at a high level, the VDD1 power supply current output by the first power supply module 30 is controlled to flow through the signal input module 10, so that the output terminal Z1 of the signal input module 10 is at a high-impedance state (no electrical communication exists between the output terminals Z1 and Z2), the output terminal Z2 is at a high-impedance state (no electrical communication exists between the output terminals Z2 and Z3), and the output terminal Z3 is at an on-state (electrical communication exists between the output terminals Z3 and GND); the output terminal Z1 in a high impedance state makes the VDD2 power supply current output by the second power supply block 40 unable to flow through the output terminals Z1 to Z3 of the signal input block 10 through the input terminal 1 of the signal output block 20, so that the output terminal OUT of the signal output block 20 is at a high level a1, and the voltage amplitude thereof is close to the power supply voltage VDD 2;

under this condition, the detecting chip 50 can correspondingly determine that the input signal S1 is low and the input signal S2 is high according to the high level a1 state of the output signal OUT.

Fourthly, when the input signal S1 provided by the external electronic circuit is at a high level and the input signal S2 is at a low level, the input terminal IN1 of the signal input module 10 is at a high level and the input terminal IN2 is at a low level, the VDD1 power current output by the first power module 30 is controlled to flow through the signal input module 10, so that the output terminal Z1 of the signal input module 10 is IN an on-state (electrical communication is provided between the output terminals Z1 and Z2), the output terminal Z2 is IN an on-state 1 (electrical communication is provided between the output terminal Z1 and no electrical communication is provided between the output terminal Z3), the output terminal Z3 is IN a high-resistance state (electrical communication is not provided between the output terminals Z3 and GND), the VDD power current output by the second power module 40 can flow through the input terminal 1 of the signal output module 20, only through the output terminals Z1 to Z2 of the signal input module 10, but not through the output terminal Z3, so that the output terminal OUT of the signal output module 20 is at the low level a2, and the voltage amplitude thereof is greater than the low level B2 and less than the high level B1;

under this condition, the detecting chip 50 can correspondingly determine that the input signal S1 is high and the input signal S2 is low according to the state of the output signal OUT at the low level a 2.

In the present invention, referring to fig. 2, in a specific implementation, the signal input module 10 includes: resistors R1-R6, resistors R14-R15, voltage-stabilizing tube D1, switching tubes Q1-Q2 and optocouplers Q6-Q7, wherein:

a1 st pin of the resistor R1, which is an input terminal IN1 of the signal input module 10, is connected to a first detection signal output terminal of the external electronic circuit, and is configured to receive an input signal S1 provided by the external electronic circuit;

the 2 nd pins of the resistor R2 and the resistor R14 are respectively connected to a ground GND1, and the ground GND1 is the negative terminal of the power output of the first power module 30;

the source S of the switch tube Q1 is connected with the ground end GND 1;

a 3 rd pin of the optical coupler Q6, which is used as the output terminal Z1 of the signal input module 10, is connected to a1 st pin of the resistor R7 in the signal output module 20 (i.e., the 1 st pin of the resistor R7 is used as the input terminal 1 of the signal output module 20);

a 4 th pin of the optical coupler Q6, which is used as the output terminal Z2 of the signal input module 10, is connected to a1 st pin of the resistor R12 in the signal output module 20 (i.e., the 1 st pin of the resistor R12 is used as the input terminal 2 of the signal output module 20);

the anode of the voltage regulator D1 is used as the output terminal Z3 of the signal input module 10, and is connected to the 2 nd pin of the resistor R12 in the signal output module 20 (i.e., the 2 nd pin of the resistor R12 is used as the input terminal 3 of the signal output module 20);

a 4 th pin of the optocoupler Q7 is connected to a ground terminal GND2, and GND2 is a negative terminal of the power output terminal of the second power module 40;

the source S of the switch tube Q2 is connected with the ground end GND 1;

a1 st pin of the resistor R3, which is an input terminal IN2 of the signal input module 10, is connected to a second detection signal output terminal of the external electronic circuit, and is configured to receive an input signal S2 provided by the external electronic circuit;

the 1 st pin of the resistor R6 and the resistor R5, which is the power input terminal VDD1 of the signal input module 10, is connected to the power output terminal of the first power module 30 for receiving the dc power VDD 1.

In a specific implementation of the present invention, the working principle of the signal input module 10 is as follows:

when the external electronic circuit does not provide the input signal S1 and the input signal S2, so that the input terminals IN1 and IN2 of the signal input module 10 are both IN a high-impedance state (a suspended state), or the input signal S1 and the input signal S2 are both IN a low level, the gate G of the switching tube Q1 is pulled down by the resistor R2 to a low level equal to the ground terminal GND1 and is turned off, so that the optocoupler Q6 is turned off; similarly, the gate G of the switching tube Q2 is pulled down by the resistor R4 to a low potential equal to the ground GND1 and is cut off, so that the optocoupler Q7 is cut off, and the output ends Z1, Z2 and Z3 of the signal input module 10 are all in a high impedance state, and the output end OUT of the signal output module 20 is controlled to be at a low level B, and the voltage amplitude thereof is 0V;

when the voltage of the power supply VDD1 is high voltage, after the resistors R5 and R14 divide the voltage of VDD1, the voltage borne between the drain D and the source S of the switching tube Q1 can be reduced, so that the switching tube Q1 can select a medium-low voltage model.

When the input signal S1 and the input signal S2 provided by the external electronic circuit are both high level, the output ends Z1, Z2 and Z3 are no longer in high resistance state; the high-level signals S1 and S2 enable the switching tubes Q1 to Q2 and the optocouplers Q6 to Q7 to be turned on, enable the output ends Z1 and Z3 to be in on states, enable the output end Z2 to be in on state 2 (voltage stabilization value Z2 of breakdown of a voltage stabilizing tube D1), control the output end OUT of the signal output module 20 to be a high level B1, and control the voltage amplitude of the output end OUT to be greater than the low level a2 and smaller than the high level a 1;

it should be noted that the current flowing through the zener diode D1 needs to be able to make the zener diode D1 enter the voltage stabilizing area, and the voltage stabilizing value Z2 is determined according to the VDD2 power voltage. For example, if VDD2 is 5V, the regulated voltage value Z2 may be 3.3V.

When an input signal S1 provided by an external electronic circuit is at a low level and an input signal S2 is at a high level, the switching tube Q1 is turned off, and the switching tube Q2 is turned on, so that the optical coupler Q6 is turned off, and the optical coupler Q7 is turned on; the cut-off optocoupler Q6 enables the output ends Z1 and Z2 to be in a high impedance state, and the turned-on optocoupler Q7 enables the output end Z3 to be in a conducting state, so that the output end OUT of the signal output module 20 is controlled to be in a high level A1, and the voltage amplitude of the output end OUT is close to the power supply voltage VDD 2.

When an input signal S1 provided by the external electronic circuit is at a high level and an input signal S2 is at a low level, the switching tube Q1 is switched on and the switching tube Q2 is switched off, so that the optical coupler Q6 is switched on and the optical coupler Q7 is switched off; the on-state optocoupler Q6 makes the output end Z1 be in a high impedance state and the output end Z2 be in an on-state 1 (the output ends Z1 and Z2 are electrically connected with each other), and the on-state optocoupler Q7 makes the output end Z3 be in an on-state, controls the output end OUT of the signal output module 20 to be a low level a2, and controls the voltage amplitude of the output end OUT to be greater than the low level B2 and less than the high level B1.

In the present invention, in a specific implementation, referring to fig. 2, the signal output module 20 includes: the resistor R7-R13, the capacitor C1 and the switch tube Q3-Q5, wherein:

a2 nd pin of the resistor R13, which serves as a power input terminal VDD2 of the signal output module 20, is connected to a power output terminal of the second power module 40, and is configured to receive a dc power supply VDD 2;

the level state of the 1 st pin of the resistor R13, which is the input terminal 1 of the signal output module 20 and is connected to the output terminals Z1 and Z1 of the signal input module 10, determines whether current flows through the input terminal 1 of the signal output module 20 and the output terminal Z1 of the signal input module 10;

the 2 nd pin of the resistor R9 is connected with the Z4 end;

a gate G of the switching tube Q5, serving as the input end 2 of the signal output module 20, is connected to the output end Z2 of the signal input module 10, and is configured to receive the voltage and current input from the output end Z2 of the signal input module 10;

the source S of the switching tube Q5, which is the input terminal 3 of the signal output module 20, is connected to the output terminals Z3 and Z3 of the signal input module 10, and determines whether current flows through the input terminal 3 of the signal output module 20 and the output terminal Z3 of the signal input module 10;

the 2 nd pin of the resistor R11, which is the output terminal OUT of the signal output module 20, is used to output four detection output signals OUT of different states to the detection chip 50, including a high level B1, a low level B2, a high level a1, and a low level a2, in order of their voltage amplitudes: low level B2 < low level a2 < high level B1 < high level a1, where low level B2 is 0V and high level a1 is close to the power supply VDD2 voltage; the detecting chip 50 can determine the level states of the input signals S1 and S2 according to the level state of the output signal OUT.

the 2 nd pin of the capacitor C1 is connected with a ground terminal GND 2;

the 2 nd pin of the resistor R8 is connected to the ground GND 2.

In the present invention, in a specific implementation, the working principle of the signal output module 20 is as follows:

when the external electronic circuit does not provide the input signal S1 and the input signal S2, the input terminals IN1 and IN2 of the signal input module 10 are all IN a high impedance state (a suspended state), or the input signal S1 and the input signal B are both provided IN a low level, the output terminals Z1, Z2 and Z3 of the signal input module 10 are all IN a high impedance state; the switching tubes Q3 to Q5 are turned off by the high-resistance states Z2 and Z3, so that the output end OUT of the input module 10 is pulled down by the resistor R8 to be equal to the potential of the ground GND2, the output end OUT is at a low level B2, and the voltage amplitude is 0V;

the sense chip 50 can determine that the input signals S1 and S2 are in a high impedance state or a low level according to the sense output signal OUT at the low level B2.

When the input signal S1 and the input signal S2 provided by the external electronic circuit are both high, the output terminals Z1 and Z3 of the signal input module 10 are both in an on state, and the output terminal Z2 is in an on state 2; therefore, the method comprises the following steps: the switching tubes Q3-Q4 are switched on, so that the current of a power supply VDD2 flows through the ends Z1, Z2 and Z3, the current enables the end Z2 to be equal to a stabilized voltage value Z2 after the voltage regulator tube D1 is broken down, and the stabilized voltage value Z2 enables the switching tube Q5 to be switched on, so that the switching tube Q4 is switched off; however, the switch Q5 and the Z3 end in the on state keep the switch Q3 on, and further keep the voltage stabilization value Z2 at the Z2 end unchanged, so that the output end OUT of the signal output module 20 is at a high level B1, the voltage amplitude of the output end OUT is equal to the voltage value obtained by dividing the voltage stabilization value Z2 by the resistors R8 and R11, and the voltage value is greater than the low level a2 and less than the high level a 1.

The sense chip 50 can determine that the input signals S1 and S2 are both high based on the sense output signal OUT at the high level B1.

When the input signal S1 provided by the external electronic circuit is at a low level and the input signal S2 is at a high level, the output terminals Z1 to Z2 of the signal input module 10 are in a high impedance state, and Z3 is in a conducting state; the input signal S1 is at low level, so that the terminal Z1 is at high impedance state, and therefore no current flows between the terminals Z1 and Z2, and the terminal Z2 and the terminal Z3 are at equal potential by the resistor R12, so that the switch tube Q5 is turned off; the input signal S2 is at a high level, so that the end Z3 is in a conducting state, the switching tubes Q3 to Q4 are turned on, the output end OUT of the signal output module 20 is at a high level a1, the voltage amplitude of the output end OUT is equal to the voltage value obtained by dividing the power supply voltage VDD2 by the resistors R8 and R9, and the voltage value obtained by subtracting the conducting voltage drop between the emitter E and the base B of the switching tube Q3 is close to the power supply voltage VDD 2;

the sense chip 50 may determine that the input signal S1 is low and the input signal S2 is high according to the sense output signal OUT of the high level a 1.

Fourthly, when the input signal S1 provided by the external electronic circuit is at a high level and the input signal S2 is at a low level, the output terminal Z1 of the signal input module 10 is in an on state, Z2 is in an on state 1, and Z3 is in a high impedance state; the input signal S2 is low level, so that the end Z3 is in a high impedance state, the switch tubes Q3-Q4 are cut off, no current flows in the switch tube Q3, and the voltage stabilizing tube D1 cannot be broken down by voltage stabilization; the input signal S1 is at a high level, so that currents flow through terminals Z1 to Z2, and the currents flow through the resistors R13, R11 and R8, at this time, the terminal voltage Z2 is equal to the voltage value obtained by dividing the power supply VDD2 by the resistors R8, R11 and R13, and the voltage can turn on the switching tube Q5, further keep the switching tube Q4 in an off state, and at the same time, the terminal Z3 in a high-resistance state keeps the switching tube Q3 in an off state, so that the output terminal OUT of the signal output module 20 is at a low level a1, and the voltage amplitude of the output terminal OUT is equal to the voltage value obtained by dividing the terminal voltage Z2 by the resistors R8 and R11;

the sense chip 50 may determine that the input signal S1 is high and the input signal S2 is low according to the sense output signal OUT of the low level a 1.

In summary, compared with the prior art, the dual-input signal synchronous detection circuit provided by the utility model has a scientific design, can realize that one output port has four-state semaphore, can represent four combined states of two input signals through one output port, can remarkably reduce the number of input and output ports of a detection chip (only one input and output port needs to be occupied), saves precious hardware resources of the detection chip, and has great production practice significance.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A dual-input signal synchronous detection circuit is characterized by comprising a signal input module (10), a signal output module (20), a first power supply module (30), a second power supply module (40) and a detection chip (40), wherein:

the input end IN1 of the signal input module (10) is connected with a first detection signal output end of the external electronic circuit and is used for receiving an input signal S1 provided by the external electronic circuit;

the input end IN2 of the signal input module (10) is connected with the second detection signal output end of the external electronic circuit and is used for receiving an input signal S2 provided by the external electronic circuit;

the power supply input end VDD1 of the signal input module (10) is connected with the power supply output end of the first power supply module (30) and is used for receiving a direct-current power supply VDD 1;

the output end Z1 of the signal input module (10) is connected with the input end 1 of the signal output module (20) and is used for controlling whether current flows through the input end 1 of the signal output module (20) by adjusting the state of the output end Z1;

the output end Z2 of the signal input module (10) is connected with the input end 2 of the signal output module (20) and is used for controlling the state change of the detection output signal OUT of the signal output module (20) by adjusting the state of the output end Z2;

the output end Z3 of the signal input module (10) is connected with the input end 3 of the signal output module (20) and is used for controlling whether current flows through the first input end of the signal output module (20) or not by adjusting the state of the output end Z3;

the power supply input end VDD2 of the signal output module (20) is connected with the power supply output end of the second power supply module (40) and is used for receiving a direct-current power supply VDD 2;

the output end OUT of the signal output module (20) is connected with one input/output port of the detection chip (40) and is used for providing a detection output signal OUT for the detection chip (40);

2. The dual input signal synchronous detection circuit as claimed in claim 1, wherein the detection chip (40) is configured to pre-store and set correspondence between the detection output signal OUT in four different states and different state combinations that the two input signals S1 and S2 have, and to correspondingly determine and detect the states of the two input signals S1 and S2 according to the state of the currently received detection output signal OUT.

3. The dual input signal synchronous detection circuit of claim 1, wherein, in order of their voltage amplitudes: low B2 < low a2 < high B1 < high a 1.

4. The dual input signal synchronous detection circuit of claim 1, wherein the signal input module (10) comprises: resistors R1-R6, resistors R14-R15, voltage-stabilizing tube D1, switching tubes Q1-Q2 and optocouplers Q6-Q7, wherein:

a1 st pin of the resistor R1, which is used as an input end IN1 of the signal input module (10), is connected with a first detection signal output end of the external electronic circuit and is used for receiving an input signal S1 provided by the external electronic circuit;

the 2 nd pins of the resistor R2 and the resistor R14 are respectively connected with a ground terminal GND1, and the ground terminal GND1 is the negative terminal of the power supply output of the first power supply module (30);

the source S of the switch tube Q1 is connected with the ground end GND 1;

a 3 rd pin of the optical coupler Q6 is used as an output end Z1 of the signal input module (10) and is connected with a1 st pin of a resistor R7 in the signal output module (20);

a 4 th pin of the optical coupler Q6 is used as an output end Z2 of the signal input module (10) and is connected with a1 st pin of a resistor R12 in the signal output module (20);

the anode of the voltage regulator tube D1 is used as the output end Z3 of the signal input module (10) and is connected with the 2 nd pin of the resistor R12 in the signal output module (20);

a 4 th pin of the optical coupler Q7 is connected with a ground terminal GND2, and GND2 is a negative terminal of the power output terminal of the second power module (40);

the source S of the switch tube Q2 is connected with the ground end GND 1;

a1 st pin of the resistor R3, which is used as an input end IN2 of the signal input module (10), is connected with a second detection signal output end of the external electronic circuit and is used for receiving an input signal S2 provided by the external electronic circuit;

the 1 st pin of the resistor R6 and the resistor R5 is used as a power input end VDD1 of the signal input module (10), is connected with a power output end of the first power module (30), and is used for receiving a direct current power supply VDD 1.

5. The dual input signal synchronous detection circuit of claim 1, wherein the signal output module (20) comprises: the resistor R7-R13, the capacitor C1 and the switch tube Q3-Q5, wherein:

a2 nd pin of the resistor R13, which is used as a power input end VDD2 of the signal output module (20), is connected with a power output end of the second power module (40) and is used for receiving a direct current power supply VDD 2;

the 1 st pin of the resistor R13 is used as the input end 1 of the signal output module (20) and is connected with the output end Z1 of the signal input module (10);

the 2 nd pin of the resistor R9 is connected with the Z4 end;

a grid G of the switching tube Q5, which is used as the input end 2 of the signal output module (20), is connected with the output end Z2 of the signal input module (10) and is used for receiving the voltage and the current input by the output end Z2 of the signal input module (10);

the source S of the switching tube Q5 is used as the input end 3 of the signal output module (20) and is connected with the output end Z3 of the signal input module (10);

the 2 nd pin of the resistor R11 is used as the output end OUT of the signal output module (20) and is used for outputting detection output signals OUT of four different states to the detection chip (40);

the 2 nd pin of the capacitor C1 is connected with a ground terminal GND 2;

the 2 nd pin of the resistor R8 is connected to the ground GND 2.