CN113359016A - Detection circuit for tri-state input signal - Google Patents
Detection circuit for tri-state input signal Download PDFInfo
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- CN113359016A CN113359016A CN202110579922.2A CN202110579922A CN113359016A CN 113359016 A CN113359016 A CN 113359016A CN 202110579922 A CN202110579922 A CN 202110579922A CN 113359016 A CN113359016 A CN 113359016A
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Abstract
The invention discloses a detection circuit of a tri-state input signal, which comprises an input module, a power supply input end and an output end, wherein the input end Vin of the input module is connected with a detection signal output end of an external electronic circuit, the power supply input end of the input module is connected with a power supply module, and the output end of the input module is connected with the input end A2 of the output module; the first input end of the enabling module is connected with the detection signal output end of the external electronic circuit; the second input end of the enabling module is connected with the power supply module; the output end of the enabling module is connected with the input end A1 of the input module; the input end A2 of the output module is connected with the output end of the input module; the power input end of the output module is connected with the power module; the output end Vo of the output module is connected with one input/output port of the detection chip. The detection circuit of the tri-state input signal disclosed by the invention can represent three states of the input signal through one output port, thereby obviously reducing the number of the input and output ports of the detection chip which need to be occupied and saving precious hardware resources of the detection chip.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a detection circuit of a tri-state input signal.
Background
At present, an input signal of an electronic circuit includes three basic logic states, i.e., a high level, a low level, and a high impedance state, and signals having the three logic states are simply referred to as three-state signals.
For the existing detection chip (such as a single chip microcomputer), only two signal states of high level and low level can be identified.
In order to make the existing detection chip (such as a single chip) recognize three basic logic states of an input signal, the existing circuit for detecting a tri-state input signal needs to adopt a method of combining signals of two output ports, for example: the two output ports are respectively connected with two input/output (I/O) ports of the detection chip (such as a singlechip), and the two output ports are connected with a third input/output port on the detection chip after confluence intersection, so that more input/output ports of the detection chip can be occupied, port resources of the detection chip are strained, and the connection requirements of other electronic modules are not easily met.
Disclosure of Invention
The invention aims to provide a detection circuit of a tri-state input signal, aiming at the technical defects in the prior art.
Therefore, the invention provides a detection circuit of a tri-state input signal, which comprises an input module, an output module, an enabling module and a power supply module, wherein:
the input end Vin of the input module is connected with the detection signal output end of the external electronic circuit and used for receiving a detection input signal Vin provided by the external electronic circuit;
the power supply input end of the input module is connected with the output end VDD of the power supply module and is used for receiving a direct-current power supply VDD;
the output end of the input module is connected with the input end A2 of the output module and is used for providing input signals A2 with different states for the output module so as to control the change of the output signal Vo of the output module;
the first input end of the enabling module is connected with the detection signal output end of the external electronic circuit and used for receiving a detection input signal Vin provided by the external electronic circuit;
the second input end of the enabling module is connected with the output end VDD of the power supply module and used for receiving a direct-current power supply VDD;
the output end of the enabling module is connected with the input end A1 of the input module and is used for providing an enabling signal A1 for the input module;
the input end A2 of the output module is connected with the output end of the input module and is used for receiving an output signal A2 provided by the input module;
the power supply input end of the output module is connected with the output end VDD of the power supply module and is used for receiving a direct-current power supply VDD;
the output end Vo of the output module is connected with one input/output port of the detection chip 50, and is used for providing a detection output signal Vo for the detection chip 50;
wherein, the detection output signal Vo has three states: high, low and 0V.
Preferably, the input module includes: resistors R1-R3 and an operational amplifier U1, wherein:
a1 st pin of the resistor R1, which is used as an input terminal Vin of the input module, is connected to a detection signal output terminal of the external electronic circuit, and is used for receiving a detection input signal Vin provided by the external electronic circuit;
a2 nd pin of the resistor R1 is connected with a2 nd pin of the operational amplifier U1, and the 2 nd pin is a signal negative pole input end;
the 1 st pin of the operational amplifier U1 is a signal positive input end of the operational amplifier U1 and is respectively connected with the 2 nd pin of the resistor R2 and the 1 st pin of the resistor R3;
the 3 rd pin of the operational amplifier U1 is used as the input end A1 of the input module and is used for receiving the enable signal A1 output by the enable module;
the 4 th pin of the operational amplifier U1 is used as a power supply input end of the input module, is connected with the output end VDD of the power supply module, and is used for receiving a direct-current power supply VDD;
the 4 th pin of the operational amplifier U1 is also connected with the 1 st pin of the resistor R2;
a1 st pin of the resistor R2, which is used as a power input terminal of the input module, is connected to an output terminal VDD of the power module, and is configured to receive a dc power supply VDD;
the 5 th pin of the operational amplifier U1 is connected with a ground terminal GND;
the 2 nd pin of the resistor R3 is connected with the ground terminal GND;
the 6 th pin of the operational amplifier U1, which is an output terminal of the input module, is connected to the input terminal a2 of the output module, and is used to provide the input signal a2 with different states for the output module.
Preferably, the enabling module comprises: resistors R4-R9 and switching tubes Q1-Q3, wherein:
the 1 st pin of the resistor R4 and the resistor R5 is used as a first input end of the enabling module, is connected with a detection signal output end of the external electronic circuit, and is used for receiving a detection input signal Vin provided by the external electronic circuit;
the 2 nd pin of the resistor R4 is respectively connected with the source S of the switching tube Q1 and the gate G of the switching tube Q2;
the source S of the switch tube Q2 is connected with the 2 nd pin of the resistor R7;
the drain D of the switching tube Q2 is respectively connected with the 1 st pin of the resistor R8 and the base B of the switching tube Q3;
a1 st pin of the resistor R7, which serves as a second input terminal of the enable module, is connected to an output terminal VDD of the power supply module, and is configured to receive a dc power supply VDD;
the 1 st pin of the resistor R7 is also connected with the 2 nd pin of the resistor R9;
the 2 nd pin of the resistor R8 is connected with the ground terminal GND;
a collector C of the switching tube Q3, serving as an output end of the enabling module, is connected to the input end a1 of the input module, and is configured to output an enabling signal a1 for the input module, where the enabling signal a1 is configured to control the operational amplifier U1 in the input module to be in a disabled or activated state;
the collector C of the switch tube Q3 is also connected with the 1 st pin of the resistor R9;
the 2 nd pin of the resistor R5 is respectively connected with the 1 st pin of the resistor R6 and the grid G of the switching tube Q1;
the 2 nd pin of the resistor R6 is connected with the ground terminal GND;
the drain D of the switching tube Q1 and the emitter E of the switching tube Q3 are both connected to the ground GND.
Preferably, the output module includes: resistors R10-R15 and switching tubes Q4-Q6, wherein:
the 1 st pin of the resistor R10, which is the input terminal a2 of the output module, is connected to the output terminal of the input module, and is used for receiving the output signal a2 provided by the input module, and the state of the output signal a2 has three states: high level, low level and high resistance state;
the 1 st pin of the resistor R10 is also connected with the 1 st pin of the resistor R11;
the 2 nd pin of the resistor R10 is connected with the grid G of the switch tube Q4;
the source S of the switch tube Q4 is connected with the 2 nd pin of the resistor R12;
the drain D of the switching tube Q4, which is the output Vo of the output module, is connected to an input/output port of the detecting chip 50, and is used to provide a detecting output signal Vo for the detecting chip, where the detecting output signal Vo has three states: high level, low level and 0V;
the drain D of the switch tube Q4 is also respectively connected with the 1 st pin of the resistor R13, the emitter E of the switch tube Q5 and the 1 st pin of the resistor R15;
the 2 nd pin of the resistor R11 is respectively connected with the base B of the switch tube Q5 and the base B of the switch tube Q6;
the collector C of the switch tube Q6 is connected with the 2 nd pin of the resistor R15;
an emitter E of the switching tube Q6 is connected with a ground end GND;
the collector C of the switch tube Q5 is connected with the 2 nd pin of the resistor R14;
a1 st pin of the resistor R14, which is used as a power input terminal of the output module, is connected to an output terminal VDD of the power module, and is configured to receive a dc power supply VDD;
the 1 st pin of the resistor R14 is also connected to the 1 st pin of the resistor R12.
Preferably, the operation mode of the enabling module is as follows:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state, the gate G of the switch tube Q1 is pulled down to a low potential equal to a ground terminal GND by the resistor R6 to be cut off, the gate G of the switch tube Q2 is pulled down to a low potential equal to the ground terminal GND by the resistors R4 to R6 to be cut off, so that the switch tube Q3 is cut off, the output end of the enable module is pulled up to a high potential equal to the power supply VDD by the resistor R9, that is, the input end a1 of the input module is at a high level, so that the operational amplifier U1 in the input module is in a disabled state;
when the detection input signal Vin provided by the external electronic circuit is at a high level, the gate G of the switching tube Q1 is turned on after being provided with the bias voltage and the current by the resistors R5 and R6, so that the gate G of the switching tube Q2 is at a low potential, and the switching tube Q2 is turned on, and then the switching tube Q3 is turned on by being provided with the bias voltage and the current by the resistor R7 and the resistor R8, so that the input end a1 of the input module is at a low level, and the operational amplifier U1 in the input module is activated;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the switching tube Q1 is turned off, the switching tube Q2 is turned on, and the switching tube Q3 is turned on by the bias voltage and current provided by the resistor R7 and the resistor R8, so that the input end a1 of the input module becomes at a low level, and the operational amplifier U1 in the input module is activated.
Preferably, the operation mode of the output module is as follows:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state, an operational amplifier U1 in the input module is in a forbidden state, and an output end of the operational amplifier U1 is in the high-impedance state, namely, an input end A1 of the output module is in the high-impedance state, the switching tubes Q4-Q6 are all cut off, so that an output end Vo of the output module is pulled down by a resistor R13 to be 0V equal to the potential of a ground end GND;
when a detection input signal Vin provided by an external electronic circuit is at a high level, an operational amplifier U1 in the input module is in an activated state, and a signal at an output end of the operational amplifier U1 is changed correspondingly along with the state of the detection input signal Vin, that is, an input end a1 of the output module is at a low level, so that the switching tubes Q5 to Q6 are all turned off, and the switching tube Q4 is turned on, so that an output end Vo of the output module is changed into a high level after being divided by a resistor R12 and a resistor R13;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the switching tube Q4 is turned off, and the switching tubes Q5-Q6 are turned on, so that the output Vo of the output module is divided by the resistor R14 and the resistor R15 and then becomes at a low level.
Preferably, the following modes of operation are included:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state, the enabling module enables an input end A1 of the input module to be in a high level, the input module is in a forbidden state, and an input end A2 of the output module is in a high-impedance state, so that an output end Vo of the output module is 0V; therefore, the detection chip 50 correspondingly determines that the input detection signal Vin is in a high impedance state according to the detection output signal Vo of 0V;
when the detection input signal Vin provided by the external electronic circuit is at a high level, the enabling module enables the input end A1 of the input module to be at a low level, and activates the input module to enable the signal state of the output end of the input module to change along with the state of the detection input signal Vin; the output end of the input module is at a low level due to the fact that the input signal Vin is detected to be at a high level, and therefore the output end Vo of the output module is at a high level; therefore, the detection chip 50 correspondingly determines that the input detection signal Vin is at a high level according to the high-level detection output signal Vo;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the enabling module enables the input end a1 of the input module to be at a low level, and activates the input module to enable the signal state of the output end of the input module to change along with the state of the detection input signal Vin; the output end of the input module is at a high level due to the fact that the input signal Vin is detected to be at a low level, and therefore the output end Vo of the output module is at a low level; therefore, the detection chip 50 determines that the input detection signal Vin is at a low level according to the low-level detection output signal Vo.
Compared with the prior art, the technical scheme provided by the invention has the advantages that the circuit for detecting the tri-state input signal is scientific in design, the semaphore of one output port with three states can be realized, the three states of the input signal can be represented through one output port, the number of the input and output ports of the detection chip which need to be occupied can be obviously reduced (only one input and output port needs to be occupied), the precious hardware resource of the detection chip is saved, and the circuit has great production practice significance.
For the invention, the voltage amplitude of the high and low level of the output port can be flexibly adjusted according to the actual requirement, which is not only convenient for the chip to identify the signal state, but also beneficial to reducing the number of the input and output ports of the detection chip (such as a singlechip) which needs to be occupied.
For the technical scheme of the invention, the hardware circuit design is scientific, the electronic components are of common application models, the model selection is easy, and the components are low in price, so that the technical scheme of the invention has very high practical value and market popularization value.
Drawings
Fig. 1 is a block diagram of a tri-state input signal detection circuit according to the present invention;
fig. 2 is a specific schematic diagram of a detection circuit for tri-state input signals according to the present invention.
Detailed Description
In order to make the technical means for realizing the invention easier to understand, the following detailed description of the present application is made in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In addition, it should be noted that, in the description of the present application, unless otherwise explicitly specified and limited, the terms "mounted, disposed" and the like are to be understood in a broad sense, e.g., either fixedly or detachably mounted.
The specific meaning of the above terms in the present application can be understood by those skilled in the art as the case may be.
Referring to fig. 1 and fig. 2, the present invention provides a detection circuit for a tri-state input signal, including an input module 10, an output module 30, an enable module 20 and a power supply module 40, wherein:
an input end Vin of the input module 10 is connected to a detection signal output end of an external electronic circuit, and is configured to receive a detection input signal Vin provided by the external electronic circuit;
it should be noted that the external electronic circuit and the input module 10 of the present invention are grounded, that is, both are powered by the same power supply VDD, the detection signal Vin provided by the external electronic circuit is a tri-state signal, and the voltage amplitudes of the high level and the low level of the detection signal Vin are set according to the power supply VDD.
In specific implementation, the external electronic circuit may be any one of the existing circuits capable of providing a tri-state signal (i.e., a signal including three basic logic states, i.e., a high level, a low level, and a high impedance state).
The power input end of the input module 10 is connected to the output end VDD of the power module 40 and is used for receiving a direct-current power supply VDD;
the output end of the input module 10 is connected to the input end a2 of the output module 30, and is used for providing input signals a2 with different states for the output module 30, so as to control the change of the output signal Vo of the output module 30;
a first input terminal of the enable module 20 is connected to a detection signal output terminal of the external electronic circuit, and is configured to receive a detection input signal Vin provided by the external electronic circuit;
a second input terminal of the enable module 20 is connected to the output terminal VDD of the power module 40, and is configured to receive the dc power VDD;
an output of the enable module 20, connected to the input a1 of the input module 10, for providing an enable signal a1 for the input module 10;
input terminal a2 of output module 30, connected to the output terminal of input module 10, for receiving output signal a2 provided by said input module 10;
the power input end of the output module 30 is connected to the output end VDD of the power module 40 and is used for receiving a direct-current power supply VDD;
the output Vo of the output module 30 is connected to an input/output port of the detecting chip 50 (e.g. a single-chip MCU), and is used for providing a detecting output signal Vo for the detecting chip 50 (e.g. the single-chip MCU), where the detecting output signal Vo has three states: high level, low level and 0V facilitate the detection chip 50 to recognize the signal status.
It should be noted that the detection chip 50 is configured to pre-store and set correspondence relationships between the detection output signals Vo in three different states and the detection input signals in the three different states, and correspondingly determine to obtain the states of the detection input signals according to the states of the currently received detection output signals Vo.
In the present invention, it should be noted that, in terms of specific implementation, the detecting chip 50 may be of a currently commonly used brand, series and model, such as the MC9S12 series of enginepu, and the model of the detecting chip 50 is not within the protection scope of the present invention.
Referring to fig. 1, the specific operation principle and operation mode of the detection circuit for tri-state input signals provided by the present invention are as follows:
when the detection input signal Vin provided by the external electronic circuit is in a high impedance state (suspended state), the enabling module 20 makes the input end a1 of the input module 10 in a high level, and then the input module 10 is in a disabled state, and makes the input end a2 of the output module 30 in a high impedance state, so that the output end Vo of the output module 30 is 0V; therefore, the detection chip 50 can correspondingly determine that the input detection signal Vin is in a high impedance state according to the detection output signal Vo of 0V;
when the detection input signal Vin provided by the external electronic circuit is at a high level, the enabling module 20 makes the input end a1 of the input module be at a low level, and activates the input module 10, so that the signal state of the output end of the input module changes along with the state of the detection input signal Vin; as the input signal Vin is detected to be at a high level, the output terminal of the input module 10 is at a low level, so that the output terminal Vo of the output module 30 is at a high level; therefore, the detection chip 50 can correspondingly determine that the input detection signal Vin is at a high level according to the high-level detection output signal Vo;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the enabling module 20 enables the input end a1 of the input module to be at a low level, and activates the input module 10, so that the signal state of the output end of the input module changes along with the state of the detection input signal Vin; as the input signal Vin is detected to be at a low level, the output terminal of the input module 10 is at a high level, so that the output terminal Vo of the output module 30 is at a low level; therefore, the detection chip 50 can correspondingly determine that the input detection signal Vin is at a low level according to the low-level detection output signal Vo.
In the present invention, in a specific implementation, referring to fig. 2, the input module 10 includes: resistors R1-R3 and an operational amplifier U1, wherein:
a1 st pin of the resistor R1, which is used as an input terminal Vin of the input module 10, is connected to a detection signal output terminal of the external electronic circuit, and is configured to receive a detection input signal Vin provided by the external electronic circuit;
a2 nd pin of the resistor R1 is connected with a2 nd pin of the operational amplifier U1, and the 2 nd pin is a signal negative pole input end;
the 1 st pin of the operational amplifier U1 is a signal positive input end of the operational amplifier U1 and is respectively connected with the 2 nd pin of the resistor R2 and the 1 st pin of the resistor R3;
a3 rd pin of the operational amplifier U1, which serves as an input terminal a1 of the input module 10, and is configured to receive an enable signal a1 output by the enable module 20;
a 4 th pin of the operational amplifier U1, which is used as a power input terminal of the input module 10, is connected to an output terminal VDD of the power module 40, and is configured to receive a dc power supply VDD;
the 4 th pin of the operational amplifier U1 is also connected with the 1 st pin of the resistor R2;
a1 st pin of the resistor R2, which is used as a power input terminal of the input module 10, is connected to an output terminal VDD of the power module 40, and is configured to receive a dc power supply VDD;
the 5 th pin of the operational amplifier U1 is connected with a ground terminal GND;
the 2 nd pin of the resistor R3 is connected with the ground terminal GND;
the 6 th pin of the operational amplifier U1, which is used as the output terminal of the input module 10, is connected to the input terminal a2 of the output module 30, and is used for providing the input signal a2 with different states to the output module 30, so as to control the change of the detection output signal Vo of the output module 30.
It should be noted that the 3 rd pin of the operational amplifier U1 is an off mode enable, and when the off mode enable is at a high level, the operational amplifier U1 is disabled, and the output terminal (i.e., the 6 th pin) of the operational amplifier U1 is at a high impedance state; when the off mode enable terminal is at low level, the operational amplifier U1 is activated, so that the signal state of the output terminal (i.e. the 6 th pin) of the operational amplifier U1 changes correspondingly with the state of the input terminal signal Vin, that is, when the input signal Vin is detected to be at high level, the output terminal (i.e. the 6 th pin) of the operational amplifier U1 is at low level; when the detection input signal Vin is low, the output terminal (i.e., the 6 th pin) of the operational amplifier U1 is high.
It should be noted that the output of the operational amplifier U1 should be a push-pull output.
In the present invention, in a specific implementation, referring to fig. 2, the enabling module 20 includes: resistors R4-R9 and switching tubes Q1-Q3, wherein:
the 1 st pin of the resistor R4 and the resistor R5, which is used as a first input terminal of the enable module 20, is connected to a detection signal output terminal of the external electronic circuit, and is used for receiving a detection input signal Vin provided by the external electronic circuit;
the 2 nd pin of the resistor R4 is respectively connected with the source S of the switching tube Q1 and the gate G of the switching tube Q2;
the source S of the switch tube Q2 is connected with the 2 nd pin of the resistor R7;
the drain D of the switching tube Q2 is respectively connected with the 1 st pin of the resistor R8 and the base B of the switching tube Q3;
a1 st pin of the resistor R7, serving as a second input terminal of the enable module 20, is connected to the output terminal VDD of the power module 40, and is configured to receive a dc power supply VDD;
the 1 st pin of the resistor R7 is also connected with the 2 nd pin of the resistor R9;
the 2 nd pin of the resistor R8 is connected with the ground terminal GND;
a collector C of the switching tube Q3, serving as an output terminal of the enabling module 20, connected to the input terminal a1 of the input module 10, and configured to output an enabling signal a1 for the input module 10, where the enabling signal a1 is used to control the operational amplifier U1 in the input module 10 to be in a disabled or activated state;
the collector C of the switch tube Q3 is also connected with the 1 st pin of the resistor R9;
the 2 nd pin of the resistor R5 is respectively connected with the 1 st pin of the resistor R6 and the grid G of the switching tube Q1;
the 2 nd pin of the resistor R6 is connected with the ground terminal GND;
the drain D of the switching tube Q1 and the emitter E of the switching tube Q3 are both connected to the ground GND.
In the present invention, in a specific implementation, the operation principle and the operation mode of the enabling module 20 are as follows:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state (suspended state), the gate G of the switch Q1 is pulled down by the resistor R6 to a low potential equal to the ground terminal GND to be turned off, the gate G of the switch Q2 is pulled down by the resistors R4 to R6 to a low potential equal to the ground terminal GND to be turned off, so that the switch Q3 is turned off, the output end of the enable module 20 is pulled up by the resistor R9 to a high potential equal to the power supply VDD, that is, the input end a1 of the input module 10 is at a high level, so that the operational amplifier U1 in the input module 10 is in a disabled state;
when the detection input signal Vin provided by the external electronic circuit is at a high level, the gate G of the switching tube Q1 is turned on by the resistors R5 and R6 providing a bias voltage and a current, so that the gate G of the switching tube Q2 is at a low potential, and the switching tube Q2 is turned on, and then the switching tube Q3 is turned on by the resistors R7 and R8 providing a bias voltage and a current, so that the input end a1 of the input module 10 is at a low level, and the operational amplifier U1 in the input module 10 is activated;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the switching tube Q1 is turned off, the switching tube Q2 is turned on, and the switching tube Q3 is turned on by the bias voltage and current provided by the resistor R7 and the resistor R8, so that the input end a1 of the input module 10 becomes at a low level, and the operational amplifier U1 in the input module 10 is activated.
In the present invention, in a specific implementation, referring to fig. 2, the output module 30 includes: resistors R10-R15 and switching tubes Q4-Q6, wherein:
the 1 st pin of the resistor R10, which is the input terminal a2 of the output module 30, is connected to the output terminal of the input module 10 (specifically, to the 6 th pin of the operational amplifier U1), and is used to receive the output signal a2 provided by the input module 10, where the state of the output signal a2 has three states: high level, low level and high resistance state;
the 1 st pin of the resistor R10 is also connected with the 1 st pin of the resistor R11;
the 2 nd pin of the resistor R10 is connected with the grid G of the switch tube Q4;
the source S of the switch tube Q4 is connected with the 2 nd pin of the resistor R12;
the drain D of the switching tube Q4, which is used as the output Vo of the output module 30, is connected to an input/output port of the detecting chip 50 (such as a single-chip MCU), and is used to provide a detecting output signal Vo for the detecting chip, where the detecting output signal Vo has three states: high level, low level and 0V;
the drain D of the switch tube Q4 is also respectively connected with the 1 st pin of the resistor R13, the emitter E of the switch tube Q5 and the 1 st pin of the resistor R15;
the 2 nd pin of the resistor R11 is respectively connected with the base B of the switch tube Q5 and the base B of the switch tube Q6;
the collector C of the switch tube Q6 is connected with the 2 nd pin of the resistor R15;
an emitter E of the switching tube Q6 is connected with a ground end GND;
the collector C of the switch tube Q5 is connected with the 2 nd pin of the resistor R14;
a1 st pin of the resistor R14, which is used as a power input terminal of the output module 30, is connected to an output terminal VDD of the power module 40, and is configured to receive a dc power supply VDD;
the 1 st pin of the resistor R14 is also connected to the 1 st pin of the resistor R12.
In the present invention, in a specific implementation, the working principle and the working mode of the output module 30 are as follows:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state (suspended state), the operational amplifier U1 in the input module 10 is in a disabled state, and an output end (i.e., the 6 th pin) thereof is in a high-impedance state, i.e., the input end a2 of the output module 30 is in a high-impedance state, then the switching tubes Q4 to Q6 are all turned off, so that the output end Vo of the output module 30 is pulled down by the resistor R13 to 0V equal to the potential of the ground end GND;
the detection chip can correspondingly recognize that the current detection input signal Vin is in a high impedance state according to the detection output signal Vo of 0V.
When the detection input signal Vin provided by the external electronic circuit is at a high level, the operational amplifier U1 in the input module 10 is in an activated state, and a signal at an output end (i.e., the 6 th pin) of the operational amplifier U1 is changed correspondingly along with the state of the detection input signal Vin, that is, the input end a2 of the output module 30 is at a low level, so that the switching tubes Q5 to Q6 are all turned off, and the switching tube Q4 is turned on, so that the output end Vo of the output module 30 is divided by the resistor R12 and the resistor R13 and then becomes a high level;
the detection chip can correspondingly recognize that the current detection input signal Vin is at a high level according to the detection output signal Vo at the high level.
When the detection input signal Vin provided by the external electronic circuit is at a low level, the switching tube Q4 is turned off, and the switching tubes Q5-Q6 are turned on, so that the output Vo of the output module 30 is divided by the resistor R14 and the resistor R15 and then becomes at a low level;
the detection chip can correspondingly recognize that the current detection input signal Vin is at a low level according to the detection output signal Vo at the low level.
It should be noted that, for the present invention, the enable function of the operational amplifier is utilized to convert the three states of the input signal, and three states of the input signal can be represented by one output port, thereby being beneficial to saving the I/O (input/output port) resource of the integrated detection chip or the single chip.
In summary, compared with the prior art, the tri-state input signal detection circuit provided by the invention has a scientific design, can realize that one output port has three-state semaphore, can represent the three states of the input signal through one output port, can remarkably reduce the number of input/output ports of the detection chip (only one input/output port needs to be occupied), saves precious hardware resources of the detection chip, and has great production practice significance.
For the invention, the voltage amplitude of the high and low level of the output port can be flexibly adjusted according to the actual requirement, which is not only convenient for the chip to identify the signal state, but also beneficial to reducing the number of the input and output ports of the detection chip (such as a singlechip) which needs to be occupied.
For the technical scheme of the invention, the hardware circuit design is scientific, the electronic components are of common application models, the model selection is easy, and the components are low in price, so that the technical scheme of the invention has very high practical value and market popularization value.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (7)
1. A circuit for detecting a tri-state input signal, comprising an input module (10), an output module (30), an enable module (20) and a power supply module (40), wherein:
the input end Vin of the input module (10) is connected with the detection signal output end of the external electronic circuit and used for receiving a detection input signal Vin provided by the external electronic circuit;
the power supply input end of the input module (10) is connected with the output end VDD of the power supply module (40) and is used for receiving a direct-current power supply VDD;
the output end of the input module (10) is connected with the input end A2 of the output module (30) and is used for providing input signals A2 with different states for the output module (30) so as to control the change of the output signal Vo of the output module (30);
the first input end of the enabling module (20) is connected with the detection signal output end of the external electronic circuit and is used for receiving a detection input signal Vin provided by the external electronic circuit;
the second input end of the enabling module (20) is connected with the output end VDD of the power supply module (40) and is used for receiving a direct current power supply VDD;
the output end of the enabling module (20) is connected with the input end A1 of the input module (10) and is used for providing an enabling signal A1 for the input module (10);
an input end A2 of the output module (30) is connected with an output end of the input module (10) and is used for receiving an output signal A2 provided by the input module (10);
the power supply input end of the output module (30) is connected with the output end VDD of the power supply module (40) and is used for receiving a direct-current power supply VDD;
the output end Vo of the output module (30) is connected with one input/output port of the detection chip 50 and is used for providing a detection output signal Vo for the detection chip 50;
wherein, the detection output signal Vo has three states: high, low and 0V.
2. A detection circuit of a tri-state input signal as claimed in claim 1, characterized in that the input module (10) comprises: resistors R1-R3 and an operational amplifier U1, wherein:
a1 st pin of the resistor R1, which is used as an input terminal Vin of the input module (10), is connected with a detection signal output terminal of an external electronic circuit, and is used for receiving a detection input signal Vin provided by the external electronic circuit;
a2 nd pin of the resistor R1 is connected with a2 nd pin of the operational amplifier U1, and the 2 nd pin is a signal negative pole input end;
the 1 st pin of the operational amplifier U1 is a signal positive input end of the operational amplifier U1 and is respectively connected with the 2 nd pin of the resistor R2 and the 1 st pin of the resistor R3;
the 3 rd pin of the operational amplifier U1 is used as the input end A1 of the input module (10) and is used for receiving the enable signal A1 output by the enable module (20);
a 4 th pin of the operational amplifier U1 is used as a power supply input end of the input module (10), is connected with an output end VDD of the power supply module (40), and is used for receiving a direct-current power supply VDD;
the 4 th pin of the operational amplifier U1 is also connected with the 1 st pin of the resistor R2;
a1 st pin of the resistor R2 is used as a power supply input end of the input module (10), is connected with an output end VDD of the power supply module (40), and is used for receiving a direct-current power supply VDD;
the 5 th pin of the operational amplifier U1 is connected with a ground terminal GND;
the 2 nd pin of the resistor R3 is connected with the ground terminal GND;
the 6 th pin of the operational amplifier U1 is used as the output end of the input module (10) and is connected with the input end A2 of the output module (30) for providing input signals A2 with different states for the output module (30).
3. The detection circuit of a tri-state input signal according to claim 1, characterized in that the enabling module (20) comprises: resistors R4-R9 and switching tubes Q1-Q3, wherein:
the 1 st pin of the resistor R4 and the resistor R5 is used as a first input end of the enabling module (20), is connected with a detection signal output end of an external electronic circuit, and is used for receiving a detection input signal Vin provided by the external electronic circuit;
the 2 nd pin of the resistor R4 is respectively connected with the source S of the switching tube Q1 and the gate G of the switching tube Q2;
the source S of the switch tube Q2 is connected with the 2 nd pin of the resistor R7;
the drain D of the switching tube Q2 is respectively connected with the 1 st pin of the resistor R8 and the base B of the switching tube Q3;
a1 st pin of the resistor R7, which is used as a second input end of the enabling module (20), is connected with an output end VDD of the power supply module (40) and is used for receiving a direct current power supply VDD;
the 1 st pin of the resistor R7 is also connected with the 2 nd pin of the resistor R9;
the 2 nd pin of the resistor R8 is connected with the ground terminal GND;
a collector C of the switching tube Q3, as an output end of the enabling module (20), is connected to the input end a1 of the input module (10), and is used for outputting an enabling signal a1 for the input module (10), where the enabling signal a1 is used for controlling the operational amplifier U1 in the input module (10) to be in a disabled or activated state;
the collector C of the switch tube Q3 is also connected with the 1 st pin of the resistor R9;
the 2 nd pin of the resistor R5 is respectively connected with the 1 st pin of the resistor R6 and the grid G of the switching tube Q1;
the 2 nd pin of the resistor R6 is connected with the ground terminal GND;
the drain D of the switching tube Q1 and the emitter E of the switching tube Q3 are both connected to the ground GND.
4. A detection circuit of a tri-state input signal as claimed in claim 1, characterized in that the output module (30) comprises: resistors R10-R15 and switching tubes Q4-Q6, wherein:
the 1 st pin of the resistor R10, which is the input terminal a2 of the output module (30), is connected to the output terminal of the input module (10) for receiving the output signal a2 provided by the input module (10), and the state of the output signal a2 has three states: high level, low level and high resistance state;
the 1 st pin of the resistor R10 is also connected with the 1 st pin of the resistor R11;
the 2 nd pin of the resistor R10 is connected with the grid G of the switch tube Q4;
the source S of the switch tube Q4 is connected with the 2 nd pin of the resistor R12;
the drain D of the switching tube Q4, which is the output Vo of the output module (30), is connected to an input/output port of the detecting chip 50, for providing the detecting chip with a detecting output signal Vo, which has three states: high level, low level and 0V;
the drain D of the switch tube Q4 is also respectively connected with the 1 st pin of the resistor R13, the emitter E of the switch tube Q5 and the 1 st pin of the resistor R15;
the 2 nd pin of the resistor R11 is respectively connected with the base B of the switch tube Q5 and the base B of the switch tube Q6;
the collector C of the switch tube Q6 is connected with the 2 nd pin of the resistor R15;
an emitter E of the switching tube Q6 is connected with a ground end GND;
the collector C of the switch tube Q5 is connected with the 2 nd pin of the resistor R14;
a1 st pin of the resistor R14 is used as a power supply input end of the output module (30), is connected with an output end VDD of the power supply module (40), and is used for receiving a direct-current power supply VDD;
the 1 st pin of the resistor R14 is also connected to the 1 st pin of the resistor R12.
5. A circuit for detecting a tri-state input signal as claimed in claim 3, characterized in that the enabling module (20) operates in the following mode:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state, the gate G of the switch tube Q1 is pulled down to a low potential equal to a ground terminal GND by the resistor R6 to be cut off, the gate G of the switch tube Q2 is pulled down to a low potential equal to the ground terminal GND by the resistors R4 to R6 to be cut off, so that the switch tube Q3 is cut off, the output end of the enable module (20) is pulled up to a high potential equal to the power supply VDD by the resistor R9, that is, the input end a1 of the input module (10) is at a high level, so that the operational amplifier U1 in the input module (10) is in a disabled state;
when a detection input signal Vin provided by an external electronic circuit is at a high level, the gate G of the switching tube Q1 is turned on after being provided with a bias voltage and a current by the resistors R5 and R6, so that the gate G of the switching tube Q2 is at a low potential, and the switching tube Q2 is turned on, and then the switching tube Q3 is turned on by being provided with the bias voltage and the current by the resistor R7 and the resistor R8, so that the input end a1 of the input module (10) is at a low level, and the operational amplifier U1 in the input module (10) is activated;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the switching tube Q1 is turned off, the switching tube Q2 is turned on, and the switching tube Q3 is turned on by the bias voltage and current provided by the resistor R7 and the resistor R8, so that the input end a1 of the input module (10) becomes at a low level, and the operational amplifier U1 in the input module (10) is activated.
6. A detection circuit of a tri-state input signal as claimed in claim 4, characterized in that the mode of operation of the output module (30) is as follows:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state, an operational amplifier U1 in the input module (10) is in a disabled state, and an output end of the operational amplifier U1 is in the high-impedance state, that is, an input end a2 of the output module (30) is in the high-impedance state, the switching tubes Q4 to Q6 are all turned off, so that an output end Vo of the output module (30) is pulled down by a resistor R13 to be 0V equal to the potential of GND (ground);
when a detection input signal Vin provided by an external electronic circuit is at a high level, an operational amplifier U1 in the input module (10) is in an activated state, and a signal at an output end of the operational amplifier U1 is correspondingly changed along with the state of the detection input signal Vin, that is, an input end A2 of the output module (30) is at a low level, so that the switching tubes Q5-Q6 are all turned off, and the switching tube Q4 is turned on, so that an output end Vo of the output module (30) is divided by a resistor R12 and a resistor R13 and then becomes at a high level;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the switch tube Q4 is turned off, and the switch tubes Q5-Q6 are turned on, so that the output Vo of the output module (30) is divided by the resistor R14 and the resistor R15 and then becomes at a low level.
7. A detection circuit for a tri-state input signal according to any of claims 1 to 6, comprising the following modes of operation:
when a detection input signal Vin provided by an external electronic circuit is in a high-impedance state, the enabling module (20) enables an input end A1 of the input module (10) to be in a high level, then the input module (10) is in a forbidden state, and an input end A2 of the output module (30) is in a high-impedance state, so that an output end Vo of the output module (30) is 0V; therefore, the detection chip 50 correspondingly determines that the input detection signal Vin is in a high impedance state according to the detection output signal Vo of 0V;
when the detection input signal Vin provided by the external electronic circuit is at a high level, the enabling module (20) enables the input end A1 of the input module to be at a low level, and activates the input module (10) to enable the signal state of the output end of the input module to change along with the state of the detection input signal Vin; the output end of the input module (10) is at a low level due to the fact that the input signal Vin is detected to be at a high level, and therefore the output end Vo of the output module (30) is at a high level; therefore, the detection chip 50 correspondingly determines that the input detection signal Vin is at a high level according to the high-level detection output signal Vo;
when the detection input signal Vin provided by the external electronic circuit is at a low level, the enabling module (20) enables the input end A1 of the input module to be at a low level, and activates the input module (10) to enable the signal state of the output end of the input module to change along with the state of the detection input signal Vin; the output end of the input module (10) is at a high level due to the fact that the detection input signal Vin is at a low level, and therefore the output end Vo of the output module (30) is at a low level; therefore, the detection chip 50 determines that the input detection signal Vin is at a low level according to the low-level detection output signal Vo.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110579922.2A CN113359016A (en) | 2021-05-26 | 2021-05-26 | Detection circuit for tri-state input signal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110579922.2A CN113359016A (en) | 2021-05-26 | 2021-05-26 | Detection circuit for tri-state input signal |
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Effective date of registration: 20220119 Address after: 266500 Minshan Road, Huangdao District, Qingdao, Shandong Applicant after: LISHEN (QINGDAO) NEW ENERGY CO.,LTD. Address before: 300384 Tianjin Binhai New Area Binhai high tech Industrial Development Zone Huayuan science and Technology Park (outer ring) 38 Haitai South Road Applicant before: LISHEN POWER BATTERY SYSTEMS Co.,Ltd. |