CN216213449U - Silicon carbide power module easy to radiate heat - Google Patents
Silicon carbide power module easy to radiate heat Download PDFInfo
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- CN216213449U CN216213449U CN202122639756.9U CN202122639756U CN216213449U CN 216213449 U CN216213449 U CN 216213449U CN 202122639756 U CN202122639756 U CN 202122639756U CN 216213449 U CN216213449 U CN 216213449U
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Abstract
The utility model discloses a silicon carbide power module easy to radiate heat, which relates to the technical field of semiconductors and comprises a substrate, wherein the topological structure of the power module is a half-bridge structure, the switch positions of an upper bridge arm and a lower bridge arm are respectively formed by connecting a plurality of silicon carbide chips in parallel, and a plurality of grid resistors are distributed on the substrate along a first direction; the silicon carbide chips are locally and symmetrically distributed on two sides of the grid resistors in the second direction, and a grid resistor is connected to the grid of each silicon carbide chip in series; the silicon carbide chips positioned on the same side of the grid resistors are distributed on the substrate in a staggered mode along the first direction. Compared with the prior art, the utility model has the following advantages: the distances among the silicon carbide chips distributed in a staggered manner are pulled, so that the thermal coupling effect is effectively reduced, and the integral heat dissipation capability is improved; the silicon carbide chips distributed in a staggered manner can enable the chip mounting and packaging tool clamp to be manufactured more easily, and packaging difficulty is reduced.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a silicon carbide power module easy to radiate heat.
Background
The multi-chip parallel layout design of the power semiconductor module has very important significance on the current capability of the power module and the overall efficiency of the motor controller of the new energy automobile. The current sharing capability among the power semiconductor devices is improved, and the grid oscillation phenomenon of the semiconductor devices in the switching process is effectively inhibited, so that the current sharing capability among the power semiconductor devices plays a decisive role in the successful use of the advanced silicon carbide power devices. Unreasonable module layout design tends to cause excessive heat loss in individual chips due to the distribution of relatively large amounts of current, which in turn leads to local overheating of the power chips, affecting their maximum output power and service life. In addition, due to the characteristics of high switching speed, small grid capacitance and low charge of the novel silicon carbide power device, grid oscillation among the devices is easily caused by an imperfect chip layout design, so that overhigh electromagnetic interference is caused, and crosstalk and false turn-on phenomena of the devices are caused.
SUMMERY OF THE UTILITY MODEL
The utility model aims to overcome the defects of the background technology and provide a silicon carbide power module with easy heat dissipation.
In a first aspect, a silicon carbide power module with easy heat dissipation is provided, including:
the power module comprises a substrate, a topological structure of the power module is a half-bridge structure and comprises an upper bridge arm and a lower bridge arm, the switch positions of the upper bridge arm and the lower bridge arm are respectively formed by connecting a plurality of silicon carbide chips in parallel, and the power module also comprises:
a plurality of gate resistors distributed on the substrate along a first direction;
the silicon carbide chips are locally and symmetrically distributed on two sides of the grid resistors in the second direction, and one grid resistor is connected to the grid of each silicon carbide chip in series;
the silicon carbide chips positioned on the same side of the grid resistors are distributed on the substrate in a staggered mode along a first direction.
Furthermore, an upper bridge area and a lower bridge area which are distributed along the first direction are arranged on the substrate;
the upper bridge area is internally provided with a first upper bridge area, a first resistance area and a second upper bridge area which are sequentially distributed at intervals along the second direction;
the lower bridge area is internally provided with a first lower bridge area, a second resistance area and a second lower bridge area which are sequentially distributed at intervals along the second direction;
a plurality of silicon carbide chips distributed along the first direction in a staggered manner are arranged in the first upper bridge region, the second upper bridge region, the first lower bridge region and the second lower bridge region respectively;
the first resistance region and the second resistance region are respectively provided with a plurality of grid resistors distributed along the first direction.
Further, the pitches of two adjacent silicon carbide chips in the first direction in the first upper bridge region, the second upper bridge region, the first lower bridge region or the second lower bridge region are the same.
Preferably, the distance between two adjacent silicon carbide chips in the first direction in the first upper bridge region, the second upper bridge region, the first lower bridge region or the second lower bridge region is 1.5 mm.
Preferably, the dislocation distance of two silicon carbide chips adjacent to each other in the first direction in the first upper bridge region, the second upper bridge region, the first lower bridge region or the second lower bridge region in the second direction is greater than 1 mm.
Further, the first resistance region and the second resistance region are distributed along the first direction in a staggered manner.
Furthermore, 3 silicon carbide chips are respectively arranged in the first upper bridge region, the second upper bridge region, the first lower bridge region and the second lower bridge region; and 6 grid resistors are respectively arranged in the first resistor area and the second resistor area.
Preferably, the length of the substrate in the first direction is 63.5mm, and the length of the substrate in the second direction is 44.5 mm.
Further, the silicon carbide power module further comprises an input terminal positive electrode and an input terminal negative electrode disposed at one end of the substrate and a power output terminal disposed at the other end of the substrate.
Preferably, the substrate is further provided with a connection line for connecting the gate resistor and the silicon carbide chip.
Compared with the prior art, the utility model has the following advantages:
1. the plurality of silicon carbide chips are distributed on the substrate in a staggered manner along the first direction, so that the distance between the silicon carbide chips distributed in the staggered manner is shortened, the thermal coupling effect is effectively reduced, and the integral heat dissipation capability is improved;
2. compared with alignment arrangement, the silicon carbide chips distributed in a staggered manner can enable the chip mounting and packaging tool clamp to be manufactured more easily, and packaging difficulty is reduced;
3. the silicon carbide chips are locally and symmetrically distributed on two sides of the grid resistors in the second direction, so that the inconsistency of parasitic parameters of different chips is reduced to the greatest extent;
4. the grid resistor is connected in series with the grid of each silicon carbide chip, so that the impedance between the grids of the silicon carbide chips is increased, and the problem of electromagnetic compatibility caused by rapid switching of the silicon carbide power device is suppressed to the greatest extent.
Drawings
Fig. 1 is a schematic perspective view of a silicon carbide power module with easy heat dissipation according to an embodiment of the present invention;
FIG. 2 is a schematic top view of the structure of FIG. 1;
fig. 3 is a schematic structural view of fig. 2 with the connecting lines removed.
In the figure: 10-a substrate; 11-a first upper bridge region; 12-a first resistive region; 13-a second upper bridge region; 14-a first lower bridge region; 15-a second resistive region; 16-a second underbridge region; 20-silicon carbide chips; 30-gate resistance; 40-connecting lines; 50-positive input terminal; 60-input terminal negative pole; 70-power output terminal.
Detailed Description
Reference will now be made in detail to the present embodiments of the utility model, examples of which are illustrated in the accompanying drawings. While the utility model will be described in conjunction with the specific embodiments, it will be understood that they are not intended to limit the utility model to the embodiments described. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the utility model as defined by the appended claims. It should be noted that the method steps described herein may be implemented by any functional block or functional arrangement, and that any functional block or functional arrangement may be implemented as a physical entity or a logical entity, or a combination of both.
In order that those skilled in the art will better understand the present invention, the following detailed description of the utility model is provided in conjunction with the accompanying drawings and the detailed description of the utility model.
Note that: the example to be described next is only a specific example, and does not limit the embodiments of the present invention necessarily to the following specific steps, values, conditions, data, orders, and the like. Those skilled in the art can, upon reading this specification, utilize the concepts of the present invention to construct more embodiments than those specifically described herein.
Unreasonable module layout design tends to cause excessive heat loss in individual chips due to the distribution of relatively large amounts of current, which in turn leads to local overheating of the power chips, affecting their maximum output power and service life. In addition, due to the characteristics of high switching speed, small grid capacitance and low charge of the novel silicon carbide power device, grid oscillation among the devices is easily caused by an imperfect chip layout design, so that overhigh electromagnetic interference is caused, and crosstalk and false turn-on phenomena of the devices are caused.
Referring to fig. 1 and 2, an embodiment of the utility model provides an easy-to-dissipate silicon carbide power module, which includes a substrate 10, a half-bridge topology of the power module, and a plurality of silicon carbide chips 20 connected in parallel at switch positions of an upper bridge arm and a lower bridge arm, and further includes a plurality of gate resistors 30, an input terminal anode 50 and an input terminal cathode 60 disposed at one end of the substrate 10, and a power output terminal 70 disposed at the other end of the substrate 10.
The gate resistors 30 are distributed on the substrate 10 along a first direction (i.e., a length direction of the substrate 10 or an input-to-output direction of the substrate 10).
The silicon carbide chips 20 are locally and symmetrically distributed on both sides of the gate resistors 30 in the second direction (i.e., the width direction of the substrate 10), and one gate resistor 30 is connected in series to each gate of the silicon carbide chips 20.
The silicon carbide chips 20 located on the same side as the gate resistors 30 are distributed on the substrate 10 in a staggered manner in the first direction.
As shown in fig. 3, the substrate 10 is provided with upper and lower bridge regions distributed in a first direction.
The upper bridge area is internally provided with a first upper bridge area 11, a first resistance area 12 and a second upper bridge area 13 which are sequentially distributed at intervals along the second direction.
The lower bridge region is internally provided with a first lower bridge region 14, a second resistance region 15 and a second lower bridge region 16 which are sequentially distributed at intervals along the second direction.
A plurality of silicon carbide chips 20 distributed in a staggered manner along the first direction are respectively arranged in the first upper bridge region 11, the second upper bridge region 13, the first lower bridge region 14 and the second lower bridge region 16.
A plurality of gate resistors 30 distributed in the first direction are disposed in the first resistance region 12 and the second resistance region 15, respectively.
It should be noted that the first upper bridge region 11, the second upper bridge region 13, the first lower bridge region 14, the second lower bridge region 16, the first resistance region 12 and the second resistance region 15 may be only marking regions printed on the substrate 10, and do not affect the arrangement of the circuit, and only serve as marks to facilitate the mounting of the silicon carbide chip 20 and the gate resistor 30. The size of each region is designed according to the number and size of the silicon carbide chips 20 or the gate resistors 30 mounted in each region. The edge profiles of the above-mentioned zones may also be discontinuous, and in the case of the first upper bridge zone 11, the first upper bridge zone 11 is not a fully enclosed zone.
In one embodiment, the pitch of two silicon carbide chips 20 adjacent in the first direction within the first upper bridge region 11, the second upper bridge region 13, the first lower bridge region 14, or the second lower bridge region 16 is the same. Preferably, the spacing is 1.5mm in this embodiment.
In one embodiment, the dislocation pitch in the second direction of two silicon carbide chips 20 adjacent in the first direction within the first upper bridge region 11, the second upper bridge region 13, the first lower bridge region 14, or the second lower bridge region 16 is greater than 1 mm. For example, the chip Q1, the chip Q2 and the chip Q3 are disposed in the first upper bridge region 11 along the first direction, and the offset pitch of the chip Q1 and the chip Q2 in the second direction is greater than 1mm, the offset pitch in this embodiment is 2.59mm, and the offset pitch of the chip Q2 and the chip Q3 in the second direction is also 2.59 mm. Of course, in one embodiment, the misalignment pitch of the chip Q1 and the chip Q2 is not necessarily the same as the misalignment pitch of the chip Q2 and the chip Q3. For example, the chip Q1 and the chip Q2 have a misalignment pitch of 1.1mm, and the chip Q2 and the chip Q3 have a misalignment pitch of 2.81 mm.
The first resistive regions 12 and the second resistive regions 15 are distributed along the first direction in a staggered manner. The first resistance region 12 and the second resistance region 15 are each a rectangular region whose length direction is arranged in the first direction. But the first resistive segment 12 and the second resistive segment 15 are spaced apart in the second direction.
The total number of gate resistors 30 in the first resistor region 12 is equal to the sum of the number of silicon carbide chips 20 in the first upper bridge region 11 and the second upper bridge region 13.
Correspondingly, the total number of gate resistors 30 in the second resistor region 15 is equal to the sum of the number of silicon carbide chips 20 in the first and second lower bridge regions 14 and 16.
In one embodiment, 3 silicon carbide chips 20 are disposed within the first upper bridge region 11, the second upper bridge region 13, the first lower bridge region 14, and the second lower bridge region 16, respectively. The first resistance region 12 and the second resistance region 15 are provided therein with 6 gate resistors 30, respectively. Of course, the number of silicon carbide chips 20 and the number of gate resistors 30 in the silicon carbide power module of the present embodiment are not limited to the above numbers, and may be other numbers, and the present embodiment is not particularly limited thereto.
In one embodiment, the length of the substrate 10 in the first direction is 63.5mm and the length of the substrate 10 in the second direction is 44.5 mm.
In one embodiment, the substrate 10 is further provided with a connection line 40 for connecting the gate resistor 30 and the silicon carbide chip 20.
In addition, compared with the Si IGBT, the SiC MOSFET has a very small gate charge, so that theoretically, the switching speed can be about one hundred times that of the Si IGBT, and in combination with the unipolar characteristic of the MOSFET, the SiC MOSFET has no significant long tail effect, and can very effectively reduce the switching loss of the device. On the other hand, due to the optimization of the on-resistance of the device, the threshold switching voltage of the device is often designed to be between 2V and 4V, which is significantly reduced compared with the 6V of the traditional Si IGBT device. The SiC MOSFET device is very easy to be influenced by electromagnetic interference to cause false turn-on, thereby causing the straight-through short circuit of the bridge arm. This is a significant consideration in the layout design of the power module. In the silicon carbide power module of the embodiment, the patch type gate resistor 30 connected with the silicon carbide chip 20 in series is arranged on the substrate 10, so that the oscillation effect caused by the switching process of different devices is isolated outside the devices in an R-L-C manner, and the crosstalk resistance of gate signals is enhanced.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
It is to be noted that, in the present invention, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The utility model provides an easy radiating carborundum power module, includes the base plate, and power module's topological structure is the half-bridge structure, includes upper bridge arm and lower bridge arm, and the switching position department of upper bridge arm and lower bridge arm is parallelly connected by a plurality of carborundum chips respectively and is formed which characterized in that still includes:
a plurality of gate resistors distributed on the substrate along a first direction;
the silicon carbide chips are locally and symmetrically distributed on two sides of the grid resistors in the second direction, and one grid resistor is connected to the grid of each silicon carbide chip in series;
the silicon carbide chips positioned on the same side of the grid resistors are distributed on the substrate in a staggered mode along a first direction.
2. The silicon carbide power module with easy heat dissipation according to claim 1, wherein the substrate is provided with upper and lower bridge regions distributed along the first direction;
the upper bridge area is internally provided with a first upper bridge area, a first resistance area and a second upper bridge area which are sequentially distributed at intervals along the second direction;
the lower bridge area is internally provided with a first lower bridge area, a second resistance area and a second lower bridge area which are sequentially distributed at intervals along the second direction;
a plurality of silicon carbide chips distributed along the first direction in a staggered manner are arranged in the first upper bridge region, the second upper bridge region, the first lower bridge region and the second lower bridge region respectively;
the first resistance region and the second resistance region are respectively provided with a plurality of grid resistors distributed along the first direction.
3. The heat dissipating silicon carbide power module of claim 2 wherein the first upper bridge region, the second upper bridge region, the first lower bridge region or the second lower bridge region have the same pitch between two silicon carbide chips adjacent in the first direction.
4. The silicon carbide power module with easy heat dissipation according to claim 3, wherein the pitch between two silicon carbide chips adjacent in the first direction in the first upper bridge region, the second upper bridge region, the first lower bridge region, or the second lower bridge region is 1.5 mm.
5. The silicon carbide power module with easy heat dissipation according to claim 3, wherein the dislocation distance of two silicon carbide chips adjacent to each other in the first direction in the first upper bridge region, the second upper bridge region, the first lower bridge region or the second lower bridge region in the second direction is greater than 1 mm.
6. The heat dissipating silicon carbide power module of claim 2, wherein the first resistive region and the second resistive region are distributed with a dislocation in the first direction.
7. The silicon carbide power module with easy heat dissipation as defined in claim 2, wherein 3 silicon carbide chips are disposed in each of the first upper bridge region, the second upper bridge region, the first lower bridge region, and the second lower bridge region; and 6 grid resistors are respectively arranged in the first resistor area and the second resistor area.
8. The heat dissipating silicon carbide power module according to any one of claims 1 to 7, wherein the length of the substrate in the first direction is 63.5mm and the length of the substrate in the second direction is 44.5 mm.
9. The silicon carbide power module with easy heat dissipation according to claim 8, further comprising a positive input terminal and a negative input terminal disposed at one end of the substrate and a power output terminal disposed at the other end of the substrate.
10. The silicon carbide power module with easy heat dissipation as defined in claim 9, wherein a connection line is further disposed on the substrate to connect the gate resistor and the silicon carbide chip.
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| CN202122639756.9U CN216213449U (en) | 2021-10-29 | 2021-10-29 | Silicon carbide power module easy to radiate heat |
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| CN202122639756.9U CN216213449U (en) | 2021-10-29 | 2021-10-29 | Silicon carbide power module easy to radiate heat |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117199065A (en) * | 2023-11-03 | 2023-12-08 | 苏州中瑞宏芯半导体有限公司 | Power semiconductor device module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117199065A (en) * | 2023-11-03 | 2023-12-08 | 苏州中瑞宏芯半导体有限公司 | Power semiconductor device module |
| CN117199065B (en) * | 2023-11-03 | 2024-02-06 | 苏州中瑞宏芯半导体有限公司 | Power semiconductor device module |
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