CN216146261U - Power conversion device, motor drive unit, and electric power steering device - Google Patents

Abstract

The utility model provides a power conversion device, a motor drive unit, and an electric power steering device. A power conversion device according to an embodiment converts power from a power supply into power to be supplied to a motor having n-phase windings, where n is an integer of 3 or more, the power conversion device including: a 1 st inverter connected to one end of each phase winding of the motor; a 2 nd inverter connected to the other end of each phase winding; a control circuit; a drive circuit; and a sub-driver circuit, wherein the 1 st inverter includes a bridge circuit including 3 arms, each arm having a low-side switching element and a high-side switching element, the 2 nd inverter includes a bridge circuit including 3 arms, each arm having a low-side switching element and a high-side switching element, and the sub-driver circuit is connected to the low-side switching element.

Description

Power conversion device, motor drive unit, and electric power steering device

The present application is a divisional application of chinese utility model patent applications having application numbers 201890001125.8(PCT/JP2018/022136), having application dates of 2018, 6 months and 11 days, and having utility model names "power conversion device, motor drive unit, and electric power steering device".

Technical Field

The present disclosure relates to a power conversion device that converts power supplied to an electric motor, a motor drive unit, and an electric power steering device.

Background

Electric motors (hereinafter, simply referred to as "motors") such as brushless DC motors and ac synchronous motors are generally driven by three-phase currents. In order to accurately control the waveform of the three-phase current, a complicated control technique such as vector control is used. Such a control technique requires a high degree of mathematical operation, and uses a digital operation circuit such as a microcontroller (microcomputer). The vector control technology is used in applications where load variation of a motor is large, for example, in the fields of washing machines, electric power-assisted bicycles, electric scooters, electric power steering apparatuses, electric automobiles, industrial equipment, and the like. On the other hand, in a motor having a relatively small output, another motor control method such as a Pulse Width Modulation (PWM) method is used.

In the field of vehicles, an Electronic Control Unit (ECU) for an automobile is used in the vehicle. The ECU includes a microcontroller, a power supply, an input/output circuit, an AD converter, a load drive circuit, a ROM (Read Only Memory), and the like. An electronic control system is built by taking an ECU as a core. For example, the ECU processes signals from sensors to control actuators such as motors. Specifically, the ECU controls the inverter in the power conversion device while monitoring the rotation speed or torque of the motor. The power conversion device converts the drive power supplied to the motor under the control of the ECU.

In recent years, an electromechanical motor in which a motor, a power conversion device, and an ECU are integrated has been developed. In the field of vehicle mounting in particular, it is required to ensure high quality from the viewpoint of safety. Therefore, a redundant design is introduced which can continue to operate safely even in the event of a failure of a part of the component. As an example of the redundant design, it is studied to provide 2 power conversion devices for 1 motor. As another example, it is studied to provide a backup microcontroller for the main microcontroller.

For example, patent document 1 discloses a power conversion device that has a control unit and 2 inverters and converts power supplied to a three-phase motor. The 2 inverters are connected to a power supply and a ground (hereinafter referred to as "GND"), respectively. One inverter is connected to one end of the three-phase winding of the motor, and the other inverter is connected to the other end of the three-phase winding. Each inverter has a bridge circuit composed of 3 legs, and each of the 3 legs includes a high-side switching device and a low-side switching device. When a failure of a switching element in 2 inverters is detected, the control unit switches the motor control from normal control to abnormal control. In the present specification, "abnormality" mainly refers to a failure of a switching element. The "normal control" refers to control in which all the switching elements are in a normal state, and the "abnormal control" refers to control in a state in which a failure has occurred in any one of the switching elements.

In the control at the time of an abnormality, in an inverter including a switching element that has a failure (hereinafter, referred to as a "failed inverter") among 2 inverters, a neutral point of a winding is formed by turning on/off the switching element according to a predetermined rule. According to this rule, for example, when an open failure occurs in which the high-side switching device is always off, the switching devices other than the failed switching device among the 3 high-side switching devices are turned off and the 3 low-side switching devices are turned on in the bridge circuit of the inverter. In this case, a neutral point is formed on the low side. Alternatively, when a short-circuit fault occurs in which the high-side switching device is always on, the switching devices other than the failed switching device among the 3 high-side switching devices are turned on and the 3 low-side switching devices are turned off in the bridge circuit of the inverter. In this case, a neutral point is formed on the high side. According to the power conversion device of patent document 1, in the event of an abnormality, the neutral point of the three-phase winding is configured in the faulty inverter. Even if the switching element fails, the motor can be continuously driven using the normal inverter.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2014-192950

Patent document 2: japanese patent laid-open publication No. 2017 and 063571

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

In the apparatus for driving the motor using 2 inverters as described above, when the inverter fails, it is required to identify a failure site.

Patent document 2 discloses a device for driving a motor having windings Y-wired by 1 inverter. Patent document 2 discloses the following technique: a signal detected in a predetermined power-on mode is checked against a predetermined abnormality type correspondence table to detect disconnection and short-circuiting of the wiring.

However, in the technique of patent document 2, when a switching element included in the inverter fails, it is not possible to determine which switching element of the plurality of switching elements has failed.

In an apparatus that drives a motor using 2 inverters, when a switching element fails, it is required to determine which switching element of a plurality of switching elements has failed.

Embodiments of the present disclosure provide a power conversion apparatus capable of determining which switching element of a plurality of switching elements is malfunctioning in the event of a failure of a switching element.

Means for solving the problems

An exemplary power conversion device (100) of the present disclosure converts power from a power source (101) into power supplied to a motor (200) having n-phase windings, where n is an integer of 3 or more, wherein the power conversion device has: a 1 st inverter (120) connected to one end of each phase winding of the motor; a 2 nd inverter (130) connected to the other end of each phase winding; a control circuit (300); a drive circuit (350); and a sub-driver circuit (160L), wherein the 1 st inverter (120) includes a bridge circuit including 3 arms, each arm has low-side switching elements (121L to 123L) and high-side switching elements (121H to 123H), the 2 nd inverter (130) includes a bridge circuit including 3 arms, each arm has low-side switching elements (131L to 133L) and high-side switching elements (131H to 133H), and the sub-driver circuit (160L) is connected to the low-side switching elements (121L to 123L).

Another exemplary power conversion device of the present disclosure converts power from a power source (101) into power to be supplied to a motor (200) having n-phase windings, where n is an integer of 3 or more, wherein the power conversion device (100) has: a 1 st inverter (120) connected to one end of each phase winding of the motor; a 2 nd inverter (130) connected to the other end of each phase winding; a control circuit (300); a drive circuit (350); and a sub-drive circuit (170L), wherein the 1 st inverter (120) includes a bridge circuit including 3 arms, each arm has low-side switching elements (121L to 123L) and high-side switching elements (121H to 123H), the 2 nd inverter (130) includes a bridge circuit including 3 arms, each arm has low-side switching elements (131L to 133L) and high-side switching elements (131H to 133H), and the sub-drive circuit (170L) is connected to the low-side switching elements (121L to 123L) and the high-side switching elements (121H to 123H).

An exemplary motor drive unit of the present disclosure has: the power conversion device described above; and the motor.

An exemplary electric power steering apparatus of the present disclosure includes the motor drive unit described above.

Effect of the utility model

According to the embodiments of the present disclosure, when a switching element included in an inverter fails, which switching element of a plurality of switching elements fails can be determined.

Drawings

Fig. 1 is a circuit diagram showing a circuit configuration of a power conversion device 100 according to an exemplary embodiment 1.

Fig. 2 is a circuit diagram showing another circuit configuration of the power conversion device 100 according to exemplary embodiment 1.

Fig. 3 is a circuit diagram showing another circuit configuration of the power conversion device 100 according to exemplary embodiment 1.

Fig. 4 is a circuit diagram showing another circuit configuration of the power conversion device 100 according to exemplary embodiment 1.

Fig. 5 is a block diagram showing a representative configuration of the motor drive unit 400 having the power conversion device 100.

Fig. 6 is a diagram showing a current waveform (sine wave) obtained by plotting current values flowing through the respective windings of the U-phase, V-phase, and W-phase of the motor 200 when the power conversion device 100 is controlled in accordance with the three-phase energization control.

Fig. 7 is a schematic diagram illustrating the flow of current in the power conversion device 100 when the FETs of the 2 switching circuits 110 and the 1 st inverter 120 are in the 1 st state.

Fig. 8 is a diagram showing a current waveform obtained by plotting current values flowing through the respective windings of the U-phase, V-phase, and W-phase of the motor 200 when the power conversion device 100 is controlled in the 1 st state.

Fig. 9 is a schematic diagram illustrating the flow of current in the power conversion device 100 when the FETs of the 2 switching circuits 110 and the 1 st inverter 120 are in the 3 rd state.

Fig. 10 is a diagram showing an example of an operation of forming a neutral point on the low side to perform failure diagnosis.

Fig. 11 is a diagram showing FETs included in the 1 st and 2 nd inverters 120 and 130.

Fig. 12 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 2 nd inverter 130 in the case where the low side constitutes the neutral point.

Fig. 13 is a diagram for explaining failure diagnosis when the FETs 132H, 133L are turned on.

Fig. 14 is a diagram for explaining failure diagnosis when the FETs 133H, 131L are turned on.

Fig. 15 is a diagram showing an example of an operation of constructing a neutral point on the high side to perform failure diagnosis.

Fig. 16 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 2 nd inverter 130 in the case where the high side constitutes the neutral point.

Fig. 17 is a diagram illustrating failure diagnosis when the FETs 132H, 133L are turned on.

Fig. 18 is a diagram for explaining failure diagnosis when the FETs 133H, 131L are turned on.

Fig. 19 is a diagram showing an example of an operation of forming a neutral point on the low side to perform failure diagnosis.

Fig. 20 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 1 st inverter 120 in a case where the low side of the 2 nd inverter 130 constitutes a neutral point.

Fig. 21 is a diagram illustrating failure diagnosis when the FETs 122H, 123L are turned on.

Fig. 22 is a diagram for explaining failure diagnosis when the FETs 123H, 121L are turned on.

Fig. 23 is a diagram showing an example of an operation of constructing a neutral point on the high side to perform failure diagnosis.

Fig. 24 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 1 st inverter 120 in the case where the high side of the 2 nd inverter 130 constitutes the neutral point.

Fig. 25 is a diagram illustrating failure diagnosis when the FETs 122H, 123L are turned on.

Fig. 26 is a diagram for explaining failure diagnosis when the FETs 123H, 121L are turned on.

Fig. 27 is a circuit diagram schematically showing the power conversion apparatus 100 having the sub-drive circuit 160L.

Fig. 28 is a circuit diagram schematically showing the circuit configuration of the sub-drive circuit 160L.

Fig. 29 is a circuit diagram schematically showing the power conversion apparatus 100 having the sub-drive circuit 160R.

Fig. 30 is a circuit diagram schematically showing the power conversion apparatus 100 having the sub-drive circuit 170L.

Fig. 31 is a circuit diagram schematically showing the circuit configuration of the sub-drive circuit 170L.

Fig. 32 is a circuit diagram schematically showing the power conversion apparatus 100 having the sub-drive circuit 170R.

Fig. 33 is a schematic diagram showing a typical configuration of an electric power steering apparatus 500 according to exemplary embodiment 2.

Description of the reference symbols

100: a power conversion device; 101: a power source; 102: a coil; 103: a capacitor; 110: a switching circuit; 111: a switching element (FET); 112: a switching element (FET); 113: a switching element (FET); 114: a switching element (FET); 115: a switching element (FET); 116: a switching element (FET); 120: 1 st inverter; 121H, 122H, 123H: a high-side switching element (FET); 121L, 122L, 123L: a low-side switching element (FET); 121R, 122R, 123R: a shunt resistor; 130: a 2 nd inverter; 131H, 132H, 133H: a high-side switching element (FET); 131L, 132L, 133L: a low-side switching element (FET); 131R, 132R, 133R: a shunt resistor; 140: a diode; 150: a current sensor; 160L, 160R: a sub-driving circuit; 161. 162: a switching circuit; 170L, 170R: a sub-driving circuit; 171. 172: a switching circuit; 200: an electric motor; 300: a control circuit; 310: a power supply circuit; 320: an angle sensor; 330: an input circuit; 340: a microcontroller; 350: a drive circuit; 360: a ROM; 370: a boost circuit; 380: a voltage detection circuit; 400: a motor drive unit; 500: an electric power steering apparatus.

Detailed Description

Hereinafter, embodiments of the power conversion device, the motor drive unit, and the electric power steering device according to the present disclosure will be described in detail with reference to the drawings. However, unnecessary detailed description may be omitted. For example, detailed descriptions of known matters and repetitive descriptions of substantially the same structure may be omitted. This is to avoid unnecessary redundancy in the following description, which will be readily understood by those skilled in the art.

In the present specification, an embodiment of the present disclosure will be described by taking as an example a power conversion device that converts power supplied to a three-phase motor having three-phase (U-phase, V-phase, W-phase) windings. However, a power conversion device that converts power supplied to an n-phase motor having four-phase or five-phase (n is an integer of 4 or more) windings is also within the scope of the present disclosure.

(embodiment mode 1)

Fig. 1 schematically shows a circuit configuration of a power conversion device 100 of the present embodiment.

The power conversion apparatus 100 includes 2 switching circuits 110, a 1 st inverter 120, and a 2 nd inverter 130. The power conversion apparatus 100 can convert power supplied to various motors. The motor 200 is a three-phase ac motor.

The motor 200 has a U-phase winding M1, a V-phase winding M2, and a W-phase winding M3, and is connected to the 1 st inverter 120 and the 2 nd inverter 130. Specifically, the 1 st inverter 120 is connected to one end of each phase winding of the motor 200, and the 2 nd inverter 130 is connected to the other end of each phase winding. In the specification of the present application, "connection" of components (constituent elements) to each other mainly means electrical connection. The 1 st inverter 120 has terminals U _ L, V _ L and W _ L corresponding to each, and the 2 nd inverter 130 has terminals U _ R, V _ R and W _ R corresponding to each.

The terminal U _ L of the 1 st inverter 120 is connected to one end of the U-phase winding M1, the terminal V _ L is connected to one end of the V-phase winding M2, and the terminal W _ L is connected to one end of the W-phase winding M3. Similarly to the 1 st inverter 120, the terminal U _ R of the 2 nd inverter 130 is connected to the other end of the U-phase winding M1, the terminal V _ R is connected to the other end of the V-phase winding M2, and the terminal W _ R is connected to the other end of the W-phase winding M3. Such wiring with the motor is different from so-called star wiring and delta wiring.

The 2 switching circuits 110 have switching elements 111, 112, 113, and 114. In the present specification, the GND-side switching circuit 110 provided with the switching elements 111 and 112 among the 2 switching circuits 110 is referred to as a "GND-side switching circuit", and the power-supply-side switching circuit 110 provided with the switching elements 113 and 114 is referred to as a "power-supply-side switching circuit". That is, the GND side switching circuit has switching elements 111 and 112, and the power supply side switching circuit has switching elements 113 and 114.

In the power conversion apparatus 100, the 1 st inverter 120 and the 2 nd inverter 130 can be electrically connected to the power source 101 and GND through 2 switching circuits 110.

Specifically, the switching element 111 switches connection/disconnection between the 1 st inverter 120 and GND. The switching element 112 switches connection/disconnection between the 2 nd inverter 130 and GND. The switching element 113 switches connection/disconnection between the power source 101 and the 1 st inverter 120. The switching element 114 switches connection/disconnection between the power source 101 and the 2 nd inverter 130.

The on/off of the switching elements 111, 112, 113, and 114 can be controlled by a microcontroller or a dedicated driver, for example. The switching elements 111, 112, 113, and 114 can cut off bidirectional current. As the switching elements 111, 112, 113, and 114, for example, semiconductor switches such as thyristors and analog switching ICs, mechanical relays, and the like can be used. A combination of diodes and Insulated Gate Bipolar Transistors (IGBTs) or the like may also be used. However, the switching element of the present disclosure includes a semiconductor switch such as a field effect transistor (typically, MOSFET) in which a parasitic diode is formed. Hereinafter, an example in which FETs are used as the switching elements 111, 112, 113, and 114 will be described, and the switching elements 111, 112, 113, and 114 will be referred to as FETs 111, 112, 113, and 114, respectively.

The FETs 111, 112 have parasitic diodes 111D, 112D, respectively, and are arranged such that the parasitic diodes 111D, 112D face the 1 st and 2 nd inverters 120, 130, respectively. In more detail, the FET111 is configured to flow a forward current in the parasitic diode 111D toward the 1 st inverter 120, and the FET112 is configured to flow a forward current in the parasitic diode 112D toward the 2 nd inverter 130.

The number of switching elements to be used is not limited to the illustrated example, and is determined as appropriate in consideration of design specifications and the like. In particular, in the field of vehicle mounting, it is required to ensure high quality from the viewpoint of safety, and therefore it is preferable to provide a plurality of switching elements as inverters in the power supply side switching circuit and the GND side switching circuit.

Fig. 2 schematically shows another circuit configuration of the power conversion device 100 of the present embodiment.

The power supply side switching circuit 110 may further include a switching element (FET)115 and a switching element (FET)116 for reverse connection protection. The FETs 113, 114, 115, and 116 have parasitic diodes, and are arranged such that the directions of the parasitic diodes in the FETs are opposite to each other. Specifically, the FET113 is configured to flow a forward current toward the power source 101 in the parasitic diode, and the FET115 is configured to flow a forward current toward the 1 st inverter 120 in the parasitic diode. The FET114 is configured to flow a forward current in the parasitic diode toward the power source 101, and the FET116 is configured to flow a forward current in the parasitic diode toward the 2 nd inverter 130. Even when the power source 101 is reversely connected, the reverse current can be cut off by the 2 FETs for reverse connection protection.

The power supply 101 generates a predetermined power supply voltage. A dc power supply is used as the power supply 101, for example. However, the power source 101 may be an AC-DC converter, a DC-DC converter, or a battery (secondary battery).

The power source 101 may be a single power source common to the 1 st and 2 nd inverters 120 and 130, or may include the 1 st power source for the 1 st inverter 120 and the 2 nd power source for the 2 nd inverter 130.

A coil 102 is provided between the power source 101 and the power source side switching current. The coil 102 functions as a noise filter for smoothing high-frequency noise included in a voltage waveform supplied to each inverter or high-frequency noise generated in each inverter so as not to flow out to the power supply 101. A capacitor 103 is connected between the power supply 101 and each inverter. In the illustrated example, a capacitor 103 is connected between the coil 102 and the power supply side switching circuit 110. The capacitor 103 is a so-called bypass capacitor, and suppresses voltage ripple. The capacitor 103 is, for example, an electrolytic capacitor, and the capacity and the number used are appropriately determined in accordance with design specifications and the like.

The 1 st inverter 120 (sometimes referred to as "bridge circuit L") includes a bridge circuit composed of 3 legs. Each branch has a low-side switching element and a high-side switching element. The switching elements 121L, 122L, and 123L shown in fig. 1 are low-side switching elements, and the switching elements 121H, 122H, and 123H are high-side switching elements. As the switching element, for example, an FET or an IGBT can be used. Hereinafter, an example using an FET as a switching element will be described, and the switching element may be referred to as an FET. For example, the switching elements 121L, 122L, and 123L are denoted as FETs 121L, 122L, and 123L.

The 1 st inverter 120 includes 3 shunt resistors 121R, 122R, and 123R as current sensors for detecting currents flowing through the phase windings of the U-phase, the V-phase, and the W-phase (see fig. 5). The current sensor 150 includes a current detection circuit (not shown) that detects a current flowing through each shunt resistor. For example, shunt resistors 121R, 122R, and 123R are connected between 3 low-side switching devices included in 3 branches of the 1 st inverter 120 and ground, respectively. Specifically, the shunt resistor 121R is electrically connected between the FET121L and the FET111, the shunt resistor 122R is electrically connected between the FET122L and the FET111, and the shunt resistor 123R is electrically connected between the FET123L and the FET 111. The resistance value of the shunt resistor is, for example, about 0.5m Ω to 1.0m Ω.

Like the 1 st inverter 120, the 2 nd inverter 130 (sometimes referred to as a "bridge circuit R") includes a bridge circuit including 3 legs. FETs 131L, 132L, and 133L shown in fig. 1 are low-side switching elements, and FETs 131H, 132H, and 133H are high-side switching elements. The 2 nd inverter 130 has 3 shunt resistors 131R, 132R, and 133R. These shunt resistors are connected between the 3 low-side switching elements included in the 3 branches and ground. The FETs of the 1 st and 2 nd inverters 120 and 130 can be controlled by a microcontroller or a dedicated driver, for example.

Fig. 1 illustrates a configuration in which 1 shunt resistor is disposed in each branch of each inverter. However, the 1 st and 2 nd inverters 120 and 130 may have 6 or less shunt resistors. For example, the shunt resistors of 6 or less can be connected between the low-side switching devices of 6 or less in the 6 legs included in the 1 st and 2 nd inverters 120 and 130 and GND. Further, if this is extended to an n-phase motor, the 1 st and 2 nd inverters 120 and 130 can have 2n or less shunt resistances. For example, 2n or less shunt resistors can be connected between 2n or less low-side switching devices in 2n branches included in the 1 st and 2 nd inverters 120 and 130 and GND.

Fig. 3 and 4 schematically show another circuit configuration of the power conversion device 100 according to the present embodiment.

As shown in fig. 3, 3 shunt resistors may be disposed between each branch of the 1 st inverter 120 or the 2 nd inverter 130 and the windings M1, M2, and M3. For example, shunt resistors 121R, 122R, and 123R may be disposed between the 1 st inverter 120 and one end of the windings M1, M2, and M3. For example, although not shown, the shunt resistors 121R and 122R may be disposed between the 1 st inverter 120 and one ends of the windings M1 and M2, and the shunt resistor 123R may be disposed between the 2 nd inverter 130 and the other end of the winding M3. In such a configuration, it is sufficient to arrange 3 shunt resistors for the U-phase, the V-phase, and the W-phase, and it is sufficient to arrange a minimum of 2 shunt resistors.

As shown in fig. 4, for example, 1 shunt resistor may be provided in each inverter in common with each phase winding. One shunt resistor can be electrically connected between a node N1 (connection point of each branch) on the low side of the 1 st inverter 120 and the FET111, for example, and the other shunt resistor can be electrically connected between a node N2 on the low side of the 2 nd inverter 130 and the FET112, for example.

Alternatively, one shunt resistor is electrically connected between the high-side node N3 of the 1 st inverter 120 and the FET113, and the other shunt resistor is electrically connected between the high-side node N4 of the 2 nd inverter 130 and the FET114, for example, as in the low side. In this way, the number of shunt resistors to be used and the arrangement of the shunt resistors are appropriately determined in consideration of product cost, design specifications, and the like.

Fig. 5 schematically shows a representative block structure of the motor drive unit 400 having the power conversion apparatus 100.

The motor drive unit 400 includes the power conversion device 100 and the motor 200. The power conversion apparatus 100 has a control circuit 300. The control circuit 300 may be provided as a component separate from the power converter 100.

The control circuit 300 has, for example, a power supply circuit 310, an angle sensor 320, an input circuit 330, a microcontroller 340, a drive circuit 350, and a ROM 360. The control circuit 300 is connected to the power conversion device 100, and controls the power conversion device 100 to drive the motor 200.

Specifically, the control circuit 300 can control the position, the rotation speed, the current, and the like of the target rotor to realize closed-loop control. The control circuit 300 may include a torque sensor instead of the angle sensor. In this case, the control circuit 300 can control the target motor torque.

The power supply circuit 310 generates DC voltages (e.g., 3V, 5V) necessary for respective blocks in the circuit. The angle sensor 320 is, for example, a resolver or a hall IC. The angle sensor 320 detects a rotation angle of the rotor of the motor 200 (hereinafter, referred to as a "rotation signal"), and outputs the rotation signal to the microcontroller 340. The input circuit 330 receives a motor current value (hereinafter, referred to as "actual current value") detected by the current sensor 150, converts the level of the actual current value into an input level of the microcontroller 340 as necessary, and outputs the actual current value to the microcontroller 340.

The microcontroller 340 controls the switching operation (on or off) of each FET in the 1 st and 2 nd inverters 120 and 130 of the power conversion apparatus 100. The microcontroller 340 sets a target current value in accordance with an actual current value, a rotor rotation signal, and the like, generates a PWM signal, and outputs the PWM signal to the drive circuit 350. The microcontroller 340 can control on/off of each FET in the 2 switching circuits 110 of the power conversion apparatus 100.

The driving circuit 350 is representatively a gate driver. The drive circuit 350 generates a control signal (gate control signal) for controlling the switching operation of each FET in the 1 st and 2 nd inverters 120 and 130 in accordance with the PWM signal, and supplies the control signal to the gate of each FET. The drive circuit 350 can generate a control signal (gate control signal) for controlling on/off of each FET in the 2 switching circuits 110 in accordance with an instruction from the microcontroller 340, and supply the control signal to the gate of each FET.

The driver circuit 350 has a booster circuit 370. The booster circuit 370 boosts the voltage supplied from the power supply 101. For example, in the case where the output voltage of the power supply 101 is 12V, the voltage-boosting circuit 370 boosts its voltage to 18V, or to 24V. The boosted voltage can be used for controlling the switching operation of each FET in the 1 st and 2 nd inverters 120 and 130 or controlling the on/off of each FET in the 2 switching circuits 110. The driving circuit 350 may be a charge pump system or a bootstrap circuit system. The booster circuit 370 may be of a charge pump type.

The driving circuit 350 has a voltage detection circuit 380. The voltage detection circuit 380 detects, for example, a source-drain voltage of each FET included in the 1 st and 2 nd inverters 120 and 130. Then, for example, as described later, the voltages of the U-phase, the V-phase, and the W-phase are detected.

In addition, the microcontroller may be caused to perform control of the FETs of the 2 switching circuits 110. In addition, the microcontroller 340 may also have the function of the driving circuit 350. In this case, the control circuit 300 may not have the driving circuit 350.

The ROM360 is, for example, a writable memory, a rewritable memory, or a read-only memory. The ROM360 stores a control program containing a command set for causing the microcontroller 340 to control the power conversion apparatus 100. For example, the control program is temporarily loaded into a RAM (not shown) at the time of startup.

The power conversion device 100 has normal control and abnormal control. The control circuit 300 (mainly, the microcontroller 340) can switch the control of the power conversion device 100 from the control at the normal time to the control at the abnormal time. The on/off state of each FET in the 2 switching circuits 110 is determined according to the failure mode of the FET. Further, the on/off state of each FET in the faulty inverter is also determined.

(1. control in normal times)

First, a specific example of a normal-time control method of the power conversion device 100 will be described. As described above, the normal state refers to a state in which the FETs of the 1 st and 2 nd inverters 120 and 130 are not failed and the FETs in the 2 switching circuits 110 are not failed.

In a normal state, the control circuit 300 turns on all of the FETs 111, 112, 113, and 114 of the 2 switching circuits 110. Thereby, power source 101 is electrically connected to 1 st inverter 120, and power source 101 is electrically connected to 2 nd inverter 130. Also, the 1 st inverter 120 is electrically connected to GND, and the 2 nd inverter 130 is electrically connected to GND. In this connected state, control circuit 300 drives motor 200 by performing three-phase energization control using both 1 st and 2 nd inverters 120 and 130. Specifically, control circuit 300 performs three-phase energization control by switching-controlling FETs of 1 st inverter 120 and FETs of 2 nd inverter 130 in mutually opposite phases (phase difference is 180 °). For example, focusing on the H- bridge including FETs 121L, 121H, 131L, and 131H, FET131L is turned off when FET121L is turned on, and FET131L is turned on when FET121L is turned off. Similarly, when FET121H is on, FET131H is off, and when FET121H is off, FET131H is on. The current output from the power supply 101 flows to GND through the high-side switching element, the winding, and the low-side switching element.

Fig. 6 illustrates a current waveform (sine wave) obtained by plotting current values flowing through the respective windings of the U-phase, V-phase, and W-phase of the motor 200 when the power conversion device 100 is controlled in accordance with the three-phase energization control. The horizontal axis represents the motor electrical angle (deg) and the vertical axis represents the current value (A). In the current waveform of fig. 6, the current value is plotted per 30 ° in electrical angle. I is_pkIndicates the maximum current value (peak current value) of each phase)。

Table 1 shows the values of the currents flowing in the terminals of the respective inverters for each electrical angle in the sine wave of fig. 6. Specifically, table 1 shows values of currents flowing in terminals U _ L, V _ L and W _ L of the 1 st inverter 120 (bridge circuit L) per 30 ° electrical angle and values of currents flowing in terminals U _ R, V _ R and W _ R of the 2 nd inverter 130 (bridge circuit R) per 30 ° electrical angle. Here, the direction of the current flowing from the terminal of the bridge circuit L to the terminal of the bridge circuit R is defined as a positive direction for the bridge circuit L. The direction of current flow shown in fig. 6 follows this definition. Further, the direction of the current flowing from the terminal of the bridge circuit R to the terminal of the bridge circuit L is defined as a positive direction for the bridge circuit R. Therefore, the phase difference between the current of the bridge circuit L and the current of the bridge circuit R is 180 °. In Table 1, the current value I₁Is [ (3)^1/2/2〕*I_pkValue of current I₂Is of size I_pk/2。

[ Table 1]

When the electrical angle is 0 °, no current flows in the U-phase winding M1. Size I in V-phase winding M2₁Flows from the bridge circuit R to the bridge circuit L, and has a magnitude of I in the W-phase winding M3₁Flows from the bridge circuit L to the bridge circuit R.

At an electrical angle of 30 °, the magnitude is I in the U-phase winding M1₂Flows from the bridge circuit L to the bridge circuit R, flows a current of Ipk in the V-phase winding M2 from the bridge circuit R to the bridge circuit L, and flows a current of I in the W-phase winding M3₂Flows from the bridge circuit L to the bridge circuit R.

At an electrical angle of 60 °, the magnitude is I in the U-phase winding M1₁Flows from the bridge circuit L to the bridge circuit R, and has a magnitude of I in the V-phase winding M2₁Flows from the bridge circuit R to the bridge circuit L. No current flows in the W-phase winding M3.

At an electrical angle of 90 °, a current of Ipk flows from bridge circuit L to bridge circuit R in U-phase winding M1The size of the V-phase winding M2 is I₂Flows from the bridge circuit R to the bridge circuit L, and has a magnitude of I in the W-phase winding M3₂Flows from the bridge circuit R to the bridge circuit L.

At an electrical angle of 120 DEG, the magnitude is I in the U-phase winding M1₁Flows from the bridge circuit L to the bridge circuit R, and has a magnitude of I in the W-phase winding M3₁Flows from the bridge circuit R to the bridge circuit L. No current flows in the V-phase winding M2.

At an electrical angle of 150 DEG, the magnitude is I in the U-phase winding M1₂Flows from the bridge circuit L to the bridge circuit R, and has a magnitude of I in the V-phase winding M2₂The current of (2) flows from the bridge circuit L to the bridge circuit R, and a current of an Ipk magnitude flows from the bridge circuit R to the bridge circuit L in the W-phase winding M3.

When the electrical angle is 180 °, no current flows in the U-phase winding M1. Size I in V-phase winding M2₁Flows from the bridge circuit L to the bridge circuit R, and has a magnitude of I in the W-phase winding M3₁Flows from the bridge circuit R to the bridge circuit L.

At an electrical angle of 210 deg., the magnitude is I in the U-phase winding M1₂The current of (2) flows from the bridge circuit R to the bridge circuit L, the current of Ipk flows from the bridge circuit L to the bridge circuit R in the V-phase winding M2, and the current of I flows in the W-phase winding M3₂Flows from the bridge circuit R to the bridge circuit L.

At an electrical angle of 240 DEG, the magnitude is I in the U-phase winding M1₁Flows from the bridge circuit R to the bridge circuit L, and has a magnitude of I in the V-phase winding M2₁Flows from the bridge circuit L to the bridge circuit R. No current flows in the W-phase winding M3.

At an electrical angle of 270 °, Ipk flows from bridge circuit R to bridge circuit L in the U-phase winding M1, and I in the V-phase winding M2₂Flows from the bridge circuit L to the bridge circuit R, and has a magnitude of I in the W-phase winding M3₂Flows from the bridge circuit L to the bridge circuit R.

At an electrical angle of 300 DEG, the magnitude is I in the U-phase winding M1₁Flows from the bridge circuit R to the bridge circuit L, and has a magnitude of I in the W-phase winding M3₁Current slave bridge circuitL flows to the bridge circuit R. No current flows in the V-phase winding M2.

At an electrical angle of 330 °, the magnitude is I in the U-phase winding M1₂Flows from the bridge circuit R to the bridge circuit L, and has a magnitude of I in the V-phase winding M2₂The current of (2) flows from the bridge circuit R to the bridge circuit L, and the current of magnitude Ipk flows from the bridge circuit L to the bridge circuit R in the W-phase winding M3.

According to the three-phase energization control, the sum of currents flowing in the three-phase windings considering the current direction is always "0" for each electrical angle. For example, the control circuit 300 controls the switching operation of each FET of the bridge circuit L and the bridge circuit R by PWM control such that the current waveform shown in fig. 6 can be obtained.

(2. control at abnormality)

As described above, the abnormality mainly means that the FET has failed. Failures of FETs are roughly classified into "open-circuit failures" and "short-circuit failures". The "open failure" refers to a failure in which the FET is open between the source and the drain (in other words, the source-drain resistance rds becomes high impedance), and the "short failure" refers to a failure in which the FET is short-circuited between the source and the drain.

Reference is again made to fig. 1. It may be considered that a random failure, which is a failure in which 1 FET among a plurality of FETs randomly occurs, generally occurs when the power conversion apparatus 100 operates. The present disclosure is mainly directed to a method of controlling the power conversion apparatus 100 when a random fault occurs. However, the present disclosure also targets a control method of the power conversion device 100 in which a plurality of FETs are in cascade failure or the like. A cascading failure refers to a failure in which, for example, the high-side switching element and the low-side switching element of 1 leg occur simultaneously.

When the power conversion apparatus 100 is used for a long period of time, random failures may be caused. In addition, random failures are different from manufacturing failures that may occur at the time of manufacturing. If 1 of the FETs of 2 inverters fails, the normal three-phase energization control is not performed.

As an example of failure detection, the driver circuit 350 monitors the source-drain voltage of each FET, and compares the source-drain voltage with a predetermined threshold voltage Vds to detect a failure of the FET. The threshold voltage is set in the driver circuit 350 by, for example, data communication with an external IC (not shown) and an external component. The driver circuit 350 is connected to a port of the microcontroller 340 and notifies the microcontroller 340 of a failure detection signal. For example, the drive circuit 350 asserts a failure detection signal when a failure of the FET is detected. Upon receiving the asserted failure detection signal, the microcontroller 340 reads internal data of the drive circuit 350 to determine which of the FETs has failed.

As another example of the failure detection, the microcontroller 340 can also detect a failure of the FET from a difference between an actual current value and a target current value of the motor. However, the failure detection is not limited to these methods, and various methods related to the failure detection can be used.

If the failure detection signal is asserted, the microcontroller 340 switches the control of the power conversion apparatus 100 from the control at the normal time to the control at the abnormal time. For example, the timing of switching control from the normal state to the abnormal state is about 10msec to 30msec after the failure detection signal is asserted.

There are various failure modes of the power conversion apparatus 100. Hereinafter, control in the event of an abnormality of power conversion device 100 will be described in detail for each of the modes by distinguishing the failure modes. In the present embodiment, the 1 st inverter 120 among the 2 inverters is treated as a faulty inverter, and the 2 nd inverter 130 is treated as a normal inverter.

[ 2-1. high-side switching element _ open-circuit failure ]

The control in the abnormal state in the case where the 3 high-side switching elements include the switching element having the open failure in the bridge circuit of the 1 st inverter 120 will be described.

It is assumed that an open failure has occurred in the FET121H in the high-side switching elements ( FETs 121H, 122H, and 123H) of the 1 st inverter 120. In addition, even when the FET122H or 123H has an open circuit failure, the power conversion device 100 can be controlled by the control method described below.

When the FET121H has an open failure, the control circuit 300 brings the FETs 111, 112, 113, and 114 of the 2 switching circuits 110 and the FETs 122H, 123H, 121L, 122L, and 123L of the 1 st inverter 120 into the 1 st state. In the 1 st state, the FETs 111 and 113 of the 2 switching circuits 110 are turned off, and the FETs 112 and 114 are turned on. Further, FETs 122H and 123H (high-side switching elements different from the failed FET121H) of the 1 st inverter 120 other than the failed FET121H are turned off, and FETs 121L, 122L and 123L are turned on.

In the 1 st state, the 1 st inverter 120 is electrically separated from the power source 101 and GND, and the 2 nd inverter 130 is electrically connected to the power source 101 and GND. In other words, when the 1 st inverter 120 is abnormal, the FET113 cuts off the connection between the power source 101 and the 1 st inverter 120, and the FET111 cuts off the connection between the 1 st inverter 120 and GND. When all of the 3 low-side switching devices are turned on, the node N1 on the low side functions as a neutral point of each winding. In the present specification, a certain node is expressed as "constituting a neutral point" as a function of functioning as a neutral point. Power conversion device 100 drives motor 200 using a neutral point formed on the lower side of inverter 1 120 and inverter 2 130.

Fig. 7 schematically shows the flow of current in the power conversion device 100 when the FETs of the 2 switching circuits 110 and the 1 st inverter 120 are in the 1 st state. Fig. 8 illustrates a current waveform obtained by plotting current values of currents flowing through the respective windings of the U-phase, V-phase, and W-phase of the motor 200 when the power conversion device 100 is controlled in the 1 st state. The flow of current is shown in fig. 7 for example at an electrical angle of 270 ° of the motor. The straight arrows indicate the currents flowing from the power source 101 to the motor 200, respectively.

In the state shown in fig. 7, in inverter 2 130, FETs 131H, 132L, and 133L are on, and FETs 131L, 132H, and 133H are off. The current flowing through the FET131H of the 2 nd inverter 130 flows to the neutral point through the winding M1 and the FET121L of the 1 st inverter 120. A part of this current flows to the winding M2 through the FET122L, and the remaining current flows to the winding M3 through the FET 123L. The current flowing through the windings M2 and M3 flows to GND via the FET112 on the 2 nd inverter 130 side. In a free wheeling diode (also referred to as a "regeneration diode") of the FET131L, a regeneration current flows toward the winding M1 of the motor 200. As will be described later with reference to fig. 11, the parasitic diodes 140 are formed inside the FETs 121L, 122L, 123L, 121H, 122H, 123H, 131L, 132L, 133L, 131H, 132H, and 133H, respectively. In each FET, the parasitic diode 140 is configured such that a forward current flows in a direction toward the power source 101. In this embodiment, the parasitic diode 140 is used as a free wheeling diode.

Table 2 illustrates a value of a current flowing in the terminal of the 2 nd inverter 130 per each electrical angle in the current waveform of fig. 8. Specifically, table 2 illustrates values of currents flowing in terminals U _ R, V _ R and W _ R of the 2 nd inverter 130 (bridge circuit R) at each electrical angle of 30 °. The current direction is defined as described above. The sign of the current value shown in fig. 8 is in an opposite relationship to the sign of the current value shown in table 2 (phase difference of 180 °), depending on the definition of the direction of the current.

[ Table 2]

For example, the magnitude is I in the U-phase winding M1 at an electrical angle of 30 °₂Flows from the bridge circuit L to the bridge circuit R, flows a current of Ipk in the V-phase winding M2 from the bridge circuit R to the bridge circuit L, and flows a current of I in the W-phase winding M3₂Flows from the bridge circuit L to the bridge circuit R. At an electrical angle of 60 °, the magnitude is I in the U-phase winding M1₁Flows from the bridge circuit L to the bridge circuit R, and has a magnitude of I in the V-phase winding M2₁Flows from the bridge circuit R to the bridge circuit L. No current flows in the W-phase winding M3. The sum of the current flowing into the neutral point and the current flowing out from the neutral point is always "0" for each electrical angle. The control circuit 300 controls the switching operation of each FET of the bridge circuit R by PWM control such that the current waveform shown in fig. 8 can be obtained, for example.

As shown in table 1 and table 2, it is understood that the motor current flowing through the motor 200 does not change for each electrical angle during the normal time and the abnormal time control period. Therefore, the assist torque of the motor is not reduced in the control at the time of abnormality, as compared with the control at the time of normal.

Since power source 101 is not electrically connected to 1 st inverter 120, current does not flow from power source 101 to 1 st inverter 120. Since the 1 st inverter 120 is not electrically connected to GND, the current flowing through the neutral point does not flow to GND. This makes it possible to form a closed loop of the drive current while suppressing power loss, thereby performing appropriate current control.

When the high-side switching element (FET121H) has an open-circuit fault, the states of the FETs of the 2 switching circuits 110 and the 1 st inverter 120 are not limited to the 1 st state. For example, the control circuit 300 may set these FETs to the 2 nd state. In the 2 nd state, the FET113 of the 2 switching circuits 110 is turned on, and the FET111 is turned off, and the FETs 112, 114 are turned on. Further, FETs 122H and 123H of the 1 st inverter 120 other than the failed FET121H are turned off, and FETs 121L, 122L and 123L are turned on. The difference between the 1 st state and the 2 nd state is whether the FET113 is on. The reason why the FET113 can be turned on is that when the FET121H has an open failure, the FETs 122H and 123H are controlled to be turned off, so that all the high-side switching elements are turned on, and thus, even if the FET113 is turned on, no current flows from the power source 101 to the 1 st inverter 120. In this way, the FET113 may be turned on or off at the time of an open failure.

[ 2-2. high-side switching element _ short-circuit failure ]

The control in the abnormal state in the case where the 3 high-side switching elements include the switching element having the short-circuit failure in the bridge circuit of the 1 st inverter 120 will be described.

It is assumed that short-circuit failure occurs in the FET121H in the high-side switching elements ( FETs 121H, 122H, and 123H) of the 1 st inverter 120. In addition, even when the short-circuit failure occurs in the FET122H or 123H, the power conversion device 100 can be controlled by the control method described below.

When the FET121H has a short-circuit failure, the control circuit 300 brings the FETs 111, 112, 113, and 114 of the 2 switching circuits 110 and the FETs 122H, 123H, 121L, 122L, and 123L of the 1 st inverter 120 into the 1 st state. In the case of a short-circuit fault, when the FET113 is turned on, a current flows from the power supply 101 to the short-circuited FET121H, and therefore, control in the 2 nd state is prohibited.

Similarly to the case of an open fault, all of the 3 low-side switching elements are turned on, and thus the node N1 on the low side forms a neutral point of each winding. Power conversion device 100 drives motor 200 using a neutral point formed on the lower side of inverter 1 120 and inverter 2 130. The control circuit 300 controls the switching operation of each FET of the bridge circuit R by PWM control such that the current waveform shown in fig. 8 can be obtained, for example. For example, in the 1 st state at the time of the short-circuit fault, the flow of the current flowing in the power conversion device 100 at the electrical angle of 270 ° is as shown in fig. 7, and the values of the currents flowing in the respective windings at each motor electrical angle are as shown in table 2.

In the case where the short-circuit failure occurs in the FET121H, for example, in the 1 st state of each FET shown in fig. 7, when the motor electrical angle is 0 ° to 120 ° in table 2, the regenerative current flows through the parasitic diode of the FET122H to the FET121H, and when the motor electrical angle is 60 ° to 180 ° in table 2, the regenerative current flows through the parasitic diode of the FET123H to the FET 121H. In this way, in the case of a short-circuit fault, the current can be dispersed by the FET121H within a certain range of the motor electrical angle.

According to this control, since the power source 101 is not electrically connected to the 1 st inverter 120, current does not flow from the power source 101 to the 1 st inverter 120. Since the 1 st inverter 120 is not electrically connected to GND, the current flowing through the neutral point does not flow to GND.

[ 2-3. Low-side switching element _ open-circuit failure ]

The control in the abnormal case when the 3 low-side switching elements include the switching element having the open failure in the bridge circuit of the 1 st inverter 120 will be described.

It is assumed that an open failure has occurred in the FET121L in the low-side switching elements ( FETs 121L, 122L, and 123L) of the 1 st inverter 120. In addition, even when the FET122L or 123L has an open failure, the power conversion device 100 can be controlled by the control method described below.

When the FET121L has an open failure, the control circuit 300 brings the FETs 111, 112, 113, and 114 of the 2 switching circuits 110 and the FETs 121H, 122H, 123H, 122L, and 123L of the 1 st inverter 120 into the 3 rd state. In the 3 rd state, the FETs 111 and 113 of the 2 switching circuits 110 are turned off, and the FETs 112 and 114 are turned on. Further, FETs 122L and 123L (low-side switching elements different from failed FET121L) of inverter 1 except for failed FET121L are turned off, and FETs 121H, 122H, and 123H are turned on.

In the 3 rd state, the 1 st inverter 120 is electrically separated from the power source 101 and GND, and the 2 nd inverter 130 is electrically connected to the power source 101 and GND. Then, all of the 3 high-side switching elements of the 1 st inverter 120 are turned on, and the high-side node N3 forms a neutral point of each winding.

Fig. 9 schematically shows the flow of current in the power conversion device 100 when the FETs of the 2 switching circuits 110 and the 1 st inverter 120 are in the 3 rd state. The flow of current at a motor electrical angle of 270 ° for example is shown in fig. 9. The straight arrows indicate the currents flowing from the power source 101 to the motor 200, respectively.

In the state shown in fig. 9, in inverter 2 130, FETs 131H, 132L, and 133L are on, and FETs 131L, 132H, and 133H are off. The current flowing through the FET131H of the 2 nd inverter 130 flows to the neutral point through the winding M1 and the FET121H of the 1 st inverter 120. A part of this current flows to the winding M2 through the FET122H, and the remaining current flows to the winding M3 through the FET 123H. The current flowing through the windings M2 and M3 flows to GND via the FET112 on the 2 nd inverter 130 side. In the parasitic diode of the FET131L, the regenerative current flows toward the winding M1 of the motor 200. For example, the values of the currents flowing in the respective windings at each motor electrical angle are shown in table 2.

Power conversion device 100 drives motor 200 using a neutral point formed on the high side of inverter 1 120 and inverter 2 130. The control circuit 300 controls the switching operation of each FET of the bridge circuit R by PWM control such that the current waveform shown in fig. 8 can be obtained, for example.

According to this control, since the power source 101 is not electrically connected to the 1 st inverter 120, no current flows from the power source 101 to the neutral point of the 1 st inverter 120. Since the 1 st inverter 120 is not electrically connected to GND, current does not flow from the 1 st inverter 120 to GND.

When the low-side switching device (FET121L) has an open-circuit fault, the states of the FETs of the 2 switching circuits 110 and the 1 st inverter 120 are not limited to the 3 rd state. For example, the control circuit 300 may set these FETs to the 4 th state. In the 4 th state, the FET113 of the 2 switching circuits 110 is turned off, the FET111 is turned on, and the FETs 112, 114 are turned on. Further, FETs 122L and 123L of the 1 st inverter 120 other than the failed FET121L are turned off, and FETs 121H, 122H and 123H are turned on. The difference between the 3 rd state and the 4 th state is whether the FET111 is on. The reason why the FET111 can be turned on is that when the FET121L has an open failure, the FETs 122L and 123L are controlled to be turned off, so that all the low-side switching elements are turned on, and thus no current flows to GND even when the FET111 is turned on. In this way, the FET111 may be in an on state or an off state at the time of an open failure.

[ 2-4. Low-side switching element _ short-circuit Fault ]

The control in the abnormal case when the 3 low-side switching elements include the switching element having the short-circuit failure in the bridge circuit of the 1 st inverter 120 will be described.

It is assumed that a short-circuit fault occurs in the FET121L in the low-side switching elements ( FETs 121L, 122L, and 123L) of the 1 st inverter 120. In addition, even when the FET122L or 123L has a short-circuit fault, the power conversion device 100 can be controlled by the control method described below.

When the FET121L has a short-circuit fault, the control circuit 300 sets the FETs 111, 112, 113, and 114 of the 2 switching circuits 110 and the FETs 121H, 122H, 123H, 122L, and 123L of the 1 st inverter 120 to the 3 rd state in the same manner as in the case of an open-circuit fault. In the case of a short-circuit fault, when the FET111 is turned on, current flows from the short-circuited FET121L to GND, and therefore control in the 4 th state is prohibited.

In the state shown in fig. 9, in inverter 2 130, FETs 131H, 132L, and 133L are on, and FETs 131L, 132H, and 133H are off. The current flowing through the FET131H of the 2 nd inverter 130 flows to the neutral point through the winding M1 and the FET121H of the 1 st inverter 120. A part of this current flows to the winding M2 through the FET122H, and the remaining current flows to the winding M3 through the FET 123H. The current flowing through the windings M2 and M3 flows to GND via the FET112 on the 2 nd inverter 130 side. In the parasitic diode of the FET131L, the regenerative current flows to the winding M1 of the motor 200. Further, unlike the open fault, in the short fault, a current flows from the FET121L in which the short circuit occurs to the node N1 on the low side. A part of this current flows to the winding M2 through the parasitic diode of the FET122L, and the remaining current flows to the winding M3 through the parasitic diode of the FET 123L. The current flowing through the windings M2 and M3 flows to GND through the FET 112.

For example, the values of the currents flowing in the respective windings at each motor electrical angle are shown in table 2.

Power conversion device 100 drives motor 200 using a neutral point formed on the high side of inverter 1 120 and inverter 2 130. The control circuit 300 controls the switching operation of each FET of the bridge circuit R by PWM control such that the current waveform shown in fig. 8 can be obtained, for example.

According to this control, since the power source 101 is not electrically connected to the 1 st inverter 120, no current flows from the power source 101 to the neutral point of the 1 st inverter 120. Since the 1 st inverter 120 is not electrically connected to GND, current does not flow from the 1 st inverter 120 to GND.

In the above description of the embodiment, the 1 st inverter 120 among the 2 inverters is treated as a faulty inverter, and the 2 nd inverter 130 is treated as a normal inverter. Even when the 2 nd inverter 130 is a faulty inverter and the 1 st inverter 120 is a normal inverter, the control in the abnormal state can be performed in the same manner as described above. In this case, the control of the 1 st inverter 120, the 2 nd inverter 130, and the switching circuit 110 is reversed from the above control. That is, the neutral point is formed in the 2 nd inverter 130, and the motor 200 can be driven using the neutral point and the 1 st inverter 120.

(3. failure diagnosis)

Next, an operation of diagnosing the presence or absence of a failure of the FET in the power conversion device 100 for driving the motor 200 using the 2 inverters 120 and 130 according to the present embodiment will be described. In the failure diagnosis of the present embodiment, when a FET fails, which FET of the plurality of FETs failed can be determined.

In the failure diagnosis of the present embodiment, the diagnosis is performed in the state where the neutral point is configured as described above. For example, in the normal control operation described above, the failure diagnosis may be performed by periodically configuring the neutral point. Further, for example, even in a state where a failure has occurred to form a neutral point and drive the motor 200, it is possible to perform a failure diagnosis.

In the failure diagnosis of the present embodiment, an open failure of the FET is detected. As described above, the open failure is a failure in which the source-drain of the FET is open (in other words, the resistance between the source and the drain is always high impedance).

[ 3-1 ] Fault diagnosis when the neutral point is formed on the low side of the 1 st inverter 120 ]

First, an operation of forming a neutral point at the node N1 on the low side of the 1 st inverter 120 to perform fault diagnosis will be described.

Fig. 10 is a diagram showing an example of an operation for constructing a neutral point and performing a failure diagnosis.

The control circuit 300 turns off the FETs 111 and 113 and turns on the FETs 112 and 114. Then, FETs 121H, 122H, and 123H are turned off, FETs 121L, 122L, and 123L are turned on, and a neutral point is formed at node N1.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 131H, 132L and turns off the FETs 131L, 132H, 133L, 133H. This makes up a conductive path in which the FET131H on the high side of the 2 nd inverter 130, the U-phase winding M1, the neutral point (node N1), the V-phase winding M2, and the FET132L on the low side of the 2 nd inverter 130 are connected. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

Fig. 11 is a diagram showing FETs included in the 1 st and 2 nd inverters 120 and 130. A parasitic diode 140 is formed inside each of the FETs 121L, 122L, 123L, 121H, 122H, 123H, 131L, 132L, 133L, 131H, 132H, and 133H. In each FET, the parasitic diode 140 is configured such that a forward current flows toward the power source 101. That is, the parasitic diode 140 is disposed such that the cathode faces the power supply 101 side and the anode faces the GND side. In this embodiment, the parasitic diode 140 is used as a free wheeling diode. In addition, an element structure in which a free wheeling diode is connected in parallel to an FET can also be used in this embodiment.

Referring to fig. 10, in the present embodiment, the presence or absence of a failure of the switching element in which the current flowing through the above-described conductive path becomes a reverse current in the free wheeling diode 140 is diagnosed. In the example shown in fig. 10, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 121L, 131H, 132L. That is, the presence or absence of a failure of the FETs 121L, 131H, 132L is diagnosed.

The control circuit 300 diagnoses the presence or absence of a fault using at least 2 of the voltage value of the U-phase, the voltage value of the V-phase, and the voltage value of the W-phase when a voltage is applied to the conductive path. The voltage value of the U phase is, for example, the voltage value of the node N131 at which the FET131H and the FET131L are connected. The voltage value of the node N131 is, for example, the potential difference between the node N131 and GND. The voltage of the node N131 can be the same as the voltage of the terminal U _ R (fig. 1). The voltage value of the V phase is, for example, the voltage value of the node N132 connected between the FET132H and the FET 132L. The voltage value of the node N132 is, for example, the potential difference between the node N132 and GND. The voltage of the node N132 can be the same as the voltage of the terminal V _ R (fig. 1). The voltage value of the W phase is, for example, the voltage value of the node N133 connected between the FETs 133H and 133L. The voltage value of the node N133 is, for example, the potential difference between the node N133 and GND. The voltage of the node N133 can be the same as the voltage of the terminal W _ R (fig. 1). The voltage detection circuit 380 (fig. 5) detects the voltage values of the U-phase, V-phase, and W-phase, and outputs the detected voltage values to the microcontroller 340.

First, the voltage values of the FETs 121L, 131H, and 132L in a normal state will be described. When the FETs 121L, 131H, and 132L are all normal, the voltage at the node N131 has a value close to the output voltage of the power supply 101. The voltage of the node N132 is a value between the output voltage of the power supply 101 and the GND voltage. For example, the voltage of the node N132 is a value slightly closer to the GND voltage than the output voltage of the power supply 101. Hereinafter, such a value close to the output voltage of the power supply 101 is expressed as "high" in voltage. The value between the output voltage of the power supply 101 and the GND voltage is expressed as "medium" voltage.

In the case where the voltage at node N131 is "high" and the voltage at node N132 is "medium", the microcontroller 340 determines that the FETs 121L, 131H, 132L are all normal.

Next, a voltage value at the time of the open failure of the FET131H will be described. When the FET131H has an open failure, the power supply voltage is not applied to the node N131. Therefore, the voltages of the nodes N131 and N132 both have a value close to the GND voltage. Hereinafter, such a value close to the GND voltage is expressed as "low" in voltage. The voltage "medium" indicates that the voltage is a value between "high" and "low".

In the case where the voltages at nodes N131, N132 are both "low", the microcontroller 340 determines that an open fault has occurred in the FET 131H.

Next, a voltage value at the time of the open failure of the FET121L will be described. In the case where the FET121L has an open circuit fault, the voltage at the node N131 is "high", and the voltage at the node N132 is "low".

In the case where the voltage at node N131 is "high" and the voltage at node N132 is "low", the microcontroller 340 determines that an open fault has occurred in FET 121L.

Next, a voltage value at the time of the open failure of the FET132L will be described. In this case, the node N132 is not connected to GND. Therefore, the voltages at nodes N131 and N132 are both "high".

In the case where the voltages at nodes N131, N132 are both "high", the microcontroller 340 determines that an open circuit fault has occurred in FET 132L.

Fig. 12 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 2 nd inverter 130 in the case where the low side constitutes the neutral point. In the table shown in fig. 12, switching elements that can be diagnosed for a switching element that is turned on are indicated by white circles. In the example shown in fig. 10, the FETs 131H, 132L are turned on, and the presence or absence of a failure of the FETs 121L, 131H, 132L can be diagnosed. The failure diagnosis when the FETs 132H, 133L are in the on state will be described below with reference to fig. 13. Further, the failure diagnosis when the FETs 133H, 131L are in the on state will be described with reference to fig. 14.

Fig. 13 is a diagram for explaining failure diagnosis when the FETs 132H, 133L are turned on. As in the example of fig. 10, the control circuit 300 forms a neutral point at the node N1.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 132H, 133L and turns off the FETs 131L, 131H, 132L, 133H. Thus, the FET132H on the high side of the 2 nd inverter 130, the V-phase winding M2, the neutral point (node N1), the W-phase winding M3, and the FET133L on the low side of the 2 nd inverter 130 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 13, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 132H, 122L, 133L. In the example shown in fig. 13, the presence or absence of a failure of the FETs 132H, 122L, 133L is diagnosed.

Similarly to the method described with reference to fig. 10, the microcontroller 340 determines which of the voltages at the nodes N132 and N133 is "high", "medium", and "low", and performs the fault diagnosis.

In the case where the voltage at node N132 is "high" and the voltage at node N133 is "medium", the microcontroller 340 determines that FETs 132H, 122L, 133L are all normal.

In the case where the voltages at nodes N132, N133 are both "low", the microcontroller 340 determines that an open fault has occurred in FET 132H.

In the case where the voltage at node N132 is "high" and the voltage at node N133 is "low", the microcontroller 340 determines that an open fault has occurred with FET 122L.

In the case where the voltages at nodes N132, N133 are both "high", the microcontroller 340 determines that an open fault has occurred in FET 133L.

Fig. 14 is a diagram for explaining failure diagnosis when the FETs 133H, 131L are turned on. As in the example of fig. 10 and 13, the control circuit 300 forms a neutral point at the node N1.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 133H, 131L and turns off the FETs 131H, 132L, 132H, 133L. Thus, the FET133H on the high side of the 2 nd inverter 130, the W-phase winding M3, the neutral point (node N1), the U-phase winding M1, and the FET131L on the low side of the 2 nd inverter 130 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 14, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 133H, 123L, 131L. In the example shown in fig. 14, the presence or absence of a failure of the FETs 133H, 123L, 131L is diagnosed.

Similarly to the methods described with reference to fig. 10 and 13, the microcontroller 340 determines which of the "high", "medium", and "low" voltages of the nodes N133 and N131 is set, and performs the fault diagnosis.

In the case where the voltage at the node N133 is "high" and the voltage at the node N131 is "medium", the microcontroller 340 determines that the FETs 133H, 123L, 131L are all normal.

When both voltages at nodes N133 and N131 are "low", the microcontroller 340 determines that the FET133H has an open fault.

In the case where the voltage at the node N133 is "high" and the voltage at the node N131 is "low", the microcontroller 340 determines that the FET123L has an open fault.

When both voltages at the nodes N133 and N131 are "high", the microcontroller 340 determines that the FET131L has an open fault.

As described above, according to the present embodiment, when a FET fails, which FET of the plurality of FETs failed can be determined.

[ 3-2 ] Fault diagnosis when the neutral Point is formed on the high side of the 1 st inverter 120 ]

Next, an operation of forming a neutral point at the node N3 on the high side of the 1 st inverter 120 and performing fault diagnosis will be described.

Fig. 15 is a diagram showing an example of an operation for constructing a neutral point and performing a failure diagnosis.

The control circuit 300 turns off the FETs 111 and 113 and turns on the FETs 112 and 114. Then, FETs 121L, 122L, and 123L are turned off, FETs 121H, 122H, and 123H are turned on, and a neutral point is formed at node N3.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 131H, 132L and turns off the FETs 131L, 132H, 133L, 133H. This makes up a conductive path in which the FET131H on the high side of the 2 nd inverter 130, the U-phase winding M1, the neutral point (node N3), the V-phase winding M2, and the FET132L on the low side of the 2 nd inverter 130 are connected. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 15, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 122H, 131H, 132L. That is, the presence or absence of a failure of the FETs 122H, 131H, 132L is diagnosed.

In the case where the voltage at node N131 is "high" and the voltage at node N132 is "medium", the microcontroller 340 determines that the FETs 122H, 131H, 132L are all normal.

In the case where the voltages at nodes N131, N132 are both "low", the microcontroller 340 determines that an open fault has occurred in the FET 131H.

In the case where the voltage at node N131 is "high" and the voltage at node N132 is "low", the microcontroller 340 determines that an open fault has occurred in FET 122H.

In the case where the voltages at nodes N131, N132 are both "high", the microcontroller 340 determines that an open circuit fault has occurred in FET 132L.

Fig. 16 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 2 nd inverter 130 in the case where the high side constitutes the neutral point. In the table shown in fig. 16, switching elements that can be diagnosed for a switching element that is turned on are indicated by white circles. In the example shown in fig. 15, the FETs 131H, 132L are turned on, and the presence or absence of a failure of the FETs 122H, 131H, 132L can be diagnosed.

Fig. 17 is a diagram illustrating failure diagnosis when the FETs 132H, 133L are turned on. As in the example of fig. 15, the control circuit 300 forms a neutral point at the node N3.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 132H, 133L and turns off the FETs 131L, 131H, 132L, 133H. Thus, the FET132H on the high side of the 2 nd inverter 130, the V-phase winding M2, the neutral point (node N3), the W-phase winding M3, and the FET133L on the low side of the 2 nd inverter 130 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 17, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 132H, 123H, 133L. In the example shown in fig. 17, the presence or absence of a failure of the FETs 132H, 123H, 133L is diagnosed.

Similarly to the above method, the microcontroller 340 determines which of the voltages of the nodes N132 and N133 is "high", "medium", and "low", and performs the fault diagnosis.

In the case where the voltage at node N132 is "high" and the voltage at node N133 is "medium", the microcontroller 340 determines that the FETs 132H, 123H, 133L are all normal.

In the case where the voltages at nodes N132, N133 are both "low", the microcontroller 340 determines that an open fault has occurred in FET 132H.

In the case where the voltage at the node N132 is "high" and the voltage at the node N133 is "low", the microcontroller 340 determines that an open-circuit fault has occurred in the FET 123H.

In the case where the voltages at nodes N132, N133 are both "high", the microcontroller 340 determines that an open fault has occurred in FET 133L.

Fig. 18 is a diagram for explaining failure diagnosis when the FETs 133H, 131L are turned on. As in the example of fig. 15 and 17, the control circuit 300 forms a neutral point at the node N3.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 133H, 131L and turns off the FETs 131H, 132L, 132H, 133L. Thus, the FET133H on the high side of the 2 nd inverter 130, the W-phase winding M3, the neutral point (node N3), the U-phase winding M1, and the FET131L on the low side of the 2 nd inverter 130 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 18, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 133H, 121H, 131L. In the example shown in fig. 18, the presence or absence of a failure of the FETs 133H, 121H, 131L is diagnosed.

Similarly to the above method, the microcontroller 340 determines which of the voltages of the nodes N133 and N131 is "high", "medium", and "low", and performs the fault diagnosis.

In the case where the voltage at the node N133 is "high" and the voltage at the node N131 is "medium", the microcontroller 340 determines that the FETs 133H, 121H, 131L are all normal.

When both voltages at nodes N133 and N131 are "low", the microcontroller 340 determines that the FET133H has an open fault.

In the case where the voltage at the node N133 is "high" and the voltage at the node N131 is "low", the microcontroller 340 determines that the FET121H has an open fault.

When both voltages at the nodes N133 and N131 are "high", the microcontroller 340 determines that the FET131L has an open fault.

As described above, according to the present embodiment, when a FET fails, which FET of the plurality of FETs failed can be determined.

[ 3-3. Fault diagnosis when neutral point is formed on the low side of the 2 nd inverter ]

Next, an operation of forming a neutral point at the node N2 on the low side of the 2 nd inverter 130 to perform fault diagnosis will be described.

Fig. 19 is a diagram showing an example of an operation for constructing a neutral point and performing a failure diagnosis.

The control circuit 300 turns off the FETs 112 and 114 and turns on the FETs 111 and 113. Then, FETs 131H, 132H, and 133H are turned off, FETs 131L, 132L, and 133L are turned on, and a neutral point is formed at node N2.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 121H, 122L and turns off the FETs 121L, 122H, 123L, 123H. Thus, the FET121H on the high side of the 1 st inverter 120, the U-phase winding M1, the neutral point (node N2), the V-phase winding M2, and the FET122L on the low side of the 1 st inverter 120 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 19, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 131L, 121H, and 122L. That is, the presence or absence of a failure of the FETs 131L, 121H, 122L is diagnosed.

The control circuit 300 diagnoses the presence or absence of a fault using at least 2 of the voltage value of the U-phase, the voltage value of the V-phase, and the voltage value of the W-phase when a voltage is applied to the conductive path. The voltage value of the U-phase is, for example, the voltage value of the node N121 to which the FETs 121H and 121L are connected. The voltage value of the node N121 is, for example, a potential difference between the node N121 and GND. The voltage of the node N121 can be the same as the voltage of the terminal U _ L (fig. 1). The voltage value of the V phase is, for example, the voltage value of the node N122 connected between the FETs 122H and 122L. The voltage value of the node N122 is, for example, the potential difference between the node N122 and GND. The voltage of the node N122 can be the same as the voltage of the terminal V _ L (fig. 1). The voltage value of the W phase is, for example, a voltage value between the FET123H and the node N123 connected to the FET 123L. The voltage value of the node N123 is, for example, a potential difference between the node N123 and GND. The voltage of the node N123 can be the same as the voltage of the terminal W _ L (fig. 1). The voltage detection circuit 380 (fig. 5) detects the voltage values of the U-phase, V-phase, and W-phase, and outputs the detected voltage values to the microcontroller 340.

First, the voltage values of the FETs 131L, 121H, and 122L in a normal state will be described. In the case where the FETs 131L, 121H, 122L are all normal, the voltage at the node N121 is "high". The voltage at the node N122 is "medium".

In the case where the voltage at the node N121 is "high" and the voltage at the node N122 is "medium", the microcontroller 340 determines that the FETs 131L, 121H, 122L are all normal.

Next, a voltage value at the time of the open failure of the FET121H will be described. When the FET121H has an open failure, the power supply voltage is not applied to the node N121. Therefore, the voltages of the nodes N121 and N122 are both "low".

In the case where the voltages at nodes N121, N122 are both "low", the microcontroller 340 determines that the FET121H has an open fault.

Next, a voltage value at the time of the open failure of the FET131L will be described. In the case where the FET131L has an open circuit fault, the voltage at the node N121 becomes "high", and the voltage at the node N122 becomes "low".

In the case where the voltage at the node N121 is "high" and the voltage at the node N122 is "low", the microcontroller 340 determines that an open fault has occurred in the FET 131L.

Next, a voltage value at the time of the open failure of the FET122L will be described. In this case, the node N122 is not connected to GND. Therefore, the voltages of the nodes N121 and N122 are both "high".

In the case where the voltages at nodes N121, N122 are both "high", the microcontroller 340 determines that an open fault has occurred in FET 122L.

Fig. 20 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 1 st inverter 120 in a case where the low side of the 2 nd inverter 130 constitutes a neutral point. In the table shown in fig. 20, switching elements that can be diagnosed for a switching element that is turned on are indicated by white circles. In the example shown in fig. 19, the FETs 121H and 122L are turned on, and the presence or absence of a failure of the FETs 131L, 121H, and 122L can be diagnosed. The failure diagnosis when the FETs 122H, 123L are in the on state will be described below with reference to fig. 21. Further, the failure diagnosis when the FETs 123H, 121L are in the on state will be described with reference to fig. 22.

Fig. 21 is a diagram illustrating failure diagnosis when the FETs 122H, 123L are turned on. As in the example of fig. 19, the control circuit 300 forms a neutral point at the node N2.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 122H, 123L and turns off the FETs 121L, 121H, 122L, 123H. Thus, the FET122H on the high side of the 1 st inverter 120, the V-phase winding M2, the neutral point (node N2), the W-phase winding M3, and the FET123L on the low side of the 1 st inverter 120 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 21, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 122H, 132L, 123L. In the example shown in fig. 21, the presence or absence of a failure of the FETs 122H, 132L, 123L is diagnosed.

Similarly to the method described with reference to fig. 19, the microcontroller 340 determines which of the voltages at the nodes N122 and N123 is "high", "medium", and "low", and performs the fault diagnosis.

In the case where the voltage at node N122 is "high" and the voltage at node N123 is "medium", the microcontroller 340 determines that the FETs 122H, 132L, 123L are all normal.

In the case where the voltages at nodes N122, N123 are both "low", the microcontroller 340 determines that an open fault has occurred in FET 122H.

In the case where the voltage at node N122 is "high" and the voltage at node N123 is "low", the microcontroller 340 determines that an open circuit fault has occurred with FET 132L.

When both voltages at nodes N122 and N123 are "high", the microcontroller 340 determines that the FET123L has an open-circuit fault.

Fig. 22 is a diagram for explaining failure diagnosis when the FETs 123H, 121L are turned on. As in the example of fig. 19 and 21, the control circuit 300 forms a neutral point at the node N2.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 123H, 121L and turns off the FETs 121H, 122L, 122H, 123L. Thus, the FET123H on the high side of the 1 st inverter 120, the W-phase winding M3, the neutral point (node N2), the U-phase winding M1, and the FET121L on the low side of the 1 st inverter 120 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 22, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 123H, 133L, 121L. In the example shown in fig. 22, the presence or absence of a failure of the FETs 123H, 133L, 121L is diagnosed.

Similarly to the method described with reference to fig. 19 and 21, the microcontroller 340 determines which of the voltages at the nodes N123 and N121 is "high", "medium", and "low", and performs the fault diagnosis.

In the case where the voltage at the node N123 is "high" and the voltage at the node N121 is "medium", the microcontroller 340 determines that the FETs 123H, 133L, 121L are all normal.

In the case where the voltages at nodes N123, N121 are both "low", the microcontroller 340 determines that an open fault has occurred in the FET 123H.

In the case where the voltage at node N123 is "high" and the voltage at node N121 is "low", the microcontroller 340 determines that an open fault has occurred in FET 133L.

In the case where the voltages at nodes N123, N121 are both "high", the microcontroller 340 determines that an open fault has occurred in the FET 121L.

As described above, according to the present embodiment, when a FET fails, which FET of the plurality of FETs failed can be determined.

[ 3-4 ] Fault diagnosis when neutral Point is formed on the high side of inverter 2]

Next, an operation of forming a neutral point at the node N4 on the high side of the 2 nd inverter 130 to perform fault diagnosis will be described.

Fig. 23 is a diagram showing an example of an operation for constructing a neutral point and performing a failure diagnosis.

The control circuit 300 turns off the FETs 112 and 114 and turns on the FETs 111 and 113. Then, FETs 131L, 132L, and 133L are turned off, FETs 131H, 132H, and 133H are turned on, and a neutral point is formed at node N4.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 121H, 122L and turns off the FETs 121L, 122H, 123L, 123H. Thus, the FET121H on the high side of the 1 st inverter 120, the U-phase winding M1, the neutral point (node N4), the V-phase winding M2, and the FET122L on the low side of the 1 st inverter 120 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 23, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 132H, 121H, and 122L. That is, the presence or absence of a failure of the FETs 132H, 121H, 122L is diagnosed.

In the case where the voltage at node N121 is "high" and the voltage at node N122 is "medium", the microcontroller 340 determines that the FETs 132H, 121H, 122L are all normal.

In the case where the voltages at nodes N121, N122 are both "low", the microcontroller 340 determines that the FET121H has an open fault.

In the case where the voltage at node N121 is "high" and the voltage at node N122 is "low", the microcontroller 340 determines that an open circuit fault has occurred with FET 132H.

In the case where the voltages at nodes N121, N122 are both "high", the microcontroller 340 determines that an open fault has occurred in FET 122L.

Fig. 24 is a diagram showing a relationship between the switching element set to on and the switching element to be diagnosed in the 1 st inverter 120 in the case where the high side of the 2 nd inverter 130 constitutes the neutral point. In the table shown in fig. 24, switching elements that can be diagnosed for a switching element that is turned on are indicated by white circles. In the example shown in fig. 23, the FETs 121H and 122L are turned on, and the presence or absence of a failure of the FETs 132H, 121H, and 122L can be diagnosed.

Fig. 25 is a diagram illustrating failure diagnosis when the FETs 122H, 123L are turned on. As in the example of fig. 23, the control circuit 300 forms a neutral point at the node N4.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 122H, 123L and turns off the FETs 121L, 121H, 122L, 123H. Thus, the FET122H on the high side of the 1 st inverter 120, the V-phase winding M2, the neutral point (node N4), the W-phase winding M3, and the FET123L on the low side of the 1 st inverter 120 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 25, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 122H, 133H, 123L. In the example shown in fig. 25, the presence or absence of a failure of the FETs 122H, 133H, 123L is diagnosed.

Similarly to the above method, the microcontroller 340 determines which of the voltages of the nodes N122 and N123 is "high", "medium", and "low", and performs the fault diagnosis.

In the case where the voltage at the node N122 is "high" and the voltage at the node N123 is "medium", the microcontroller 340 determines that the FETs 122H, 133H, 123L are all normal.

In the case where the voltages at nodes N122, N123 are both "low", the microcontroller 340 determines that an open fault has occurred in FET 122H.

In the case where the voltage at the node N122 is "high" and the voltage at the node N123 is "low", the microcontroller 340 determines that the FET133H has an open fault.

When both voltages at nodes N122 and N123 are "high", the microcontroller 340 determines that the FET123L has an open-circuit fault.

Fig. 26 is a diagram for explaining failure diagnosis when the FETs 123H, 121L are turned on. As in the example of fig. 23 and 25, the control circuit 300 forms a neutral point at the node N4.

In parallel with the operation of forming the neutral point, the control circuit 300 turns on the FETs 123H, 121L and turns off the FETs 121H, 122L, 122H, 123L. Thus, the FET123H on the high side of the 1 st inverter 120, the W-phase winding M3, the neutral point (node N4), the U-phase winding M1, and the FET121L on the low side of the 1 st inverter 120 are connected to form a conductive path. In the conductive path, a voltage is applied from the power supply 101, and a current flows. The straight arrows respectively indicate the currents flowing in the conductive paths.

In the example shown in fig. 26, the current flowing through the conductive path becomes a reverse current in the free wheeling diode 140 of the FETs 123H, 131H, and 121L. In the example shown in fig. 26, the presence or absence of a failure of the FETs 123H, 131H, 121L is diagnosed.

Similarly to the above method, the microcontroller 340 determines which of the voltages of the nodes N123 and N121 is "high", "medium", and "low", and performs the fault diagnosis.

In the case where the voltage at node N123 is "high" and the voltage at node N121 is "medium", the microcontroller 340 determines that the FETs 123H, 131H, 121L are all normal.

In the case where the voltages at nodes N123, N121 are both "low", the microcontroller 340 determines that an open fault has occurred in the FET 123H.

In the case where the voltage at the node N123 is "high" and the voltage at the node N121 is "low", the microcontroller 340 determines that an open fault has occurred in the FET 131H.

In the case where the voltages at nodes N123, N121 are both "high", the microcontroller 340 determines that an open fault has occurred in the FET 121L.

As described above, according to the present embodiment, when a FET fails, which FET of the plurality of FETs failed can be determined.

In particular, by performing both the diagnosis shown in fig. 12 and the diagnosis shown in fig. 16, it is possible to perform failure diagnosis of all of the 12 FETs included in the 1 st and 2 nd inverters 120 and 130.

By performing both the diagnosis shown in fig. 20 and the diagnosis shown in fig. 24, it is possible to perform failure diagnosis of all of the 12 FETs included in the 1 st and 2 nd inverters 120 and 130.

By performing both the diagnosis shown in fig. 12 and the diagnosis shown in fig. 20, it is possible to perform failure diagnosis of all of the 12 FETs included in the 1 st and 2 nd inverters 120 and 130.

By performing both the diagnosis shown in fig. 16 and the diagnosis shown in fig. 24, it is possible to perform failure diagnosis of all of the 12 FETs included in the 1 st and 2 nd inverters 120 and 130.

By performing both the diagnosis shown in fig. 12 and the diagnosis shown in fig. 24, it is possible to perform failure diagnosis of all of the 12 FETs included in the 1 st and 2 nd inverters 120 and 130.

By performing both the diagnosis shown in fig. 16 and the diagnosis shown in fig. 20, it is possible to perform failure diagnosis of all of the 12 FETs included in the 1 st and 2 nd inverters 120 and 130.

In this way, by performing at least 2 of the 4 diagnoses shown in fig. 12, 16, 20, and 24, it is possible to perform failure diagnosis of all of the 12 FETs included in the 1 st and 2 nd inverters 120 and 130.

All of the 4 diagnoses shown in fig. 12, 16, 20, and 24 may be performed. By performing all of the 4 kinds of diagnosis, the accuracy of detection of the faulty switching element can be improved.

Thus, for example, even in the system in which the voltage between the source and the drain of the FET is not monitored as described above, it is possible to specify the FET that has failed.

In the normal control operation of the power conversion device 100, the above-described failure diagnosis can be performed by periodically configuring the neutral point. By the above failure diagnosis, when the FET having a failure is detected, the "normal control" can be switched to the "abnormal control", and the motor 200 can be continuously driven.

For example, the following actions may also be performed: the above 2 diagnoses are continuously executed in the middle of the normal control operation, and the control operation is resumed to the normal control operation. Further, for example, the following actions may be performed: the above-described 3 types of diagnosis are continuously executed in the middle of the normal control operation, and the control operation is resumed to the normal control operation. Further, for example, the following actions may be performed: the 4 kinds of diagnosis are continuously executed in the middle of the normal control operation, and the control operation is resumed to the normal control operation.

(4. voltage of gate control signal)

Next, a gate control signal for switching on/off the high-side switching elements ( FETs 121H, 122H, 123H, 131H, 132H, 133H) and the low-side switching elements ( FETs 121L, 122L, 123L, 131L, 132L, 133L) will be described. Here, the description is given focusing on the high-side switching elements ( FETs 121H, 122H, 123H) and the low-side switching elements ( FETs 121L, 122L, 123L) of the 1 st inverter 120, but the same applies to the 2 nd inverter 130.

In normal control of the 1 st inverter 120, the drive circuit 350 supplies gate control signals for switching on/off of the FETs 121L, 122L, 123L to the FETs 121L, 122L, 123L. The FET111 of the switching circuit 110 is turned on, and the source potentials of the FETs 121L, 122L, and 123L are low because they are GND potentials. Since the reference potential of the gate is the GND potential, even if the voltage of the gate control signal (gate voltage) is relatively low, the FETs 121L, 122L, 123L can be turned on. Hereinafter, the voltage of the gate control signal may be referred to as a gate voltage. In this example, the voltage of the gate control signal and the gate voltage indicate values based on the GND potential.

On the other hand, the source potentials of the FETs 121H, 122H, 123H are high because they are the drive voltages supplied to the windings M1, M2, M3. Therefore, the gate voltage for turning on the FETs 121H, 122H, 123H is set to be higher than the gate voltage for turning on the FETs 121L, 122L, 123L. The higher gate voltage is generated, for example, by the boost circuit 370 (fig. 5).

In the normal control of the 1 st inverter 120, the gate voltage for turning on the FETs 121L, 122L, 123L is, for example, 12V. The gate voltage for turning on the FETs 121H, 122H, 123H is, for example, 24V.

In the case where an open fault or a short fault occurs in at least 1 of the FETs 121H, 122H, 123H, the node N1 on the low side constitutes a neutral point as described above. The FETs 111, 113 of the switching circuit 110 are turned off. In this case, the source potentials of the FETs 121L, 122L, 123L do not reach the GND potential. The source potentials of the FETs 121L, 122L, 123L become the potential of the neutral point higher than the GND potential. In other words, the reference voltages of the sources of the FETs 121L, 122L, 123L are in a floating state. Therefore, the gate-source voltages of the FETs 121L, 122L, 123L are smaller than in the normal control.

When the gate-source voltage is small, the resistance value between the source and the drain of the FETs 121L, 122L, 123L in the on state may become large, or the FETs 121L, 122L, 123L may become in the off state undesirably. Therefore, when the node N1 on the low side constitutes a neutral point, it is considered that the voltage (gate voltage) of the gate control signal for turning on the FETs 121L, 122L, 123L is set to be higher than that in the normal state.

Fig. 27 schematically shows the power conversion apparatus 100 having the sub drive circuit 160L of the present embodiment. The sub-driver circuit 160L is connected to the FETs 121L, 122L, 123L.

In normal control of the 1 st inverter 120, gate control signals are supplied from the drive circuit 350 to the FETs 121L, 122L, 123L. When the node N1 forms a neutral point in the 1 st inverter 120 in an abnormal state, the sub-drive circuit 160L supplies gate control signals to the FETs 121L, 122L, 123L. Regarding the FETs 121L, 122L, 123L, the voltage of the gate control signal output by the sub-drive circuit 160L is higher than the voltage of the gate control signal output by the drive circuit 350. The higher gate voltage is generated, for example, by the boost circuit 370 (fig. 5). The voltage of the gate control signal output by the sub-driving circuit 160L is, for example, 24V.

The sub-driver circuit 160L includes switching circuits 161 and 162. In normal control of the 1 st inverter 120, the switching circuits 161 and 162 are turned off.

When the node N1 of the 1 st inverter 120 constitutes a neutral point, the microcontroller 340 turns on the switching circuit 161. Then, the voltage of the voltage source 163 is supplied as a gate voltage to the FETs 121L, 122L, 123L via the switching circuit 161. The voltage of the voltage source 163 is the voltage generated by the voltage boosting circuit 370. The voltage of the voltage source 163 is set such that the gate-source voltage of the FETs 121L, 122L, 123L is smaller than the withstand voltage, for example.

As control different from control for constituting the neutral point, the microcontroller 340 turns the switching circuit 162 into the on state when the operation of the 1 st inverter 120 is forcibly stopped. Thus, the gates of the FETs 121L, 122L, and 123L are connected to GND, and the FETs 121L, 122L, and 123L are turned off. For example, when the control for forming the neutral point is performed, there is a possibility that some further trouble occurs. In this case, by turning on the switching circuit 162, the FETs 121L, 122L, 123L can be forcibly turned off. In addition, when control for forcibly turning off the FETs 121L, 122L, 123L is not necessary, the switch circuit 162 may be omitted. When the power conversion apparatus 100 does not include the switching circuit 162, the operation of the 1 st inverter 120 may be forcibly stopped by turning off the drive circuit 350 and the switching circuit 161.

Fig. 28 schematically shows an example of the circuit configuration of the sub-drive circuit 160L. In fig. 28, the illustration of the 2 nd inverter 130 is omitted for ease of understanding of the sub-drive circuit 160L. In the example shown in fig. 28, the sub-driver circuit 160L is a circuit having a transistor of an open collector output system. The switching circuit 161 (fig. 27) has switching elements 10, 11, 12, and 13. The switching circuit 162 (fig. 27) has switching elements 20, 21, 22, and 23. The switching circuits 161 and 162 are, for example, push-pull circuits, respectively.

In the example shown in fig. 28, the switching elements 11, 12, 13, and 20 are PNP bipolar transistors. The switching elements 10, 21, 22, and 23 are NPN bipolar transistors. Hereinafter, an example in which bipolar transistors are used as the switching elements 10, 11, 12, 13, 20, 21, 22, and 23 will be described, and these switching elements may be referred to as transistors.

The base of the transistor 10 is connected to the microcontroller 340. The emitter of the transistor 10 is connected to GND. The collector of transistor 10 is connected to the bases of transistors 11, 12, 13.

The emitters of the transistors 11, 12, 13 are connected to a voltage source 163. The collector of the transistor 11 is connected to the gate of the FET 121L. The collector of transistor 12 is connected to the gate of FET 122L. The collector of the transistor 13 is connected to the gate of the FET 123L.

The base of transistor 20 is connected to microcontroller 340. The emitter of transistor 20 is connected to a voltage source Vcc. The collector of transistor 20 is connected to the bases of transistors 21, 22, 23.

The emitters of the transistors 21, 22, and 23 are connected to GND. The collector of the transistor 21 is connected to the gate of the FET 121L. The collector of transistor 22 is connected to the gate of FET 122L. The collector of transistor 23 is connected to the gate of FET 123L.

Protection circuits 31, 32, and 33 are connected between the gates and sources of the FETs 121L, 122L, and 123L, and resistors and diodes are connected in parallel to the protection circuits 31, 32, and 33. Protection circuits 41, 42, and 43 are connected between the gates and sources of the FETs 121H, 122H, and 123H, and resistors and diodes are connected in parallel to the protection circuits 41, 42, and 43.

The protection circuit 51 is connected between an output terminal (not shown) of the drive circuit 350 connected to the gate of the FET121L and GND. The protection circuit 52 is connected between an output terminal (not shown) of the drive circuit 350 connected to the gate of the FET122L and GND. The protection circuit 53 is connected between an output terminal (not shown) of the drive circuit 350 connected to the gate of the FET123L and GND.

In normal control of the 1 st inverter 120, the microcontroller 340 turns off the transistors 10 and 20. By turning off the transistors 10 and 20, the transistors 11, 12, 13, 21, 22, and 23 are turned off.

Next, an operation of forming a neutral point at the node N1 on the low side will be described. When a neutral point is formed at the node N1, the microcontroller 340 turns off the gate control signal output from the driver circuit 350 to the FETs 121L, 122L, 123L. At the same time, the microcontroller 340 turns on the transistor 10. When the transistor 10 is turned on, the bases of the transistors 11, 12, and 13 become GND level, and the transistors 11, 12, and 13 are turned on.

When the transistors 11, 12, and 13 are turned on, the voltage of the voltage source 163 is supplied to the FETs 121L, 122L, and 123L as the gate control signal. This enables the FETs 121L, 122L, 123L to be supplied with a higher gate voltage than in the normal state. By increasing the gate voltage, even if the source potential becomes a potential of a neutral point, a drop in the gate-source voltage can be suppressed. This can suppress an increase in the source-drain resistance of the FETs 121L, 122L, 123L in the on state, and can suppress the FETs 121L, 122L, 123L from being in the off state undesirably.

The protection circuits 51, 52, and 53 suppress the supply of a voltage higher than or equal to the withstand voltage to the output terminal of the drive circuit 350 connected to the gates of the FETs 121L, 122L, and 123L. The withstand voltage here is, for example, the withstand voltage of the circuit element of the drive circuit 350 that outputs the gate control signal for the FETs 121L, 122L, 123L in normal control.

The protection circuits 51, 52, 53 are, for example, zener diodes. The protection circuits 51, 52, and 53 function when the voltage of the gate control signal output from the sub-drive circuit 160L is equal to or higher than the withstand voltage. For example, when the withstand voltage is 18V, the protection circuits 51, 52, and 53 function when the voltage of the gate control signal is 17V or more. Accordingly, the voltage supplied to the output terminal of the driver circuit 350 connected to the gates of the FETs 121L, 122L, 123L can be made smaller than the withstand voltage. In this example, a gate voltage higher than that in the normal state is supplied to the FETs 121L, 122L, 123L. Even if the high gate voltage is undesirably higher than the withstand voltage, the protection circuits 51, 52, and 53 can protect the drive circuit 350.

Next, an operation of forcibly turning off the FETs 121L, 122L, 123L will be described. When the FETs 121L, 122L, 123L are forcibly turned off, the microcontroller 340 turns on the transistor 20. When the transistor 20 is turned on, the bases of the transistors 21, 22, and 23 become the level of the voltage source Vcc, and the transistors 21, 22, and 23 are turned on. When the transistors 21, 22, and 23 are turned on, the gates of the FETs 121L, 122L, and 123L are at GND level. This can forcibly turn off the FETs 121L, 122L, 123L.

Further, the same circuit as the sub-drive circuit 160L may be connected to the 2 nd inverter 130. Fig. 29 schematically shows the power conversion apparatus 100 having the sub drive circuit 160R of the present embodiment. The sub-driver circuit 160L is connected to the FETs 121L, 122L, 123L of the 1 st inverter 120. On the other hand, the sub-driver circuit 160R is connected to the FETs 131L, 132L, 133L of the 2 nd inverter 130. The other circuit configuration of the sub-driver circuit 160R is the same as that of the sub-driver circuit 160L described with reference to fig. 27 and 28.

In the case where an open fault or a short fault occurs in at least 1 of the FETs 121H, 122H, 123H of the 1 st inverter 120, the node N1 on the low side constitutes a neutral point as described above. Similarly, when at least 1 of the FETs 131H, 132H, 133H of the 2 nd inverter 130 has an open-circuit fault or a short-circuit fault, the node N2 on the low side forms a neutral point. In this case, the voltage of the gate control signal for turning on the FETs 131L, 132L, 133L is set to be higher than that in the normal state using the sub-driver circuit 160R. This can suppress an increase in the source-drain resistance of the FETs 131L, 132L, 133L in the on state, and can suppress the FETs 131L, 132L, 133L from being in the off state undesirably.

The power conversion apparatus 100 may include both the sub-drive circuits 160L and 160R, or may include only one of the sub-drive circuits 160L and 160R.

In the above example, the switching circuits 161 and 162 having transistors are exemplified, but the switching circuits 161 and 162 may have analog switches. For example, the switch circuits 161 and 162 may have single-throw switches.

Next, another example of the sub-drive circuit will be described.

Fig. 30 schematically shows the power conversion apparatus 100 having the sub-drive circuit 170L of the present embodiment. The sub-driver circuit 170L is connected to the FETs 121H, 122H, 123H, 121L, 122L, 123L.

When at least 1 of the FETs 121H, 122H, 123H has an open-circuit fault or a short-circuit fault, a neutral point is formed at the node N1. As described above, in the normal control of the 1 st inverter 120, the voltage of the gate control signal for turning on the FETs 121H, 122H, 123H is larger than the voltage of the gate control signal for turning on the FETs 121L, 122L, 123L. In this example, when the node N1 constitutes a neutral point, gate control signals of relatively high voltages for the FETs 121H, 122H, and 123H are supplied to the FETs 121L, 122L, and 123L. In this example, the driving circuit 350 is a charge pump system. The drive circuit 350 generates a gate control signal having the GND potential as a reference potential, instead of generating a gate control signal having the source potential as a reference potential.

The sub-driving circuit 170L includes switching circuits 171 and 172. When the node N1 of the 1 st inverter 120 constitutes a neutral point, the microcontroller 340 turns off the switch circuit 172 and turns on the switch circuit 171. In this way, the gate control signals for the FETs 121H, 122H, 123H output from the driver circuit 350 with a higher voltage are supplied to the FETs 121L, 122L, 123L, rather than to the FETs 121H, 122H, 123H.

Fig. 31 schematically shows an example of the circuit configuration of the sub-driver circuit 170L. In order to easily understand the sub-drive circuit 170L, the illustration of the 2 nd inverter 130 is omitted in fig. 31. In the example shown in fig. 31, the sub-driver circuit 170L is a circuit having a transistor of an open collector output system. The switching circuit 171 (fig. 30) includes switching elements 60, 61, 62, and 63. The switching circuit 172 (fig. 30) has switching elements 70, 71, 72, 73. The switching circuits 171 and 172 are, for example, push-pull circuits, respectively.

In the example shown in fig. 31, the switching elements 60 and 70 are NPN-type bipolar transistors. The switching elements 61, 62, 63, 71, 72, 73 are PNP bipolar transistors. Hereinafter, an example in which bipolar transistors are used as the switching elements 60, 61, 62, 63, 70, 71, 72, 73 will be described, and these switching elements may be referred to as transistors.

The base of transistor 60 is connected to microcontroller 340. The emitter of the transistor 60 is connected to GND. The collector of transistor 60 is connected to the bases of transistors 61, 62, 63.

The emitter of the transistor 61 is connected to the drive circuit 350 side of the control line for the gate of the FET 121H. The emitter of the transistor 61 may be connected to an output terminal (not shown) of the driver circuit 350 that outputs a gate control signal for the FET121H, for example.

The emitter of the transistor 62 is connected to the driver circuit 350 side of the control line for the gate of the FET 122H. The emitter of the transistor 62 may be connected to an output terminal (not shown) of the driver circuit 350 that outputs a gate control signal for the FET122H, for example.

The emitter of the transistor 63 is connected to the drive circuit 350 side of the control line for the gate of the FET 123H. The emitter of the transistor 63 may be connected to an output terminal (not shown) of the driver circuit 350 that outputs a gate control signal for the FET123H, for example.

The collector of the transistor 61 is connected to the gate of the FET 121L. The collector of transistor 62 is connected to the gate of FET 122L. The collector of transistor 63 is connected to the gate of FET 123L.

The base of transistor 70 is connected to microcontroller 340. The emitter of the transistor 70 is connected to GND. The collector of transistor 70 is connected to the bases of transistors 71, 72, 73.

The collector of the transistor 71 is connected to the gate of the FET 121H. The collector of transistor 72 is connected to the gate of FET 122H. The collector of transistor 73 is connected to the gate of FET 123H.

The emitter of the transistor 71 is connected to a control line for the gate of the FET 121H. The emitter of the transistor 71 is connected to the control line at a position closer to the FET121H side than a connection point between the control line and the emitter of the transistor 61.

The emitter of the transistor 72 is connected to a control line for the gate of the FET 122H. The emitter of the transistor 72 is connected to the control line at a position closer to the FET122H side than the connection point between the control line and the emitter of the transistor 62.

The emitter of the transistor 73 is connected to a control line for the gate of the FET 123H. The emitter of the transistor 73 is connected to the control line at a position closer to the FET123H side than a connection point between the control line and the emitter of the transistor 63.

The protection circuit 51 is connected between an output terminal (not shown) of the drive circuit 350 connected to the gate of the FET121L and GND. The protection circuit 52 is connected between an output terminal (not shown) of the drive circuit 350 connected to the gate of the FET122L and GND. The protection circuit 53 is connected between an output terminal (not shown) of the drive circuit 350 connected to the gate of the FET123L and GND. Accordingly, even when the gate voltage supplied to the gates of the FETs 121L, 122L, 123L is high, the voltage applied to the output terminal of the driver circuit 350 can be made smaller than the withstand voltage.

In normal control of the 1 st inverter 120, the microcontroller 340 turns on the transistor 70. When the transistor 70 is turned on, the bases of the transistors 71, 72, and 73 become GND level, and the transistors 71, 72, and 73 are turned on. And, the microcontroller 340 turns off the transistor 60. By turning off the transistor 60, the transistors 61, 62, and 63 are turned off. Thus, the gate control signals for the FETs 121H, 122H, 123H output from the driver circuit 350 are supplied to the FETs 121H, 122H, 123H.

Next, an operation of forming a neutral point at the node N1 on the low side will be described. When a neutral point is formed at node N1, microcontroller 340 turns off transistor 70. By turning off the transistor 70, the transistors 71, 72, and 73 are turned off. At the same time, the microcontroller 340 turns on the transistor 60. When the transistor 60 is turned on, the bases of the transistors 61, 62, and 63 become GND level, and the transistors 61, 62, and 63 are turned on.

When the transistor 61 is turned on, the gate control signal for the FET121H output from the driver circuit 350 is supplied to the FET121L through the transistor 61. When the transistor 62 is turned on, the gate control signal for the FET122H output from the driver circuit 350 is supplied to the FET122L through the transistor 62. When the transistor 63 is turned on, the gate control signal for the FET123H output from the driver circuit 350 is supplied to the FET123L through the transistor 63.

This enables the FETs 121L, 122L, 123L to be supplied with a higher gate voltage than in the normal state. By increasing the gate voltage, even if the source potential becomes a potential of a neutral point, a drop in the gate-source voltage can be suppressed. This can suppress an increase in the source-drain resistance of the FETs 121L, 122L, 123L in the on state, and can suppress the FETs 121L, 122L, 123L from being in the off state undesirably.

When the operation of the 1 st inverter 120 is forcibly stopped, the switching circuits 171 and 172 are turned off, and the gate control signals for the FETs 121L, 122L, and 123L output from the driving circuit 350 are turned off. This can forcibly stop the operation of the 1 st inverter 120.

The same circuit as the sub-driving circuit 170L may be connected to the 2 nd inverter 130. Fig. 32 schematically shows the power conversion apparatus 100 having the sub-drive circuit 170R of the present embodiment. The sub-driver circuit 170L is connected to the FETs 121H, 122H, 123H, 121L, 122L, 123L of the 1 st inverter 120. On the other hand, the sub-driver circuit 170R is connected to the FETs 131H, 132H, 133H, 131L, 132L, and 133L of the 2 nd inverter 130. The other circuit configuration of the sub-driver circuit 170R is the same as that of the sub-driver circuit 170L described with reference to fig. 30 and 31.

In the case where an open fault or a short fault occurs in at least 1 of the FETs 121H, 122H, 123H of the 1 st inverter 120, the node N1 on the low side constitutes a neutral point as described above. Similarly, when at least 1 of the FETs 131H, 132H, 133H of the 2 nd inverter 130 has an open-circuit fault or a short-circuit fault, the node N2 on the low side forms a neutral point. In this case, the voltage of the gate control signal for turning on the FETs 131L, 132L, 133L is set to be higher than that in the normal state by the sub-driver circuit 170R. This can suppress an increase in the source-drain resistance of the FETs 131L, 132L, 133L in the on state, and can suppress the FETs 131L, 132L, 133L from being in the off state undesirably.

The power conversion apparatus 100 may include both the sub-driver circuits 170L and 170R, or may include only one of the sub-driver circuits 170L and 170R.

In the above example, the switching circuits 171 and 172 having transistors are exemplified, but the switching circuits 171 and 172 may have analog switches. The switch circuits 171, 172 may have, for example, single throw switches. The switch circuits 171 and 172 may have double-throw switches, for example. In order to suppress the influence on the PWM control, an analog switch having a small on-resistance (for example, several tens of m Ω to several Ω) can be used as the analog switch used on the high side.

As described above, in the present embodiment, the fault diagnosis is performed to diagnose whether or not the FETs included in the 1 st and 2 nd inverters 120 and 130 have a fault. In the aspect in which the power conversion device 100 includes the sub-drive circuit described above, the diagnosis in the state in which the neutral point is formed on the low side may be performed before the diagnosis in the state in which the neutral point is formed on the high side.

For example, in the embodiment in which the power conversion device 100 includes the sub-drive circuit 160L or 170L, the control circuit 300 performs diagnosis by configuring the neutral point (node N1) on the low side of the 1 st inverter 120 before diagnosis by configuring the neutral point (node N3) on the high side of the 1 st inverter 120. For example, the control circuit 300 performs the diagnosis shown in fig. 12 before the diagnosis shown in fig. 16.

For example, in the embodiment in which the power conversion device 100 includes the sub-drive circuit 160R or 170R, the control circuit 300 performs diagnosis by configuring the neutral point (node N2) on the low side of the 2 nd inverter 130 before diagnosis by configuring the neutral point (node N4) on the high side of the 2 nd inverter 130. For example, the control circuit 300 performs the diagnosis shown in fig. 20 before the diagnosis shown in fig. 24.

For example, in the mode in which the power conversion apparatus 100 includes the sub-drive circuits 160L and 160R, the control circuit 300 performs the diagnosis shown in fig. 12 and 20 before the diagnosis shown in fig. 16 and 24.

For example, in the mode in which the power conversion apparatus 100 includes the sub-drive circuits 170L and 170R, the control circuit 300 performs the diagnosis shown in fig. 12 and 20 before the diagnosis shown in fig. 16 and 24.

(embodiment mode 2)

Vehicles such as automobiles generally have an electric power steering apparatus. The electric power steering apparatus generates an assist torque for assisting a steering torque of a steering system generated by a driver operating a steering wheel. The assist torque is generated by the assist torque mechanism, and the operation load of the driver can be reduced. For example, the assist torque mechanism includes a steering torque sensor, an ECU, a motor, a speed reduction mechanism, and the like. The steering torque sensor detects a steering torque in the steering system. The ECU generates a drive signal based on a detection signal of the steering torque sensor. The motor generates an assist torque corresponding to the steering torque in accordance with the drive signal, and transmits the assist torque to the steering system via the speed reduction mechanism.

The motor drive unit 400 of the present disclosure is suitably used for an electric power steering apparatus. Fig. 33 schematically shows a typical configuration of an electric power steering apparatus 500 according to the present embodiment. The electric power steering apparatus 500 has a steering system 520 and an assist torque mechanism 540.

The steering system 520 includes, for example, a steering wheel 521, a steering shaft 522 (also referred to as a "steering column"), universal joints 523A and 523B, a rotary shaft 524 (also referred to as a "pinion shaft" or an "input shaft"), a rack-and-pinion mechanism 525, a rack shaft 526, left and right ball joints 552A and 552B, tie rods 527A and 527B, steering knuckles 528A and 528B, and left and right steered wheels (e.g., left and right front wheels) 529A and 529B. The steering wheel 521 is connected to the rotating shaft 524 via the steering shaft 522 and the universal joints 523A and 523B. A rack shaft 526 is connected to the rotating shaft 524 via a rack and pinion mechanism 525. The rack and pinion mechanism 525 includes a pinion 531 provided on the rotating shaft 524 and a rack 532 provided on the rack shaft 526. A right steering wheel 529A is connected to a right end of the rack shaft 526 through a ball joint 552A, a tie rod 527A, and a knuckle 528A in this order. Similarly to the right side, a left steered wheel 529B is connected to the left end of the rack shaft 526 through a ball joint 552B, a tie rod 527B, and a knuckle 528B in this order. Here, the right side and the left side correspond to the right side and the left side, respectively, as viewed from the driver sitting on the driver's seat.

According to the steering system 520, a steering torque is generated by the driver operating the steering wheel 521, and the steering torque is transmitted to the left and right steering wheels 529A and 529B via the rack and pinion mechanism 525. This allows the driver to operate the left and right steerable wheels 529A and 529B.

The assist torque mechanism 540 includes, for example, a steering torque sensor 541, an ECU542, a motor 543, a reduction mechanism 544, and a power conversion device 545. The assist torque mechanism 540 provides assist torque to the steering system 520 from the steering wheel 521 to the left and right steered wheels 529A, 529B. In addition, the assist torque is sometimes referred to as "additional torque".

Control circuit 300 according to embodiment 1 can be used as ECU542, and power conversion device 100 according to embodiment 1 can be used as power conversion device 545. The motor 543 corresponds to the motor 200 in embodiment 1. The motor drive unit 400 of embodiment 1 can be suitably used as an electromechanical integrated unit having the ECU542, the motor 543, and the power conversion device 545.

The steering torque sensor 541 detects a steering torque of the steering system 520 applied by the steering wheel 521. The ECU542 generates a drive signal for driving the motor 543 based on a detection signal (hereinafter referred to as "torque signal") from the steering torque sensor 541. The motor 543 generates an assist torque corresponding to the steering torque in accordance with the drive signal. The assist torque is transmitted to the rotary shaft 524 of the steering system 520 via the speed reduction mechanism 544. The reduction mechanism 544 is, for example, a worm gear mechanism. The assist torque is transmitted from the rotating shaft 524 to the rack and pinion mechanism 525.

The electric power steering apparatus 500 can be classified into a pinion assist type, a rack assist type, a column assist type, and the like according to a portion where assist torque is applied to the steering system 520. Fig. 33 illustrates a pinion-assist electric power steering apparatus 500. However, the electric power steering apparatus 500 may be a rack assist type, a column assist type, or the like.

The ECU542 can be inputted with not only a torque signal but also a vehicle speed signal, for example. The external device 560 is, for example, a vehicle speed sensor. Alternatively, the external device 560 may be another ECU that can communicate using an in-vehicle network such as can (controller Area network). The microcontroller of the ECU542 can perform vector control or PWM control on the motor 543 in accordance with the torque signal, the vehicle speed signal, or the like.

The ECU542 sets a target current value based on at least the torque signal. Preferably, ECU542 sets the target current value in consideration of a vehicle speed signal detected by a vehicle speed sensor, and further in consideration of a rotor rotation signal detected by an angle sensor. The ECU542 can control a drive current, which is a drive signal of the motor 543, so that an actual current value detected by a current sensor (not shown) matches a target current value.

According to the electric power steering apparatus 500, the left and right steered wheels 529A and 529B can be operated by the rack shaft 526 using a composite torque obtained by adding the steering torque of the driver to the assist torque of the motor 543. In particular, by using the motor drive unit 400 of the present disclosure in the above-described electromechanical integrated unit, it is possible to provide an electric power steering apparatus having a motor drive unit that can improve the quality of components and can appropriately control the current at both the normal time and the abnormal time.

Industrial applicability

Embodiments of the present disclosure can be widely applied to various apparatuses having various motors, such as a vacuum cleaner, a blower, a ceiling fan, a washing machine, a refrigerator, and an electric power steering apparatus.

Claims (17)

1. A power conversion device (100) that converts power from a power source (101) into power to be supplied to a motor (200) having n-phase windings, where n is an integer of 3 or more,

the power conversion device includes:

a 1 st inverter (120) connected to one end of each phase winding of the motor;

a 2 nd inverter (130) connected to the other end of each phase winding;

a control circuit (300);

a drive circuit (350); and

a 1 st sub-driver circuit (160L),

the 1 st inverter (120) comprises a bridge circuit consisting of 3 branches,

each branch having a 1 st low-side switching element (121L), a 2 nd low-side switching element (122L), a 3 rd low-side switching element (123L), and a 1 st high-side switching element (121H), a 2 nd high-side switching element (122H), a 3 rd high-side switching element (123H),

the 2 nd inverter (130) comprises a bridge circuit consisting of 3 branches,

each of the branches has a 4 th low-side switching device (131L), a 5 th low-side switching device (132L), a 6 th low-side switching device (133L), and a 4 th high-side switching device (131H), a 5 th high-side switching device (132H), a 6 th high-side switching device (133H),

the 1 st sub-driver circuit (160L) is connected (123L) to the 1 st low-side switching device (121L), the 2 nd low-side switching device (122L), and the 3 rd low-side switching device.

2. The power conversion apparatus according to claim 1,

the 1 st sub-driver circuit (160L) has a transistor of an open collector output system.

3. The power conversion apparatus according to claim 1,

the 1 st sub-drive circuit (160L) has a 1 st switch circuit (161) and a 2 nd switch circuit (162),

the 1 st switching circuit (161) has a 1 st switching element (10), a 2 nd switching element (11), a 3 rd switching element (12), and a 4 th switching element (13),

the 2 nd switching circuit (162) has a 5 th switching element (20), a 6 th switching element (21), a 7 th switching element (22), and an 8 th switching element (23).

4. The power conversion apparatus according to claim 3,

the 2 nd switching element (11), the 3 rd switching element (12), the 4 th switching element (13), and the 5 th switching element (20) are PNP type bipolar transistors,

the 1 st switching element (10), the 6 th switching element (21), the 7 th switching element (22), and the 8 th switching element (23) are NPN-type bipolar transistors.

5. The power conversion apparatus according to claim 4,

the control circuit (300) has a microcontroller (340),

the driver circuit (350) has a voltage booster circuit (370),

the base of the 1 st switching element (10) is connected to the microcontroller (340),

the emitter of the 1 st switching element (10) is connected to Ground (GND),

a collector of the 1 st switching element (10) is connected to bases of the 2 nd switching element (11), the 3 rd switching element (12), and the 4 th switching element (13),

emitters of the 2 nd switching element (11), the 3 rd switching element (12), and the 4 th switching element (13) are connected to a 1 st voltage source (163) generated by the booster circuit,

a collector of the 2 nd switching element (11) is connected to a gate of the 1 st low-side switching element (121L),

a collector of the 3 rd switching element (12) is connected to a gate of the 2 nd low-side switching element (122L),

a collector of the 4 th switching element (13) is connected to a gate of the 3 rd low-side switching element (123L),

the base of the 5 th switching element (20) is connected to a microcontroller (340),

the emitter of the 5 th switching element (20) is connected to a 2 nd voltage source (Vcc),

a collector of the 5 th switching element (20) is connected to bases of the 6 th switching element (21), the 7 th switching element (22), and the 8 th switching element (23),

emitters of the 6 th switching element (21), the 7 th switching element (22), and the 8 th switching element (23) are connected to Ground (GND),

a collector of the 6 th switching element (21) is connected to a gate of the 1 st low-side switching element (121L),

a collector of the 7 th switching element (22) is connected to a gate of the 2 nd low-side switching element (122L),

the collector of the 8 th switching element (23) is connected to the gate of the 3 rd low-side switching element (123L).

6. The power conversion apparatus according to claim 1,

the power conversion device (100) includes a 1 st protection circuit (51), a 2 nd protection circuit (52), and a 3 rd protection circuit (53),

the 1 st protection circuit (51) is provided between an output terminal of the drive circuit (350) connected to the gate of the 1 st low-side switching element (121L) and Ground (GND),

the 2 nd protection circuit (52) is provided between an output terminal of the drive circuit (350) connected to the gate of the 2 nd low-side switching element (122L) and Ground (GND),

the 3 rd protection circuit (53) is provided between an output terminal of the driver circuit (350) connected to the gate of the 3 rd low-side switching element (123L) and Ground (GND).

7. The power conversion apparatus according to claim 6,

the 1 st protection circuit (51), the 2 nd protection circuit (52), and the 3 rd protection circuit (53) are zener diodes.

8. The power conversion apparatus according to claim 1,

the power conversion apparatus (100) has a 2 nd sub-drive circuit (160R),

the 2 nd sub-driver circuit (160R) is connected to the 4 th low-side switching device (131L), the 5 th low-side switching device (132L), and the 6 th low-side switching device (133L).

9. A motor drive unit is characterized in that,

having a power conversion device (100) of claim 1; and

the motor (200).

10. An electric power steering apparatus characterized by having the motor drive unit (400) of claim 9.

11. A power conversion device (100) that converts power from a power source (101) into power to be supplied to a motor (200) having n-phase windings, where n is an integer of 3 or more,

the power conversion device (100) comprises:

a 1 st inverter (120) connected to one end of each phase winding of the motor;

a 2 nd inverter (130) connected to the other end of each phase winding;

a control circuit (300);

a drive circuit (350); and

a 3 rd sub-driving circuit (170L),

the 1 st inverter (120) comprises a bridge circuit consisting of 3 branches,

each branch having a 1 st low-side switching element (121L), a 2 nd low-side switching element (122L), a 3 rd low-side switching element (123L), and a 1 st high-side switching element (121H), a 2 nd high-side switching element (122H), a 3 rd high-side switching element (123H),

the 2 nd inverter (130) comprises a bridge circuit consisting of 3 branches,

each of the branches has a 4 th low-side switching device (131L), a 5 th low-side switching device (132L), a 6 th low-side switching device (133L), and a 4 th high-side switching device (131H), a 5 th high-side switching device (132H), a 6 th high-side switching device (133H),

the 3 rd sub-driver circuit (170L) is connected to the 1 st low-side switching device (121L), the 2 nd low-side switching device (122L), the 3 rd low-side switching device (123L), and the 1 st high-side switching device (121H), the 2 nd high-side switching device (122H), and the 3 rd high-side switching device (123H).

12. The power conversion apparatus according to claim 11,

the 3 rd sub-driver circuit (170L) has a transistor of an open collector output system.

13. The power conversion apparatus according to claim 11,

the 3 rd sub-drive circuit (170L) has a 3 rd switch circuit (171) and a 4 th switch circuit (172),

the 3 rd switching circuit (171) has a 9 th switching element (60), a 10 th switching element (61), an 11 th switching element (62), and a 12 th switching element (63),

the 4 th switching circuit (172) has a 13 th switching element (70), a 14 th switching element (71), a 15 th switching element (72), and a 16 th switching element (73),

the 9 th switching element (60) and the 13 th switching element (70) are NPN type bipolar transistors,

the 10 th switching element (61), the 11 th switching element (62), the 12 th switching element (63), the 14 th switching element (71), the 15 th switching element (72), and the 16 th switching element (73) are PNP-type bipolar transistors.

14. The power conversion apparatus according to claim 13,

the power conversion apparatus has a booster circuit (370) and a microcontroller (340),

the base of the 9 th switching element (60) is connected to the microcontroller,

an emitter of the 9 th switching element (60) is connected to Ground (GND),

a collector of the 9 th switching element (60) is connected to bases of the 10 th switching element (61), the 11 th switching element (62), and the 12 th switching element (63),

the emitter of the 10 th switching element (61) is connected to the drive circuit (350) side of the control line for the gate of the 1 st high-side switching element (121H),

a collector of the 10 th switching element (61) is connected to a gate of the 1 st low-side switching element (121L),

the emitter of the 11 th switching element (62) is connected to the drive circuit (350) side of the control line for the gate of the 2 nd high-side switching element (122H),

a collector of the 11 th switching element (62) is connected to a gate of the 2 nd low-side switching element (122L),

the emitter of the 12 th switching element (63) is connected to the drive circuit (350) side of the control line for the gate of the 3 rd high-side switching element (123H),

a collector of the 12 th switching element (63) is connected to a gate of the 3 rd low-side switching element (123L),

the base of the 13 th switching element (70) is connected to the microcontroller,

an emitter of the 13 th switching element (70) is connected to Ground (GND),

a collector of the 13 th switching element (70) is connected to bases of the 14 th switching element (71), the 15 th switching element (72), and the 16 th switching element (73),

an emitter of the 14 th switching element (71) is connected to a control line for a gate of the 1 st high-side switching element (121H),

a collector of the 14 th switching element (71) is connected to a gate of the 1 st high-side switching element (121H),

an emitter of the 15 th switching element (72) is connected to a control line for a gate of the 2 nd high-side switching element (122H),

a collector of the 15 th switching element (72) is connected to a gate of the 2 nd high-side switching element (122H),

an emitter of the 16 th switching element (73) is connected to a control line for a gate of the 3 rd high-side switching element (123H),

the collector of the 16 th switching element (73) is connected to the gate of the 3 rd high-side switching element (123H).

15. The power conversion apparatus according to claim 11,

the power conversion apparatus has a 4 th sub-drive circuit (170R),

the 4 th sub-driver circuit (170R) is connected to the 4 th low-side switching device (131L), the 5 th low-side switching device (132L), the 6 th low-side switching device (133L), and the 4 th high-side switching device (131H), the 5 th high-side switching device (132H), and the 6 th high-side switching device (133H).

16. A motor drive unit is characterized in that,

having the power conversion apparatus (100) of claim 11; and

the motor (200).

17. An electric power steering apparatus characterized by having the motor drive unit (400) according to claim 16.

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