CN216145101U

CN216145101U - Double-channel high-speed data playback device

Info

Publication number: CN216145101U
Application number: CN202121581673.2U
Authority: CN
Inventors: 高前英; 江栾凤
Original assignee: Hefei Alabeta Electronic Technology Co ltd
Current assignee: Hefei Alabeta Electronic Technology Co ltd
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2022-03-29
Anticipated expiration: 2031-07-09

Abstract

The utility model discloses a dual-channel high-speed data playback device, which comprises: the FPGA chip is respectively connected with 4 DDR3 memory chips; the FPGA chip is connected with an upper computer through a kilomega network port; the FPGA chip also receives an external trigger signal through a trigger control module; the clock distribution network transmits a clock signal to the two-channel analog-to-digital converter and the FPGA chip after receiving an external clock signal; the FPGA chip is connected with external equipment through a two-channel analog-to-digital converter; data stored in the DDR3 memory chip are called according to signals transmitted by the upper computer, and the double-channel analog-to-digital converter receives the data transmitted by the FPGA chip, converts the data and outputs the data to external equipment. The utility model realizes the double-channel data playback by the matching of the FPGA chip, the DDR3 internal memory chip and the double-channel analog-to-digital converter, selects an acquisition channel and a sampling rate through signals received by the FPGA chip, and has the DAC playback analog delay function by setting a synchronous clock network, thereby stepping by 25 ps.

Description

Double-channel high-speed data playback device

Technical Field

The utility model belongs to the technical field of data acquisition, and particularly relates to a dual-channel high-speed data playback device.

Background

The data acquisition card is an important component of a measurement and control instrument, collects various analog quantity or digital quantity, converts the analog quantity into a digital signal through an AD converter, or acquires the digital quantity into a digital signal through an acquisition processor, and outputs an effective digital signal after the digital signal is processed by a digital processing chip.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a double-channel high-speed data playback device, which realizes double-channel data playback by matching an FPGA chip, a DDR3 memory chip and a double-channel analog-to-digital converter, selects an acquisition channel and a sampling rate through a signal received by the FPGA chip, and has a DAC (digital-to-analog converter) playback analog delay function by setting a synchronous clock network, wherein the step is 25 ps; has simple structure and low cost.

In order to solve the technical problems, the utility model is realized by the following technical scheme:

the utility model relates to a double-channel high-speed data playback device, which comprises an FPGA chip, a power module, a clock distribution network and a double-channel analog-to-digital converter, wherein the FPGA chip is connected with the power module through a power line; the FPGA chip is respectively connected with 4 DDR3 memory chips; the FPGA chip is connected with an upper computer through a kilomega network port; the FPGA chip also receives an external trigger signal through a trigger control module; the clock distribution network receives an external clock signal and then transmits the clock signal to the two-channel analog-to-digital converter and the FPGA chip; the FPGA chip is connected with external equipment through a two-channel analog-to-digital converter; the data stored in the DDR3 memory chip is called after the signals transmitted by the upper computer are received, and the double-channel analog-to-digital converter receives the data transmitted by the FPGA chip, converts the data and outputs the data to external equipment; the power supply module supplies power for the FPGA chip, the DDR3 memory chip and the dual-channel analog-to-digital converter respectively.

Further, the model of the FPGA chip is 5AGZME1H2F35C 3N; and the FPGA chip receives the trigger signal and then controls the dual-channel analog-to-digital converter to start outputting the signal.

Further, the model of the two-channel analog-to-digital converter is ADS54J 42; the maximum sampling rate of the double-channel analog-to-digital converter is 500 MHz.

Furthermore, the FPGA chip is also connected with an active crystal oscillator.

Furthermore, the FPGA chip is communicated with an upper computer through a USB3.0 interface and an optical module.

The utility model has the following beneficial effects:

the utility model realizes the double-channel data playback by the matching of the FPGA chip, the DDR3 internal memory chip and the double-channel analog-to-digital converter, selects an acquisition channel and a sampling rate through a signal received by the FPGA chip, and has the DAC playback analog delay function by setting a synchronous clock network, and the step is 25 ps; has simple structure and low cost.

Of course, it is not necessary for any product in which the utility model is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a system block diagram of a dual channel high speed data playback device;

fig. 2 is a flowchart of the operation of a dual-channel high-speed data playback apparatus.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The first embodiment is as follows:

referring to fig. 1, the present invention is a dual-channel high-speed data playback apparatus, including an FPGA chip, a power module, a clock distribution network, and a dual-channel analog-to-digital converter; the model of the two-channel analog-to-digital converter is ADS54J 42; the maximum sampling rate of the double-channel analog-to-digital converter is 500 MHz; the model of the FPGA chip is 5AGZME1H2F35C 3N; the FPGA chip receives the trigger signal and then controls the two-channel analog-to-digital converter to start outputting a signal;

the FPGA chip is respectively connected with 4 DDR3 memory chips; the FPGA chip is connected with an upper computer through a kilomega network port; the FPGA chip also receives an external trigger signal through a trigger control module; the clock distribution network receives an external clock signal and then transmits the clock signal to the two-channel analog-to-digital converter and the FPGA chip;

the FPGA chip is connected with external equipment through a two-channel analog-to-digital converter; the data stored in the DDR3 memory chip is called after the signals transmitted by the upper computer are received, and the double-channel analog-to-digital converter receives the data transmitted by the FPGA chip, converts the data and outputs the data to external equipment; the power module supplies power for an FPGA chip, a DDR3 memory chip and a dual-channel analog-to-digital converter respectively, the FPGA chip is further connected with an active crystal oscillator, the FPGA chip is further communicated with an upper computer through a USB3.0 interface and an optical module, and the upper computer is a PC.

Example two:

as shown in fig. 2, the present embodiment is a workflow of a dual-channel high-speed data playback apparatus, including the following steps:

the method comprises the following steps: starting, powering on a system;

step two: judging whether the PC data is received or not, if so, entering a third step, and if not, returning to the second step;

step three: putting the received PC data into a cache region;

step four: setting a signal calculation strategy according to a PC;

step five: starting a policy algorithm module to calculate cache data;

step six: selecting DAC channel output according to the setting of the PC;

step seven: and (6) ending.

In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The preferred embodiments of the utility model disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model. The utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A dual-channel high-speed data playback device is characterized by comprising an FPGA chip, a power supply module, a clock distribution network and a dual-channel analog-to-digital converter;

the FPGA chip is respectively connected with 4 DDR3 memory chips; the FPGA chip is connected with an upper computer through a kilomega network port; the FPGA chip also receives an external trigger signal through a trigger control module;

the clock distribution network receives an external clock signal and then transmits the clock signal to the two-channel analog-to-digital converter and the FPGA chip;

the FPGA chip is connected with external equipment through a two-channel analog-to-digital converter; the data stored in the DDR3 memory chip is called after the signals transmitted by the upper computer are received, and the double-channel analog-to-digital converter receives the data transmitted by the FPGA chip, converts the data and outputs the data to external equipment;

the power supply module supplies power for the FPGA chip, the DDR3 memory chip and the dual-channel analog-to-digital converter respectively.

2. The dual-channel high-speed data playback device of claim 1, wherein the FPGA chip is 5 agmme 1H2F35C 3N; and the FPGA chip receives the trigger signal and then controls the dual-channel analog-to-digital converter to start outputting the signal.

3. The dual-channel high-speed data playback device of claim 1, wherein the dual-channel analog-to-digital converter is of the type ADS54J 42; the maximum sampling rate of the double-channel analog-to-digital converter is 500 MHz.

4. The dual-channel high-speed data playback device as claimed in claim 1, wherein the FPGA chip is further connected to an active crystal oscillator.

5. The dual-channel high-speed data playback device of claim 1, wherein the FPGA chip further communicates with the upper computer through a USB3.0 interface and an optical module.