CN216054652U - Chip package carrying plate - Google Patents
Chip package carrying plate Download PDFInfo
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- CN216054652U CN216054652U CN202122016792.XU CN202122016792U CN216054652U CN 216054652 U CN216054652 U CN 216054652U CN 202122016792 U CN202122016792 U CN 202122016792U CN 216054652 U CN216054652 U CN 216054652U
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Abstract
The utility model relates to a chip packaging and loading plate. The chip packaging carrier plate comprises a metal substrate and an insulating base layer, wherein the metal substrate is provided with a first side surface and a second side surface opposite to the first side surface, the first side surface is provided with a plurality of first electrode grooves, the insulating base layer is formed in the first electrode grooves, and the second side surface is provided with a plurality of second electrode grooves. The chip packaging carrier plate provided by the application can be formed at different times by the grooves on the two opposite sides of the metal substrate, the shapes and the sizes of the grooves on the two opposite sides of the metal substrate can be designed independently, the problem that the bottom electrode and the top electrode of the chip packaging carrier plate are the same in shape and size due to process limitation is solved, and the freedom of engineering design such as the line width and wiring of the bottom electrode and the top electrode of the chip packaging carrier plate is improved.
Description
Technical Field
The utility model relates to the technical field of semiconductor devices, in particular to a chip packaging and loading plate.
Background
With the rapid development of the optoelectronic industry and the IC industry, the carrier plate for carrying the chip has a great demand, and the carrier plate not only provides the chip with supporting, protecting and heat dissipating functions, but also provides electronic connection between the chip and the PCB motherboard.
At present, metal lead carrier plates are widely applied, and besides high strength and high heat conductivity, the metal lead carrier plates are required to have good brazing performance, processing performance, etching performance, sealing performance and the like. However, the bottom electrode and the top electrode of the metal lead carrier are limited by the process and have the same shape and size, so that the problem of poor freedom of engineering design such as line width, wiring and the like exists.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide a chip package carrier with good freedom of engineering design of a metal lead carrier, aiming at the problem of poor freedom of engineering design of the metal lead carrier.
The utility model provides a chip package loading board, comprising:
the metal substrate is provided with a first side surface and a second side surface opposite to the first side surface, and the first side surface is provided with a plurality of first electrode grooves;
the insulating base layer is formed in the first electrode grooves;
the second side surface is provided with a plurality of second electrode grooves, and the plurality of second electrode grooves correspond to the plurality of first electrode grooves one to one;
the bottom of each second electrode groove is provided with a communication hole communicated with the corresponding first electrode groove, and the insulation base layer covers all the communication holes.
In one embodiment, the opening shape of at least one first electrode groove is different from the opening shape of the corresponding second electrode groove; and/or
Wherein the opening area of at least one first electrode groove is different from the opening area of the corresponding second electrode groove.
In one embodiment, a first metal layer is formed on the first side and a second metal layer is formed on the second side.
In one embodiment, the first and second plating metal layers are gold, silver, nickel, copper, tin, palladium, or an alloy thereof.
In one embodiment, the first electroplated metal layer is overlaid with a peelable high temperature resistant carrier sheet.
In one embodiment, the thickness of the insulation base layer is smaller than the groove depth of the first electrode groove.
In one embodiment, the metal substrate is a copper foil.
In one embodiment, the insulation base layer is an insulation resin base layer.
In one embodiment, the first side surface is provided with a first etching area, and a plurality of first electrode grooves are formed in the first etching area in an etching mode;
the second side surface is provided with a second etching area, and a plurality of second electrode grooves are formed in the second etching area in an etching mode.
In one embodiment, the chip package carrier further includes a first photosensitive film layer formed on the first side surface, and the first etching region is formed by patterning the first photosensitive film;
the chip packaging carrier plate further comprises a second photosensitive film layer, the second photosensitive film layer is formed on the second side face, and the second etching area is formed through patterning of the second photosensitive film.
According to the chip packaging carrier plate, the first side surface of the metal substrate is provided with the plurality of first electrode grooves, the insulating base layer is formed in the first side surface of the metal substrate and serves as an interface for the second side surface opposite to the first side surface to be provided with the plurality of second electrode grooves, so that the grooves on two opposite sides of the metal substrate can be formed at different times, the shapes and the sizes of the grooves on two opposite sides of the metal substrate can be designed independently, the shapes and the sizes of the bottom electrode and the top electrode of the chip packaging carrier plate are different, the problem that the shapes and the sizes of the bottom electrode and the top electrode of the chip packaging carrier plate are the same due to process limitation is solved, and the freedom of engineering design such as line width and wiring of the bottom electrode and the top electrode of the chip packaging carrier plate is improved.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a chip package carrier according to an embodiment of the utility model;
fig. 2 is a schematic cross-sectional view illustrating a chip package carrier according to another embodiment of the utility model;
fig. 3 is a schematic cross-sectional view illustrating a partial structure of a chip package carrier in a manufacturing process according to an embodiment of the utility model;
fig. 4 is a schematic cross-sectional view illustrating a partial structure of a chip package carrier in a manufacturing process according to another embodiment of the utility model.
Description of reference numerals:
100. a chip packaging carrier plate; 10. a metal substrate; 11. a first side surface; 111. a first electrode groove; 112. a first electroplated metal layer; 12. a second side surface; 121. a second electrode groove; 122. a second electroplated metal layer; 20. an insulating base layer; 30. a high temperature resistant carrier sheet; 41. a first photosensitive film layer; 42. a second photosensitive film layer; 50. and (3) a shielding film.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the utility model and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the utility model.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.
Furthermore, the drawings are not 1: 1, and the relative dimensions of the various elements in the figures are drawn for illustration only and not necessarily to true scale.
Fig. 1 shows a schematic cross-sectional view of a chip package carrier 100 according to an embodiment of the present application. For the purpose of illustration, the drawings show only the structures associated with embodiments of the utility model.
Referring to the drawings, in one embodiment, a chip package carrier 100 includes a metal substrate 10 and an insulating base layer 20.
The metal substrate 10 has a first side 11 and a second side 12 opposite to the first side 11, the first side 11 has a plurality of first electrode grooves 111, and the insulating base layer 20 is formed in the plurality of first electrode grooves 111.
The second side 12 has a plurality of second electrode grooves 121, the plurality of second electrode grooves 121 correspond to the plurality of first electrode grooves 111 one by one, the bottom of each second electrode groove 121 has a via hole connected to the corresponding first electrode groove 111, and the insulating base layer 20 covers all the via holes.
Specifically, in the embodiment of the present application, the first side surface 11 has a first etching region, a plurality of first electrode grooves 111 are formed in the first etching region by etching, the second side surface 12 has a second etching region, and a plurality of second electrode grooves 121 are formed in the second etching region by etching. Therefore, the processing process mainly adopts an etching process, and metal connecting ribs are not generated between the bottom electrode and the top electrode, so that when a packaged chip is cut, the metal ribs on a cutting channel can damage a cutter, and the cutting efficiency and the cutting speed are improved.
Further, as shown in fig. 3 and 4, the chip package carrier 100 further includes a peelable first photosensitive film 41, the first photosensitive film 41 is formed on the first side 11, the first etching area is formed by patterning the first photosensitive film 41, the chip package carrier 100 further includes a peelable second photosensitive film 42, the second photosensitive film 42 is formed on the second side 12, and the second etching area is formed by patterning the second photosensitive film 42. Thus, an etching region can be formed by patterning the photosensitive film, so that the first side surface 11 and the second side surface 12 of the chip package carrier 100 can be etched by using an etching solution.
It should be noted that the first side surface 11 and the groove walls of the plurality of first electrode grooves 111 on the metal substrate 10 form one of the bottom electrode and the top electrode, and the second side surface 12 and the groove walls of the plurality of second electrode grooves 121 form the other of the bottom electrode and the top electrode. In the embodiment of the present application, the first side surface 11 and the groove walls of the plurality of first electrode grooves 111 on the metal substrate 10 form a bottom electrode, and the second side surface 12 and the groove walls of the plurality of second electrode grooves 121 form a top electrode.
According to the chip packaging carrier plate 100, the first side surface 11 of the metal substrate 10 is provided with the plurality of first electrode grooves 111, the insulating base layer 20 is formed in the first side surface, and the insulating base layer serves as an interface for arranging the plurality of second electrode grooves 121 on the second side surface 12 opposite to the first side surface 11, so that the grooves on the two opposite sides of the metal substrate 10 can be formed at different times, namely, the shapes and the sizes of the grooves on the two opposite sides of the metal substrate 10 can be designed independently, and further, the shapes and the sizes of the bottom electrode and the top electrode of the chip packaging carrier plate 100 are different, so that the problem that the shapes and the sizes of the bottom electrode and the top electrode of the chip packaging carrier plate 100 are the same due to process limitation is solved, and the freedom of engineering design such as line width and wiring of the bottom electrode and the top electrode of the chip packaging carrier plate 100 is improved.
Referring to fig. 1 again, in some embodiments, the opening shape of at least one first electrode recess 111 is different from the opening shape of the corresponding second electrode recess 121. Thus, the bottom electrode and the top electrode of the chip package carrier 100 have different shapes, which can avoid the process limitation of the same shape, thereby ensuring the freedom of engineering design.
In other embodiments, the opening area of at least one first electrode groove 111 is different from the opening area of the corresponding second electrode groove 121. Thus, the bottom electrode and the top electrode of the chip package carrier 100 have different sizes, which can avoid the process limitation of the same size, thereby ensuring the freedom of engineering design.
In other embodiments, the shape of the first electrode groove 111 and the shape and the opening area of the corresponding second electrode groove 121 may be different, and are not limited herein.
In some embodiments, a first plated metal layer 112 is formed on the first side 11 and a second plated metal layer 122 is formed on the second side 12. In this manner, a metal layer is plated on the surface of the metal substrate 10 to ensure the airtightness of the package.
Preferably, the first and second plating metal layers 112 and 122 are gold, silver, nickel, copper, tin, palladium, or an alloy thereof.
It should be noted that, in other embodiments, as shown in fig. 2, when the second electrode groove 121 is etched, since the second plating metal layer 122 covers the second side 12, the second side 12 of the metal substrate 10 can be protected during the etching process of the second electrode groove 121, and only a side etching exists to form a mushroom head "T" structure on the metal base layer 10. Thus, the chip package carrier 100 can be ensured to have good air tightness. In other embodiments, the first electrode groove 111 can also protect the first side 11 from being covered by the first plating metal layer 112 during etching, which is not limited herein.
Referring to fig. 1 again, the first plating metal layer 112 is further covered with a peelable high temperature resistant carrier sheet 30. Therefore, glue overflow can be avoided during packaging, and the post-treatment process after packaging and injection molding is reduced.
Preferably, the high temperature resistant carrier sheet 30 is a PI film. Specifically, the high temperature resistant carrier sheet 30 is a PI film resistant to 300 degrees.
In some embodiments, the thickness of the insulation base layer 20 is less than the groove depth of the first electrode groove 111. Therefore, the bottom electrode can be formed in a convex shape, which is beneficial to welding and reduces cold joint.
In some embodiments, the metal substrate 10 is a copper foil. Compared with metals such as aluminum and iron, the copper foil has a better heat conduction effect, and can improve the heat dissipation performance of the chip package carrier 100.
In some embodiments, the insulation base layer 20 is an insulation resin base layer. Due to the adhesiveness of the resin, when the resin is formed in the first electrode groove 111 of the metal substrate 10, the resin can be well bonded to the metal substrate 10, and the structural strength of the metal substrate 10 can be improved.
Preferably, the insulation base layer 20 is an insulation epoxy resin base layer, and epoxy resin can be well combined with encapsulation resin. Thus, the hermeticity of the chip package carrier 100 can be improved.
In order to further understand the technical solution of the present invention, the present invention further provides a method for manufacturing a chip package carrier 100.
The method for manufacturing the chip package carrier 100 according to an embodiment of the utility model includes:
step S10: a metal substrate 10 is provided, and a shielding film 50 is attached to the second side surface 12. Wherein, there can not be the bubble cavity between metal substrate 10 and the shielding film 50, and the shielding film 50 guarantees to be smooth and not to have the fold, not damaged. Specifically, the metal substrate 10 is a copper foil.
Step S11: the first photosensitive film layer 41 is coated and patterned on the first side 11 of the metal substrate 10. The exposed metal substrate has a clean surface and neat pattern edges.
Step S12: the metal substrate 10 exposed on the metal substrate 10 is etched by an acidic etching solution, the metal substrate 10 is left under the protection of the first photosensitive film layer 41 to form a first electrode groove 111, and then the first electrode groove 111 is filled with an insulating resin by an electroplating method to form an insulating base layer 20. Wherein the height of the insulation base layer 20 cannot exceed the depth of the first electrode groove 111.
Step S13: the first photosensitive film layer 41 coated in step S11 is removed by strong alkali to expose the metal substrate 10, so as to form a bottom electrode, and a first plated metal layer 112 is formed on the surface of the bottom electrode by electroplating. The first plating metal layer 112 is gold, silver, nickel, copper, tin, palladium or an alloy thereof.
Step S14: the peelable high temperature resistant carrier sheet 30 is attached to the surface of the first plating metal layer 112. The high temperature resistant bearing sheet 30 is a PI film resistant to 300 degrees of temperature, and the high temperature resistant bearing sheet 30 is attached to ensure flatness without wrinkles and damage.
Step S15: the masking film 50 of the second side surface 12 is removed. Wherein it is desirable to keep the second side 12 surface clean.
Step S16: a second photosensitive film layer 42 is applied and patterned on the second side 12. The exposed metal substrate 10 has a clean surface and regular pattern edges.
Step S17: the exposed metal substrate 10 is etched by acidic etching liquid, and the metal substrate 10 is remained under the protection of the second photosensitive film layer 42 to form a top electrode. Wherein the etching depth is based on exposing the insulation base layer 20.
Step S18: the second photosensitive film layer 42 coated in step S16 is removed by strong alkali to expose the bottom electrode, and a second plated metal layer 122 is formed on the surface of the bottom electrode by electroplating. The second plating metal layer 122 is gold, silver, nickel, copper, tin, palladium or an alloy thereof.
The method for manufacturing the chip package carrier 100 according to another embodiment of the utility model includes:
step S10: a metal substrate 10 is provided, and a shielding film 50 is attached to the second side surface 12. Wherein, there can not be the bubble cavity between metal substrate 10 and the shielding film 50, and the shielding film 50 guarantees to be smooth and not to have the fold, not damaged. Specifically, the metal substrate 10 is a copper foil.
Step S11: the first photosensitive film layer 41 is coated and patterned on the first side 11 of the metal substrate 10. The exposed metal substrate 10 has a clean surface and regular pattern edges.
Step S12: the metal substrate 10 exposed on the metal substrate 10 is etched by an acidic etching solution, the metal substrate 10 is left under the protection of the first photosensitive film layer 41 to form a first electrode groove 111, and then the first electrode groove 111 is filled with an insulating resin by an electroplating method to form an insulating base layer 20. Wherein the height of the insulation base layer 20 cannot exceed the depth of the first electrode groove 111.
Step S13: the first photosensitive film layer 41 coated in step S11 is removed by strong alkali to expose the metal substrate 10, so as to form a bottom electrode, and a first plated metal layer 112 is formed on the surface of the bottom electrode by electroplating. The first plating metal layer 112 is gold, silver, nickel, copper, tin, palladium or an alloy thereof.
Step S14: the peelable high temperature resistant carrier sheet 30 is attached to the surface of the first plating metal layer 112. The high temperature resistant bearing sheet 30 is a PI film resistant to 300 degrees of temperature, and the high temperature resistant bearing sheet 30 is attached to ensure flatness without wrinkles and damage.
Step S15: the masking film 50 of the second side surface 12 is removed. Wherein it is desirable to keep the second side 12 surface clean.
Step S16: a second photosensitive film layer 42 is coated and patterned on the second side 12 of the metal substrate 10. The exposed metal substrate 10 has a clean surface and regular pattern edges.
Step S17: a second metal layer 122 is formed on the second side 12 of the metal substrate 10 by electroplating. The second plating metal layer 122 is gold, silver, nickel, copper, tin, palladium or an alloy thereof.
Step S18: the second photosensitive film layer 42 applied at step S16 is removed with strong alkali to expose the metal substrate 10.
Step S19: the exposed metal substrate 10 is etched by an alkaline etching solution, and the metal substrate 10 forms a mushroom head "T" structure under the protection of the second plating metal layer 122. Wherein the etching depth is based on the exposure of the insulating resin 20.
Compared with the prior art, the chip package carrier 100 provided in the embodiment of the present application has the following beneficial effects:
(1) the first side surface 11 and the second side surface 12 opposite to the first side surface 11 of the metal substrate 10 are respectively provided with the plurality of first electrode grooves 111 and the plurality of second electrode grooves 112, so that the bottom electrode and the top electrode of the chip package carrier 100 are not limited by the shape and size, and the freedom of engineering design such as the line width and wiring of the chip package carrier 100 is improved.
(2) According to the chip packaging carrier plate 100 processed by the etching process, metal connecting ribs are not generated between the bottom electrode and the top electrode, the electrodes are freely distributed, and the cutting efficiency and the cutting speed of the packaged chip can be improved. The first plating metal layer 112 is covered with a peelable high temperature resistant carrier sheet, which can prevent glue overflow during packaging and reduce post-treatment processes after packaging and injection molding.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A chip package carrier board, comprising:
the metal substrate is provided with a first side surface and a second side surface opposite to the first side surface, and the first side surface is provided with a plurality of first electrode grooves;
an insulating base layer formed in the plurality of first electrode grooves;
the second side surface is provided with a plurality of second electrode grooves, and the plurality of second electrode grooves correspond to the plurality of first electrode grooves one to one;
the bottom of each second electrode groove is provided with a communication hole communicated with the corresponding first electrode groove, and the insulation base layer covers all the communication holes.
2. The chip package carrier according to claim 1, wherein at least one of the first electrode grooves has an opening with a shape different from that of the corresponding second electrode groove; and/or
The opening area of at least one first electrode groove is different from the opening area of the corresponding second electrode groove.
3. The chip package carrier according to claim 1, wherein the first side has a first metal layer formed thereon, and the second side has a second metal layer formed thereon.
4. The chip package carrier according to claim 3, wherein the first plating metal layer and the second plating metal layer are gold, silver, nickel, copper, tin, palladium or alloys thereof.
5. The chip package carrier according to claim 3, wherein the first plated metal layer is covered with a peelable high temperature resistant carrier.
6. The chip package carrier according to claim 1, wherein the thickness of the insulation base layer is smaller than the groove depth of the first electrode groove.
7. The chip package carrier according to claim 1, wherein the metal substrate is a copper foil.
8. The chip package carrier according to claim 1, wherein the insulation base layer is an insulation resin base layer.
9. The chip package carrier according to claim 1, wherein the first side has a first etching area, and the plurality of first electrode grooves are formed in the first etching area by etching;
the second side surface is provided with a second etching area, and the plurality of second electrode grooves are formed in the second etching area in an etching mode.
10. The chip package carrier according to claim 9, further comprising a peelable first photosensitive film layer formed on the first side, wherein the first etching area is formed by patterning the first photosensitive film layer;
the chip packaging carrier plate further comprises a second strippable photosensitive film layer, the second photosensitive film layer is formed on the second side face, and the second etching area is formed by patterning the second photosensitive film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122016792.XU CN216054652U (en) | 2021-08-25 | 2021-08-25 | Chip package carrying plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122016792.XU CN216054652U (en) | 2021-08-25 | 2021-08-25 | Chip package carrying plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216054652U true CN216054652U (en) | 2022-03-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122016792.XU Active CN216054652U (en) | 2021-08-25 | 2021-08-25 | Chip package carrying plate |
Country Status (1)
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| CN (1) | CN216054652U (en) |
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2021
- 2021-08-25 CN CN202122016792.XU patent/CN216054652U/en active Active
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