TWI221011B - Method for making a package substrate without etching metal layer on side walls of die cavity and structure from the same - Google Patents
Method for making a package substrate without etching metal layer on side walls of die cavity and structure from the same Download PDFInfo
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- TWI221011B TWI221011B TW091115136A TW91115136A TWI221011B TW I221011 B TWI221011 B TW I221011B TW 091115136 A TW091115136 A TW 091115136A TW 91115136 A TW91115136 A TW 91115136A TW I221011 B TWI221011 B TW I221011B
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- cavity
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- metal layer
- layer
- side wall
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
、.一;、 j yCj #£91115136 年 月 曰 修正 五、發明說明（1) 【發明所屬之技術領域】 ^本發明係有關於一種半導體封裝基板之製造方法，特 別係有關於一種晶穴朝下〔cavi ty—d〇wri〕封裝基板之製 造方法，以防止蝕除晶穴側壁上金屬層。 【先前技術】 一般常見之半導體封裝結構係為晶穴朝下〔cavi ty down〕之球格陣列封裝結構〔Ball Grid Array package〕’簡稱為晶穴朝丁BGA封裝，如美國專利第5,834,839與6,084,777號，晶穴朝下BGA封裝之基本架構 係如第1圖所示，其係在一散熱片i 〇〔 heat spreade]r〕上 黏设有一具開孔21之電路基板2〇，由電路基板2〇之開孔2i 與政熱片10形成一晶穴〔die cavity〕，以黏設一半導體 晶片30於該晶穴，並將一封膠體4〇形成於該晶穴，以密封 晶片30與電性連接之焊線31，而在電路基板2〇之外表面22 係形成有焊球23。 ^ 然而此一適用於晶穴朝下BGA封裝之電路基板20習知 係為一印刷電路板，如FR —4、FR — 5或”樹脂等玻璃纖維強 化樹脂’其形成有單層或多層之電路圖案層，基於訊號傳 遞或電路設計之需求，特別在高頻之設計，電路基板2〇在 晶穴側壁需要形成有一金屬層〔metal layer〕〔圊未繪 出〕’以作為晶片之接地電位連接，然而就一般而言，在 此種半導體封裝之電路基板2 〇之製造過程中，在晶穴側壁 之金屬層係會被不當蝕除，為了避免蝕除晶穴側壁上金屬 層’一種習知電路基板之製造方法係為鍍金製程〔G〇 1(1 Plating Process〕，首先係在電路基板上直接撈出大面、 1 ;, j yCj # £ 91115136 Revised January 5, V. Description of the Invention (1) [Technical Field to which the Invention belongs] ^ The present invention relates to a method for manufacturing a semiconductor package substrate, and particularly relates to a cavity facing The following [cavi ty-dwwri] manufacturing method of the packaging substrate to prevent the metal layer on the sidewall of the cavity from being etched. [Prior technology] A common semiconductor package structure is a cavi ty down ball grid array package structure [Ball Grid Array package], which is abbreviated as a cavity facing BGA package, such as US Patent Nos. 5,834,839 and 6,084,777 No., the basic structure of the BGA package with the cavity facing down is shown in Figure 1. It is a circuit board 20 with an opening 21 attached to a heat sink i 0 [heat spreade] r. The opening 2i of 20 forms a die cavity with the thermal sheet 10 to attach a semiconductor wafer 30 to the cavity, and a colloid 40 is formed in the cavity to seal the wafer 30 and Electrically connected bonding wires 31 are formed with solder balls 23 on the outer surface 22 of the circuit board 20. ^ However, this circuit board 20, which is suitable for the BGA package with the cavity facing down, is conventionally a printed circuit board, such as FR-4, FR-5, or "fiber-reinforced resin such as" resin ", which is formed with a single layer or multiple layers. The circuit pattern layer is based on the requirements of signal transmission or circuit design, especially in high-frequency design. The circuit substrate 20 needs to have a metal layer [metal layer] [〕 not shown] 'on the side wall of the cavity as the ground potential of the wafer. However, in general, in the manufacturing process of such a semiconductor package circuit substrate 20, the metal layer on the side wall of the cavity will be etched improperly. In order to avoid the metal layer on the side wall of the cavity, it is a custom It is known that the manufacturing method of the circuit board is a gold plating process [G〇1 (1 Plating Process)]. First, the large surface is directly taken out from the circuit board.
1221011 修正 魏91115136 年月 日 五、發明說明（2) 積之貫通晶穴，並電鍍上一銅層於該電路基板之上下表面 及其to穴之側壁’再覆蓋上乾膜〔dry f i丨m〕，並對該乾 膜$行曝光顯影工程，而顯露出預定形成線路位置及晶穴 側f ’之後’電鍍一鎳/金層使其形成於上述該些顯露之 預定線路位置以及晶穴側壁，再移除該乾膜之後，以該鎳 /金胃層作為抗姓刻之保護層，在銅蝕刻過程，將形成線路 與aa八側壁之金屬層，之後，再塗佈一防銲層於該電路基 板之上表面與下表面，由於該鎳/金層係以選擇性電鍍方 式預先形成在晶穴側壁之金屬層以及上下表面之全部線路 之顯露表面，將增加製程之複雜及困難度，且因基板之線 ，全電鍍有鎳/金，故成本較高，在實際生產上，信賴性 與良率亦較差。 【發明内容】 么思本發明之主要目的在於提供一種防止餘除晶穴侧壁上 # π，之^裝基板製造方法，其係在基板形成貫通槽孔， 1 = f已疋義之晶穴區域内形成一支撐體，以供防蝕層遮 敝该貫通槽孔，防止晶穴側壁之金屬層被不當蝕刻。 令厘本發月之次一目的在於提供一種防止餘除晶穴側壁上 f之封裝基板製造方法，以較經濟方式製造半導體封 板’其晶穴之側壁係具有金屬層。 明之再一目的在於提供一種半導體封裝基板，適 績^ Γ穴朝下之球格陣列封裝，其晶穴之側壁係具有非連 接地傳S層，其係由移除支撐體後成形，以作為一晶片之1221011 Rev. Wei, 91115136 5. Description of the invention (2) A through hole is formed, and a copper layer is plated on the upper and lower surface of the circuit substrate and the side wall of the to hole, and then covered with a dry film [dry fi 丨 m ], And expose the dry film to the development process, and expose the planned circuit position and the cavity side f 'after', electroplating a nickel / gold layer to form the above-mentioned exposed predetermined circuit positions and the sidewall of the cavity After removing the dry film, the nickel / gold stomach layer is used as a protective layer to resist engraving. During the copper etching process, a metal layer of the circuit and the aa eight side walls is formed, and then a solder resist is applied on the The upper and lower surfaces of the circuit substrate, because the nickel / gold layer is formed in advance by selective plating on the side wall of the cavity and the exposed surfaces of all the lines on the upper and lower surfaces, will increase the complexity and difficulty of the process. And because the substrate line, full plating with nickel / gold, so the cost is higher, in actual production, reliability and yield are also poor. [Summary of the invention] The main purpose of the present invention is to provide a method for manufacturing a substrate on the side wall of a cavity to prevent residues. The method is to form a through slot in the substrate, and 1 = the area of the cavity of the righteousness. A support body is formed inside for the anti-corrosion layer to cover the through slot and prevent the metal layer on the side wall of the cavity from being etched improperly. The second purpose of this month is to provide a method for manufacturing a package substrate that prevents f on the side wall of the cavity, and to manufacture the semiconductor package board in a more economical manner. The side wall of the cavity has a metal layer. Another purpose of the Ming is to provide a semiconductor package substrate suitable for a ball grid array package with a Γ cavity facing down. The side wall of the cavity has a non-connected ground pass S layer, which is formed by removing the support body as a One chip
第6頁 1221011Page 6 1221011
造方法， 穴區域形 其寬度約 成形於該 面與貫通 防姓層貼 貫通槽孔 層，之後 與支撐體 【實施方 首先進行基板之第一次形體加工，在已定義之晶 成至少一狹長之貫通槽孔，如直線槽或L形槽， 在0·1〜4.〇fflffl，使得在該晶穴區域内具有一一體 基板之支撐體，之後，形成金屬層於該基板上表 槽孔之側壁，接著形成一防蝕層於該金屬層，當 附，金屬層，該防蝕層在支撐體之支撐下密封該 ’可避免姓刻液侵入貫通槽孔而蝕除侧壁之金屬 ’進彳^基板之第二次形體加工，其係移除防蝕層 ’以構成一在晶穴側壁具有金屬層之電路基板。 式】The manufacturing method is to form a cavity region whose width is approximately formed on the surface and to pass through the slot layer through the penetration prevention layer, and then with the support body [the implementation body first performs the first shape processing of the substrate, and forms at least one narrow length in the defined crystal. A through slot, such as a linear slot or an L-shaped slot, in the range of 0.1 to 4.0 fflffl, so that there is an integrated substrate support in the cavity area, and then a metal layer is formed on the substrate surface groove An anti-corrosion layer is then formed on the side wall of the hole. When attached, the metal layer is sealed under the support of the support body to prevent the 'etching liquid from penetrating through the slot and eroding the metal on the side wall'.彳 ^ The second physical processing of the substrate is to remove the anti-corrosion layer to form a circuit substrate having a metal layer on the side wall of the cavity. formula】
明參閱所附圖式，本發明將列舉以下之實施例說明：Referring to the attached drawings, the present invention will enumerate the following embodiments:
、 依本發明之防止蝕除晶穴侧壁上金屬層之封裝基板製 造方法’如第2圖所示，半導體封裝基板係為一電路基板 60丄如FR-4、FR-5或BT樹脂等玻璃纖維強化樹脂為主體之 銅治基板’該電路基板6 〇係適用於晶穴朝下之半導體封裝 結構，該電路基板60係具有一上表面61、一下表面62及貫 穿上表面61與下表面62之晶穴66，並在電路基板60之下表 面62黏設一散熱片50，該晶穴66之尺寸應略大於晶片90， 係用以容置晶片9 0，晶片9 0係裝設於該電路基板6 〇之晶穴 6 6並以晶片9 0之背面黏設該散熱片5 〇，複數個焊線91係供 電性連接在晶片90之主動面之焊墊與電路基板6〇之電路圖 案層71〔 circuit pattern〕，該電路圖案層71係形成於 電路基板60之上表面61其係電性導接焊線91與在上表面61 之焊球93〔solder ball〕，該焊球93係為鉛錫合金或其 它導接物，如插針〔pin〕等，通常在晶穴66處係以壓模2. The manufacturing method of the package substrate for preventing the metal layer on the side wall of the cavity according to the present invention, as shown in FIG. 2, the semiconductor package substrate is a circuit substrate 60, such as FR-4, FR-5, or BT resin, etc. Glass fiber reinforced resin as the main body of the copper substrate 'The circuit board 60 is suitable for semiconductor packaging structure with the cavity facing down, and the circuit board 60 has an upper surface 61, a lower surface 62, and penetrates the upper surface 61 and the lower surface Cavity 66 of 62, and a heat sink 50 is adhered on the surface 62 of the lower surface of the circuit substrate 60. The size of the cavity 66 should be slightly larger than the wafer 90, which is used to accommodate the wafer 90, and the wafer 90 is mounted on The circuit board 60 has a cavity 66, and the heat sink 50 is adhered to the back of the chip 90. A plurality of bonding wires 91 are electrically connected to the pads on the active surface of the chip 90 and the circuit of the circuit board 60. A pattern layer 71 [circuit pattern], which is formed on the upper surface 61 of the circuit substrate 60, which is an electrically conductive bonding wire 91 and a solder ball 93 on the upper surface 61, the solder ball 93 It is a lead-tin alloy or other conductive materials, such as pins, etc. Die 66
12210111221011
〔molding〕或填塗〔potting〕方法在晶穴66形成一封膠 體92，該電路基板6〇在晶穴66之側壁67係形成有一金屬層 70，如電鍍銅層，用以電性連接至該晶片9〇之接地電位 〔ground potential〕〔圖未繪出〕，供訊號傳輸，並可 阻絕晶片90與電路基板60之訊號干擾，減少串訊現象，較 佳地’在側壁67之金屬層70上遮蔽有一表面處理層69，如-鎳-金層〔Ni-Au〕，以避免在側壁67之金屬層7〇氧化，此 外’在電路基板60之上表面61及電路圖案層71上係形成有 一絕緣保護層68 ’如防焊漆〔solder resist〕或保護膠 膜〔cover layer〕，其係覆蓋該電路圖案層η。 _ 上述封裝基板之製造流程係如第3A至311圖所示，如第 3A圖所示，首先提供一基板60，該基板6〇係具有一上表面 61、一下表面62及一已定義之晶穴區域63 ,該晶穴區域63 係略大於晶片9 0之尺寸，該基板6 〇係可為一單層印刷電路 板或多層印刷電路板，其内部電路可預先以圖案電鑛方法 〔pattern plating method〕或減去蝕刻方法 〔subtractive etching method〕成形；如第 3B 及4 圖所 示’在上述晶穴區域6 3周邊以切割或沖、銑〔p u n c h〕方 式形成至少一貫通槽孔6 4，在本實施例中，貫通槽孔6 4係 呈直線槽，且貫穿該基板60之上表面61與下表面62，使得藝 在該基板60之晶穴區域63内形成為一暫時性且一艘成形於 該基板6 0之支撲體6 5，該支撲體6 5係被至少一銜接部6 51 連接於該基板60，較佳地，該貫通槽孔64之寬度係介於〇. 1〜4.0mm之間；再如第3C圖所示，以電極電鍵 〔electroplating〕、無電極電鍍〔electroless[Molding] or potting [potting] method to form a colloid 92 in the cavity 66, the circuit substrate 60 on the side wall 67 of the cavity 66 is formed with a metal layer 70, such as electroplated copper layer, for electrical connection to The ground potential of the chip 90 (not shown in the figure) is used for signal transmission, and can prevent the signal interference between the chip 90 and the circuit substrate 60, reducing crosstalk, and preferably 'the metal layer on the side wall 67 A surface treatment layer 69, such as a nickel-gold layer [Ni-Au], is shielded on 70 to avoid oxidation of the metal layer 70 on the side wall 67. In addition, the surface 61 and the circuit pattern layer 71 are mounted on the circuit substrate 60. An insulating protective layer 68 'is formed, such as a solder resist or a cover layer, which covers the circuit pattern layer η. _ The manufacturing process of the above package substrate is shown in Figures 3A to 311. As shown in Figure 3A, a substrate 60 is provided first. The substrate 60 has an upper surface 61, a lower surface 62, and a defined crystal. The cavity area 63 is slightly larger than the size of the wafer 90. The substrate 60 can be a single-layer printed circuit board or a multilayer printed circuit board. The internal circuit can be pre-patterned with a pattern plating method [pattern plating]. method] or subtracting the etching method [subtractive etching method] forming; as shown in Figures 3B and 4 ', at least one through slot 6 4 is formed by cutting, punching, or milling around the above-mentioned cavity region 6 3, In this embodiment, the through-slots 64 are linear grooves and penetrate the upper surface 61 and the lower surface 62 of the substrate 60, so that the technique is formed into a temporary and a ship in the cavity region 63 of the substrate 60. 1 Branch body 6 5 formed on the substrate 60, which is connected to the substrate 60 by at least one engagement portion 6 51, preferably, the width of the through slot 64 is between 0.1 ~ 4.0mm; and then as shown in Figure 3C, the electrode key [elect roplating], electrodeless
I2210H __案號 9111513R_^ % B 修正 五、發明說明（5) plating〕、真空蒸鑛〔evap〇rati〇n〕、濺鑛 〔sputtering〕或沉積〔deposition〕等技術形成一金屬 層70〔如銅、鋁或金〕於該基板60之上表面61、下表面62 與貫通槽孔6 4之側壁6 7 ;之後，如第3 D圖所示，以壓合貼 附等方式形成一防蝕層80於該金屬層70，在本實施例中， a亥防触層80係為感光型乾膜〔dry film〕，由於防蚀層80 亦貼附於支撐體65，在支撐體65之支撐下，故該防蝕層80 係能遮蔽該貫通槽孔64，而達到密封該貫通槽孔64之目 的’以保護在貫通槽孔64内側壁6 7之金屬層70不被蝕除； 再如第3 E圖所示’以曝光顯影等技術〔e X p 〇 s u r e & development〕圖案化該防蝕層8〇，以得到一預定之囷案 化後之防ϋ層8 0，該圖案化防蝕層8 〇係覆蓋預定保留線路 之位置；如第3F圖所示，藉由該圖案化後之防蝕層8〇作為 姓刻保護層而蝕刻在該基板6〇表面之金屬層7〇，以使該基 板6 0表面之金屬層70形成電路圖案層71。由於蝕刻時該圖 ，化後之防蝕層80係遮蔽該貫通槽孔64，氣化鐵养氣化銅 等餘刻液不會侵入貫通槽孔64，在貫通槽孔64側壁67之金 屬層70係不會被不當蝕除；再如第3G圖所示，移除該圖案 化後之防蝕層80，最後，如第3H及4圖所示，沿基板6〇之 銜接部651移除該支撐體65，並以噴塗、印刷或壓合等方 式形成一絕緣保護層68於該基板60之上表面61及電路圖案 層71上，如防焊漆〔solder resist〕或保護膠膜〔c〇ver layer〕，以製造上述如第2圖所示之電路基板6〇，較佳 地’以電鍍方式在側壁67之金屬層7〇上形成一如鎳—金之 表面處理層69，以防止側壁67之金屬層70氧化，該電路基I2210H __Case No. 9111513R_ ^% B Revision V. Description of the Invention (5) plating], vacuum evaporation [evap〇rati〇n], sputtering (deposition) or deposition [deposition] and other technologies to form a metal layer 70 [such as Copper, aluminum, or gold] on the upper surface 61, lower surface 62 of the substrate 60, and the side wall 6 7 of the through slot 64; after that, as shown in FIG. 3D, an anti-corrosion layer is formed by pressure bonding and the like. 80 is on the metal layer 70. In this embodiment, the contact prevention layer 80 is a photosensitive dry film. Since the anti-corrosion layer 80 is also attached to the support 65, it is supported by the support 65. Therefore, the anti-corrosion layer 80 can shield the through slot 64 and seal the through slot 64 to protect the metal layer 70 on the inner wall 67 of the through slot 64 from being etched. As shown in the figure E, the anti-corrosion layer 80 is patterned by techniques such as exposure and development [e X p osure & development] to obtain a predetermined anti-corrosion layer 80, which is patterned. 〇 Covers the position of the reserved line; as shown in Figure 3F, the patterned anti-corrosion layer 80 is used as the last name. Covering the metal layer in the etched surface of the substrate 7〇 6〇, so that the substrate 60 of the surface of the metal layer 70 forming a circuit pattern layer 71. Due to the figure during etching, the anti-corrosion layer 80 is used to shield the through-slot 64, and the remaining liquids such as vaporized iron and copper are not penetrated into the through-slot 64. The metal layer 70 on the side wall 67 of the through-slot 64 It will not be etched improperly; as shown in FIG. 3G, the patterned anti-corrosion layer 80 is removed. Finally, as shown in FIGS. 3H and 4, the support body is removed along the connecting portion 651 of the substrate 60. 65, and an insulating protection layer 68 is formed on the upper surface 61 of the substrate 60 and the circuit pattern layer 71 by spraying, printing or laminating, such as solder resist or protective film ] To manufacture the above-mentioned circuit substrate 60 as shown in FIG. 2, it is preferable to form a surface treatment layer 69 such as nickel-gold on the metal layer 70 of the side wall 67 by electroplating to prevent the The metal layer 70 is oxidized and the circuit base
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第9頁 1221011 案號 91115136Page 9 1221011 Case number 91115136
五、發明說明（6) 板6 0係形成有一用以容置晶 該晶穴66之側壁67係形成有 會被蝕除。 片之晶穴66 〔die cavity〕， 非連續狀之金屬層70，其係不 依本發明之 造方法，在形成 貫通槽孔64之外 晶穴區域63周邊 示同時形成有直 如U形貫通槽孔 故本發明之 者為準，任何熟 範圍内所作之任 圍。 = 示晶穴侧壁上金屬層之封裝基板製 貫通：孔64之步驟中，除了可形成直線之 ，如第5圖所示，亦可在基板60之已定義 形成L形之貫通槽孔64a，或者如第6圖所 線之貫通槽孔64與L形之貫通槽孔64a， 、圖未緣出〕。 保護範圍當視後附之申請專利範圍 知此項技藝者，在不脫離本發明之神 何變化與修改，均屬於本發明之保護範 1221011 91115136--月 日 條正 -- —* ' -----— 圖式簡單說明 【圖式簡單說明】 第1 圖：習知晶穴朝下之BGA封裝結構之截面示意 圖； ^ 第2 圖：依照本發明’所提供之晶穴朝下之BGA封裝 結構之截面示意圖； 第3A至3H圖：依照本發明之防止蝕除晶穴側壁上金屬層之 封裝基板製造方法，在製造過程中該基板之 截面示意圖； 第4 圖：依照本發明之防止蝕除晶穴侧壁上金屬層之V. Description of the invention (6) The plate 60 is formed with a wall 67 for accommodating crystals. The side wall 67 of the crystal cavity 66 is formed and will be eroded. Die cavity 66 [die cavity], a discontinuous metal layer 70, which is not in accordance with the manufacturing method of the present invention, and a straight U-shaped through groove is formed at the periphery of the cavity area 63 outside the through groove 64 Therefore, the person in charge of the present invention shall prevail, and any tasks made within the scope of this document shall be deemed to be accurate. = Shows the through-hole of the package substrate of the metal layer on the side wall of the cavity: In the step of hole 64, in addition to forming a straight line, as shown in FIG. 5, an L-shaped through-hole 64a can also be formed on the substrate 60. Or, as shown in FIG. 6, the through slot 64 and the L-shaped through slot 64a are not shown in the figure]. The scope of protection should be based on the scope of the patent application attached. Those skilled in the art, without departing from the spirit of the invention, are all within the scope of protection of the invention 1221011 91115136-the day of the month--* '- ----- Brief description of the drawings [Simplified description of the drawings] Figure 1: A cross-sectional view of a conventional BGA package structure with a crystal cavity facing down; ^ Figure 2: A BGA package structure with a crystal cavity facing down according to the present invention Sectional schematic diagrams; FIGS. 3A to 3H: A method for manufacturing a package substrate for preventing a metal layer on a sidewall of a cavity according to the present invention, a schematic sectional view of the substrate during the manufacturing process; FIG. 4: Erosion prevention according to the present invention Metal layer on the side wall of the cavity
封裝基板製造方法，形成有狹長貫通槽孔之 基板立體示意圖； 第5 圖：依照本發明之防止蝕除晶穴側壁上金屬層之 封裝基板製造方法，在第二具體實施例中形 成有狹長貫通槽孔之基板頂面示意圖；及 第6 圖·依照本發明之防止钱除晶穴側壁上金屬層之 封裝基板製造方法，在第三具體實施例中形 成有狹長貫通槽孔之基板頂面示意圖。 元件符號簡單說明： 電路基板 21 晶穴 焊球 24 側壁 焊線 40 封膠體 電路基板 61 上表面 晶穴區域 64 貫通槽孔 支撐體 651 銜接部 10 散熱片 20 22 外表面 23 3 0 晶片 31 5 0 散熱片 60 62 下表面 μ 64a貫通槽孔Packaging substrate manufacturing method, a schematic perspective view of a substrate with narrow through-holes formed; Figure 5: A method for manufacturing a packaging substrate for preventing the metal layer on the side wall of a cavity according to the present invention, forming a narrow through-hole in a second embodiment Schematic diagram of the top surface of the substrate of the slot; and FIG. 6 · Schematic diagram of the top surface of the substrate with a narrow through slot in the third embodiment according to the method for manufacturing a package substrate for preventing the metal layer on the side wall of the cavity according to the present invention . Brief description of the component symbols: Circuit board 21 Cavity solder ball 24 Side wall bonding wire 40 Sealed circuit board 61 Upper surface cavity area 64 Through slot support 651 Joint 10 Heat sink 20 22 Outer surface 23 3 0 Wafer 31 5 0 Heat sink 60 62 lower surface μ 64a through slot
第11頁 1221011 案號 91115136 曰 修正 圖式簡單說明 66 晶穴 67 側壁 68 絕緣保護層 69 70 金屬層 71 電路圖案層 80 防触層 90 晶片 91 92 封膠體 93 焊球 表面處理層 焊線 第12頁Page 11 1221011 Case No. 91115136 Brief description of the amendments 66 Cavity 67 Side wall 68 Insulation protection layer 69 70 Metal layer 71 Circuit pattern layer 80 Anti-contact layer 90 Chip 91 92 Sealant 93 Solder ball surface treatment layer Welding wire No. 12 page
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091115136A TWI221011B (en) | 2002-07-03 | 2002-07-03 | Method for making a package substrate without etching metal layer on side walls of die cavity and structure from the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091115136A TWI221011B (en) | 2002-07-03 | 2002-07-03 | Method for making a package substrate without etching metal layer on side walls of die cavity and structure from the same |
Publications (1)
| Publication Number | Publication Date |
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| TWI221011B true TWI221011B (en) | 2004-09-11 |
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| TW091115136A TWI221011B (en) | 2002-07-03 | 2002-07-03 | Method for making a package substrate without etching metal layer on side walls of die cavity and structure from the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI393667B (en) * | 2010-02-04 | 2013-04-21 | Unimicron Technology Corp | Method for forming a lid member on mems device |
| TWI398401B (en) * | 2009-11-20 | 2013-06-11 | Unimicron Technology Corp | Lid, fabricating method thereof, and mems package made thereby |
-
2002
- 2002-07-03 TW TW091115136A patent/TWI221011B/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI398401B (en) * | 2009-11-20 | 2013-06-11 | Unimicron Technology Corp | Lid, fabricating method thereof, and mems package made thereby |
| TWI393667B (en) * | 2010-02-04 | 2013-04-21 | Unimicron Technology Corp | Method for forming a lid member on mems device |
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